dts/upstream/src/riscv/microchip/mpfs.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
   3
   4 /dts-v1/;
   5 #include "dt-bindings/clock/microchip,mpfs-clock.h"
   6
   7 / {
   8         #address-cells = <2>;
   9         #size-cells = <2>;
  10         model = "Microchip PolarFire SoC";
  11         compatible = "microchip,mpfs";
  12
  13         cpus {
  14                 #address-cells = <1>;
  15                 #size-cells = <0>;
  16                 timebase-frequency = <1000000>;
  17
  18                 cpu0: cpu@0 {
  19                         compatible = "sifive,e51", "sifive,rocket0", "riscv";
  20                         device_type = "cpu";
  21                         i-cache-block-size = <64>;
  22                         i-cache-sets = <128>;
  23                         i-cache-size = <16384>;
  24                         reg = <0>;
  25                         riscv,isa = "rv64imac";
  26                         riscv,isa-base = "rv64i";
  27                         riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",
  28                                                "zihpm";
  29                         clocks = <&clkcfg CLK_CPU>;
  30                         status = "disabled";
  31
  32                         cpu0_intc: interrupt-controller {
  33                                 #interrupt-cells = <1>;
  34                                 compatible = "riscv,cpu-intc";
  35                                 interrupt-controller;
  36                         };
  37                 };
  38
  39                 cpu1: cpu@1 {
  40                         compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
  41                         d-cache-block-size = <64>;
  42                         d-cache-sets = <64>;
  43                         d-cache-size = <32768>;
  44                         d-tlb-sets = <1>;
  45                         d-tlb-size = <32>;
  46                         device_type = "cpu";
  47                         i-cache-block-size = <64>;
  48                         i-cache-sets = <64>;
  49                         i-cache-size = <32768>;
  50                         i-tlb-sets = <1>;
  51                         i-tlb-size = <32>;
  52                         mmu-type = "riscv,sv39";
  53                         reg = <1>;
  54                         riscv,isa = "rv64imafdc";
  55                         riscv,isa-base = "rv64i";
  56                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
  57                                                "zifencei", "zihpm";
  58                         clocks = <&clkcfg CLK_CPU>;
  59                         tlb-split;
  60                         next-level-cache = <&cctrllr>;
  61                         status = "okay";
  62
  63                         cpu1_intc: interrupt-controller {
  64                                 #interrupt-cells = <1>;
  65                                 compatible = "riscv,cpu-intc";
  66                                 interrupt-controller;
  67                         };
  68                 };
  69
  70                 cpu2: cpu@2 {
  71                         compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
  72                         d-cache-block-size = <64>;
  73                         d-cache-sets = <64>;
  74                         d-cache-size = <32768>;
  75                         d-tlb-sets = <1>;
  76                         d-tlb-size = <32>;
  77                         device_type = "cpu";
  78                         i-cache-block-size = <64>;
  79                         i-cache-sets = <64>;
  80                         i-cache-size = <32768>;
  81                         i-tlb-sets = <1>;
  82                         i-tlb-size = <32>;
  83                         mmu-type = "riscv,sv39";
  84                         reg = <2>;
  85                         riscv,isa = "rv64imafdc";
  86                         riscv,isa-base = "rv64i";
  87                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
  88                                                "zifencei", "zihpm";
  89                         clocks = <&clkcfg CLK_CPU>;
  90                         tlb-split;
  91                         next-level-cache = <&cctrllr>;
  92                         status = "okay";
  93
  94                         cpu2_intc: interrupt-controller {
  95                                 #interrupt-cells = <1>;
  96                                 compatible = "riscv,cpu-intc";
  97                                 interrupt-controller;
  98                         };
  99                 };
 100
 101                 cpu3: cpu@3 {
 102                         compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
 103                         d-cache-block-size = <64>;
 104                         d-cache-sets = <64>;
 105                         d-cache-size = <32768>;
 106                         d-tlb-sets = <1>;
 107                         d-tlb-size = <32>;
 108                         device_type = "cpu";
 109                         i-cache-block-size = <64>;
 110                         i-cache-sets = <64>;
 111                         i-cache-size = <32768>;
 112                         i-tlb-sets = <1>;
 113                         i-tlb-size = <32>;
 114                         mmu-type = "riscv,sv39";
 115                         reg = <3>;
 116                         riscv,isa = "rv64imafdc";
 117                         riscv,isa-base = "rv64i";
 118                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
 119                                                "zifencei", "zihpm";
 120                         clocks = <&clkcfg CLK_CPU>;
 121                         tlb-split;
 122                         next-level-cache = <&cctrllr>;
 123                         status = "okay";
 124
 125                         cpu3_intc: interrupt-controller {
 126                                 #interrupt-cells = <1>;
 127                                 compatible = "riscv,cpu-intc";
 128                                 interrupt-controller;
 129                         };
 130                 };
 131
 132                 cpu4: cpu@4 {
 133                         compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
 134                         d-cache-block-size = <64>;
 135                         d-cache-sets = <64>;
 136                         d-cache-size = <32768>;
 137                         d-tlb-sets = <1>;
 138                         d-tlb-size = <32>;
 139                         device_type = "cpu";
 140                         i-cache-block-size = <64>;
 141                         i-cache-sets = <64>;
 142                         i-cache-size = <32768>;
 143                         i-tlb-sets = <1>;
 144                         i-tlb-size = <32>;
 145                         mmu-type = "riscv,sv39";
 146                         reg = <4>;
 147                         riscv,isa = "rv64imafdc";
 148                         riscv,isa-base = "rv64i";
 149                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
 150                                                "zifencei", "zihpm";
 151                         clocks = <&clkcfg CLK_CPU>;
 152                         tlb-split;
 153                         next-level-cache = <&cctrllr>;
 154                         status = "okay";
 155                         cpu4_intc: interrupt-controller {
 156                                 #interrupt-cells = <1>;
 157                                 compatible = "riscv,cpu-intc";
 158                                 interrupt-controller;
 159                         };
 160                 };
 161
 162                 cpu-map {
 163                         cluster0 {
 164                                 core0 {
 165                                         cpu = <&cpu0>;
 166                                 };
 167
 168                                 core1 {
 169                                         cpu = <&cpu1>;
 170                                 };
 171
 172                                 core2 {
 173                                         cpu = <&cpu2>;
 174                                 };
 175
 176                                 core3 {
 177                                         cpu = <&cpu3>;
 178                                 };
 179
 180                                 core4 {
 181                                         cpu = <&cpu4>;
 182                                 };
 183                         };
 184                 };
 185         };
 186
 187         refclk: mssrefclk {
 188                 compatible = "fixed-clock";
 189                 #clock-cells = <0>;
 190         };
 191
 192         syscontroller: syscontroller {
 193                 compatible = "microchip,mpfs-sys-controller";
 194                 mboxes = <&mbox 0>;
 195         };
 196
 197         soc {
 198                 #address-cells = <2>;
 199                 #size-cells = <2>;
 200                 compatible = "simple-bus";
 201                 ranges;
 202
 203                 cctrllr: cache-controller@2010000 {
 204                         compatible = "microchip,mpfs-ccache", "sifive,fu540-c000-ccache", "cache";
 205                         reg = <0x0 0x2010000 0x0 0x1000>;
 206                         cache-block-size = <64>;
 207                         cache-level = <2>;
 208                         cache-sets = <1024>;
 209                         cache-size = <2097152>;
 210                         cache-unified;
 211                         interrupt-parent = <&plic>;
 212                         interrupts = <1>, <3>, <4>, <2>;
 213                 };
 214
 215                 clint: clint@2000000 {
 216                         compatible = "sifive,fu540-c000-clint", "sifive,clint0";
 217                         reg = <0x0 0x2000000 0x0 0xC000>;
 218                         interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
 219                                               <&cpu1_intc 3>, <&cpu1_intc 7>,
 220                                               <&cpu2_intc 3>, <&cpu2_intc 7>,
 221                                               <&cpu3_intc 3>, <&cpu3_intc 7>,
 222                                               <&cpu4_intc 3>, <&cpu4_intc 7>;
 223                 };
 224
 225                 plic: interrupt-controller@c000000 {
 226                         compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
 227                         reg = <0x0 0xc000000 0x0 0x4000000>;
 228                         #address-cells = <0>;
 229                         #interrupt-cells = <1>;
 230                         interrupt-controller;
 231                         interrupts-extended = <&cpu0_intc 11>,
 232                                               <&cpu1_intc 11>, <&cpu1_intc 9>,
 233                                               <&cpu2_intc 11>, <&cpu2_intc 9>,
 234                                               <&cpu3_intc 11>, <&cpu3_intc 9>,
 235                                               <&cpu4_intc 11>, <&cpu4_intc 9>;
 236                         riscv,ndev = <186>;
 237                 };
 238
 239                 pdma: dma-controller@3000000 {
 240                         compatible = "sifive,fu540-c000-pdma", "sifive,pdma0";
 241                         reg = <0x0 0x3000000 0x0 0x8000>;
 242                         interrupt-parent = <&plic>;
 243                         interrupts = <5 6>, <7 8>, <9 10>, <11 12>;
 244                         dma-channels = <4>;
 245                         #dma-cells = <1>;
 246                 };
 247
 248                 clkcfg: clkcfg@20002000 {
 249                         compatible = "microchip,mpfs-clkcfg";
 250                         reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>;
 251                         clocks = <&refclk>;
 252                         #clock-cells = <1>;
 253                         #reset-cells = <1>;
 254                 };
 255
 256                 ccc_se: clock-controller@38010000 {
 257                         compatible = "microchip,mpfs-ccc";
 258                         reg = <0x0 0x38010000 0x0 0x1000>, <0x0 0x38020000 0x0 0x1000>,
 259                               <0x0 0x39010000 0x0 0x1000>, <0x0 0x39020000 0x0 0x1000>;
 260                         #clock-cells = <1>;
 261                         status = "disabled";
 262                 };
 263
 264                 ccc_ne: clock-controller@38040000 {
 265                         compatible = "microchip,mpfs-ccc";
 266                         reg = <0x0 0x38040000 0x0 0x1000>, <0x0 0x38080000 0x0 0x1000>,
 267                               <0x0 0x39040000 0x0 0x1000>, <0x0 0x39080000 0x0 0x1000>;
 268                         #clock-cells = <1>;
 269                         status = "disabled";
 270                 };
 271
 272                 ccc_nw: clock-controller@38100000 {
 273                         compatible = "microchip,mpfs-ccc";
 274                         reg = <0x0 0x38100000 0x0 0x1000>, <0x0 0x38200000 0x0 0x1000>,
 275                               <0x0 0x39100000 0x0 0x1000>, <0x0 0x39200000 0x0 0x1000>;
 276                         #clock-cells = <1>;
 277                         status = "disabled";
 278                 };
 279
 280                 ccc_sw: clock-controller@38400000 {
 281                         compatible = "microchip,mpfs-ccc";
 282                         reg = <0x0 0x38400000 0x0 0x1000>, <0x0 0x38800000 0x0 0x1000>,
 283                               <0x0 0x39400000 0x0 0x1000>, <0x0 0x39800000 0x0 0x1000>;
 284                         #clock-cells = <1>;
 285                         status = "disabled";
 286                 };
 287
 288                 mmuart0: serial@20000000 {
 289                         compatible = "ns16550a";
 290                         reg = <0x0 0x20000000 0x0 0x400>;
 291                         reg-io-width = <4>;
 292                         reg-shift = <2>;
 293                         interrupt-parent = <&plic>;
 294                         interrupts = <90>;
 295                         current-speed = <115200>;
 296                         clocks = <&clkcfg CLK_MMUART0>;
 297                         status = "disabled"; /* Reserved for the HSS */
 298                 };
 299
 300                 mmuart1: serial@20100000 {
 301                         compatible = "ns16550a";
 302                         reg = <0x0 0x20100000 0x0 0x400>;
 303                         reg-io-width = <4>;
 304                         reg-shift = <2>;
 305                         interrupt-parent = <&plic>;
 306                         interrupts = <91>;
 307                         current-speed = <115200>;
 308                         clocks = <&clkcfg CLK_MMUART1>;
 309                         status = "disabled";
 310                 };
 311
 312                 mmuart2: serial@20102000 {
 313                         compatible = "ns16550a";
 314                         reg = <0x0 0x20102000 0x0 0x400>;
 315                         reg-io-width = <4>;
 316                         reg-shift = <2>;
 317                         interrupt-parent = <&plic>;
 318                         interrupts = <92>;
 319                         current-speed = <115200>;
 320                         clocks = <&clkcfg CLK_MMUART2>;
 321                         status = "disabled";
 322                 };
 323
 324                 mmuart3: serial@20104000 {
 325                         compatible = "ns16550a";
 326                         reg = <0x0 0x20104000 0x0 0x400>;
 327                         reg-io-width = <4>;
 328                         reg-shift = <2>;
 329                         interrupt-parent = <&plic>;
 330                         interrupts = <93>;
 331                         current-speed = <115200>;
 332                         clocks = <&clkcfg CLK_MMUART3>;
 333                         status = "disabled";
 334                 };
 335
 336                 mmuart4: serial@20106000 {
 337                         compatible = "ns16550a";
 338                         reg = <0x0 0x20106000 0x0 0x400>;
 339                         reg-io-width = <4>;
 340                         reg-shift = <2>;
 341                         interrupt-parent = <&plic>;
 342                         interrupts = <94>;
 343                         clocks = <&clkcfg CLK_MMUART4>;
 344                         current-speed = <115200>;
 345                         status = "disabled";
 346                 };
 347
 348                 /* Common node entry for emmc/sd */
 349                 mmc: mmc@20008000 {
 350                         compatible = "microchip,mpfs-sd4hc", "cdns,sd4hc";
 351                         reg = <0x0 0x20008000 0x0 0x1000>;
 352                         interrupt-parent = <&plic>;
 353                         interrupts = <88>;
 354                         clocks = <&clkcfg CLK_MMC>;
 355                         max-frequency = <200000000>;
 356                         status = "disabled";
 357                 };
 358
 359                 spi0: spi@20108000 {
 360                         compatible = "microchip,mpfs-spi";
 361                         #address-cells = <1>;
 362                         #size-cells = <0>;
 363                         reg = <0x0 0x20108000 0x0 0x1000>;
 364                         interrupt-parent = <&plic>;
 365                         interrupts = <54>;
 366                         clocks = <&clkcfg CLK_SPI0>;
 367                         status = "disabled";
 368                 };
 369
 370                 spi1: spi@20109000 {
 371                         compatible = "microchip,mpfs-spi";
 372                         #address-cells = <1>;
 373                         #size-cells = <0>;
 374                         reg = <0x0 0x20109000 0x0 0x1000>;
 375                         interrupt-parent = <&plic>;
 376                         interrupts = <55>;
 377                         clocks = <&clkcfg CLK_SPI1>;
 378                         status = "disabled";
 379                 };
 380
 381                 qspi: spi@21000000 {
 382                         compatible = "microchip,mpfs-qspi", "microchip,coreqspi-rtl-v2";
 383                         #address-cells = <1>;
 384                         #size-cells = <0>;
 385                         reg = <0x0 0x21000000 0x0 0x1000>;
 386                         interrupt-parent = <&plic>;
 387                         interrupts = <85>;
 388                         clocks = <&clkcfg CLK_QSPI>;
 389                         status = "disabled";
 390                 };
 391
 392                 i2c0: i2c@2010a000 {
 393                         compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7";
 394                         reg = <0x0 0x2010a000 0x0 0x1000>;
 395                         #address-cells = <1>;
 396                         #size-cells = <0>;
 397                         interrupt-parent = <&plic>;
 398                         interrupts = <58>;
 399                         clocks = <&clkcfg CLK_I2C0>;
 400                         clock-frequency = <100000>;
 401                         status = "disabled";
 402                 };
 403
 404                 i2c1: i2c@2010b000 {
 405                         compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7";
 406                         reg = <0x0 0x2010b000 0x0 0x1000>;
 407                         #address-cells = <1>;
 408                         #size-cells = <0>;
 409                         interrupt-parent = <&plic>;
 410                         interrupts = <61>;
 411                         clocks = <&clkcfg CLK_I2C1>;
 412                         clock-frequency = <100000>;
 413                         status = "disabled";
 414                 };
 415
 416                 can0: can@2010c000 {
 417                         compatible = "microchip,mpfs-can";
 418                         reg = <0x0 0x2010c000 0x0 0x1000>;
 419                         clocks = <&clkcfg CLK_CAN0>;
 420                         interrupt-parent = <&plic>;
 421                         interrupts = <56>;
 422                         status = "disabled";
 423                 };
 424
 425                 can1: can@2010d000 {
 426                         compatible = "microchip,mpfs-can";
 427                         reg = <0x0 0x2010d000 0x0 0x1000>;
 428                         clocks = <&clkcfg CLK_CAN1>;
 429                         interrupt-parent = <&plic>;
 430                         interrupts = <57>;
 431                         status = "disabled";
 432                 };
 433
 434                 mac0: ethernet@20110000 {
 435                         compatible = "microchip,mpfs-macb", "cdns,macb";
 436                         reg = <0x0 0x20110000 0x0 0x2000>;
 437                         #address-cells = <1>;
 438                         #size-cells = <0>;
 439                         interrupt-parent = <&plic>;
 440                         interrupts = <64>, <65>, <66>, <67>, <68>, <69>;
 441                         local-mac-address = [00 00 00 00 00 00];
 442                         clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>;
 443                         clock-names = "pclk", "hclk";
 444                         resets = <&clkcfg CLK_MAC0>;
 445                         status = "disabled";
 446                 };
 447
 448                 mac1: ethernet@20112000 {
 449                         compatible = "microchip,mpfs-macb", "cdns,macb";
 450                         reg = <0x0 0x20112000 0x0 0x2000>;
 451                         #address-cells = <1>;
 452                         #size-cells = <0>;
 453                         interrupt-parent = <&plic>;
 454                         interrupts = <70>, <71>, <72>, <73>, <74>, <75>;
 455                         local-mac-address = [00 00 00 00 00 00];
 456                         clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>;
 457                         clock-names = "pclk", "hclk";
 458                         resets = <&clkcfg CLK_MAC1>;
 459                         status = "disabled";
 460                 };
 461
 462                 gpio0: gpio@20120000 {
 463                         compatible = "microchip,mpfs-gpio";
 464                         reg = <0x0 0x20120000 0x0 0x1000>;
 465                         interrupt-parent = <&plic>;
 466                         interrupt-controller;
 467                         #interrupt-cells = <1>;
 468                         clocks = <&clkcfg CLK_GPIO0>;
 469                         gpio-controller;
 470                         #gpio-cells = <2>;
 471                         status = "disabled";
 472                 };
 473
 474                 gpio1: gpio@20121000 {
 475                         compatible = "microchip,mpfs-gpio";
 476                         reg = <0x0 0x20121000 0x0 0x1000>;
 477                         interrupt-parent = <&plic>;
 478                         interrupt-controller;
 479                         #interrupt-cells = <1>;
 480                         clocks = <&clkcfg CLK_GPIO1>;
 481                         gpio-controller;
 482                         #gpio-cells = <2>;
 483                         status = "disabled";
 484                 };
 485
 486                 gpio2: gpio@20122000 {
 487                         compatible = "microchip,mpfs-gpio";
 488                         reg = <0x0 0x20122000 0x0 0x1000>;
 489                         interrupt-parent = <&plic>;
 490                         interrupt-controller;
 491                         #interrupt-cells = <1>;
 492                         clocks = <&clkcfg CLK_GPIO2>;
 493                         gpio-controller;
 494                         #gpio-cells = <2>;
 495                         status = "disabled";
 496                 };
 497
 498                 rtc: rtc@20124000 {
 499                         compatible = "microchip,mpfs-rtc";
 500                         reg = <0x0 0x20124000 0x0 0x1000>;
 501                         interrupt-parent = <&plic>;
 502                         interrupts = <80>, <81>;
 503                         clocks = <&clkcfg CLK_RTC>, <&clkcfg CLK_RTCREF>;
 504                         clock-names = "rtc", "rtcref";
 505                         status = "disabled";
 506                 };
 507
 508                 usb: usb@20201000 {
 509                         compatible = "microchip,mpfs-musb";
 510                         reg = <0x0 0x20201000 0x0 0x1000>;
 511                         interrupt-parent = <&plic>;
 512                         interrupts = <86>, <87>;
 513                         clocks = <&clkcfg CLK_USB>;
 514                         interrupt-names = "dma","mc";
 515                         status = "disabled";
 516                 };
 517
 518                 mbox: mailbox@37020000 {
 519                         compatible = "microchip,mpfs-mailbox";
 520                         reg = <0x0 0x37020000 0x0 0x58>, <0x0 0x2000318C 0x0 0x40>,
 521                               <0x0 0x37020800 0x0 0x100>;
 522                         interrupt-parent = <&plic>;
 523                         interrupts = <96>;
 524                         #mbox-cells = <1>;
 525                         status = "disabled";
 526                 };
 527         };
 528 };