1 // SPDX-License-Identifier: BSD-3-Clause
3 * IPQ5332 device tree source
5 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
8 #include <dt-bindings/clock/qcom,apss-ipq.h>
9 #include <dt-bindings/clock/qcom,ipq5332-gcc.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 interrupt-parent = <&intc>;
18 sleep_clk: sleep-clk {
19 compatible = "fixed-clock";
23 xo_board: xo-board-clk {
24 compatible = "fixed-clock";
35 compatible = "arm,cortex-a53";
37 enable-method = "psci";
38 next-level-cache = <&L2_0>;
39 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
40 operating-points-v2 = <&cpu_opp_table>;
45 compatible = "arm,cortex-a53";
47 enable-method = "psci";
48 next-level-cache = <&L2_0>;
49 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
50 operating-points-v2 = <&cpu_opp_table>;
55 compatible = "arm,cortex-a53";
57 enable-method = "psci";
58 next-level-cache = <&L2_0>;
59 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
60 operating-points-v2 = <&cpu_opp_table>;
65 compatible = "arm,cortex-a53";
67 enable-method = "psci";
68 next-level-cache = <&L2_0>;
69 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
70 operating-points-v2 = <&cpu_opp_table>;
82 compatible = "qcom,scm-ipq5332", "qcom,scm";
83 qcom,dload-mode = <&tcsr 0x6100>;
88 device_type = "memory";
89 /* We expect the bootloader to fill in the size */
90 reg = <0x0 0x40000000 0x0 0x0>;
93 cpu_opp_table: opp-table-cpu {
94 compatible = "operating-points-v2";
98 opp-hz = /bits/ 64 <1488000000>;
99 clock-latency-ns = <200000>;
104 compatible = "arm,cortex-a53-pmu";
105 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
109 compatible = "arm,psci-1.0";
114 #address-cells = <2>;
118 bootloader@4a100000 {
119 reg = <0x0 0x4a100000 0x0 0x400000>;
124 reg = <0x0 0x4a500000 0x0 0x100000>;
128 tz_mem: tz@4a600000 {
129 reg = <0x0 0x4a600000 0x0 0x200000>;
134 compatible = "qcom,smem";
135 reg = <0x0 0x4a800000 0x0 0x100000>;
138 hwlocks = <&tcsr_mutex 3>;
143 compatible = "simple-bus";
144 #address-cells = <1>;
146 ranges = <0 0 0 0xffffffff>;
149 compatible = "qcom,ipq5332-usb-hsphy";
150 reg = <0x0007b000 0x12c>;
152 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>;
154 resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
161 qfprom: efuse@a4000 {
162 compatible = "qcom,ipq5332-qfprom", "qcom,qfprom";
163 reg = <0x000a4000 0x721>;
164 #address-cells = <1>;
169 compatible = "qcom,prng-ee";
170 reg = <0x000e3000 0x1000>;
171 clocks = <&gcc GCC_PRNG_AHB_CLK>;
172 clock-names = "core";
175 tlmm: pinctrl@1000000 {
176 compatible = "qcom,ipq5332-tlmm";
177 reg = <0x01000000 0x300000>;
178 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
181 gpio-ranges = <&tlmm 0 0 53>;
182 interrupt-controller;
183 #interrupt-cells = <2>;
185 serial_0_pins: serial0-state {
186 pins = "gpio18", "gpio19";
187 function = "blsp0_uart0";
188 drive-strength = <8>;
193 gcc: clock-controller@1800000 {
194 compatible = "qcom,ipq5332-gcc";
195 reg = <0x01800000 0x80000>;
198 #power-domain-cells = <1>;
199 clocks = <&xo_board>,
206 tcsr_mutex: hwlock@1905000 {
207 compatible = "qcom,tcsr-mutex";
208 reg = <0x01905000 0x20000>;
212 tcsr: syscon@1937000 {
213 compatible = "qcom,tcsr-ipq5332", "syscon";
214 reg = <0x01937000 0x21000>;
218 compatible = "qcom,ipq5332-sdhci", "qcom,sdhci-msm-v5";
219 reg = <0x07804000 0x1000>, <0x07805000 0x1000>;
221 interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
222 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>;
223 interrupt-names = "hc_irq", "pwr_irq";
225 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
226 <&gcc GCC_SDCC1_APPS_CLK>,
228 clock-names = "iface", "core", "xo";
232 blsp_dma: dma-controller@7884000 {
233 compatible = "qcom,bam-v1.7.0";
234 reg = <0x07884000 0x1d000>;
235 interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>;
236 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
237 clock-names = "bam_clk";
242 blsp1_uart0: serial@78af000 {
243 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
244 reg = <0x078af000 0x200>;
245 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
246 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
247 <&gcc GCC_BLSP1_AHB_CLK>;
248 clock-names = "core", "iface";
252 blsp1_uart1: serial@78b0000 {
253 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
254 reg = <0x078b0000 0x200>;
255 interrupts = <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>;
256 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
257 <&gcc GCC_BLSP1_AHB_CLK>;
258 clock-names = "core", "iface";
259 dmas = <&blsp_dma 2>, <&blsp_dma 3>;
260 dma-names = "tx", "rx";
264 blsp1_spi0: spi@78b5000 {
265 compatible = "qcom,spi-qup-v2.2.1";
266 reg = <0x078b5000 0x600>;
267 #address-cells = <1>;
269 interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
270 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
271 <&gcc GCC_BLSP1_AHB_CLK>;
272 clock-names = "core", "iface";
273 dmas = <&blsp_dma 4>, <&blsp_dma 5>;
274 dma-names = "tx", "rx";
278 blsp1_i2c1: i2c@78b6000 {
279 compatible = "qcom,i2c-qup-v2.2.1";
280 reg = <0x078b6000 0x600>;
281 #address-cells = <1>;
283 interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>;
284 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
285 <&gcc GCC_BLSP1_AHB_CLK>;
286 clock-names = "core", "iface";
287 dmas = <&blsp_dma 6>, <&blsp_dma 7>;
288 dma-names = "tx", "rx";
292 blsp1_spi2: spi@78b7000 {
293 compatible = "qcom,spi-qup-v2.2.1";
294 reg = <0x078b7000 0x600>;
295 #address-cells = <1>;
297 interrupts = <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>;
298 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
299 <&gcc GCC_BLSP1_AHB_CLK>;
300 clock-names = "core", "iface";
301 dmas = <&blsp_dma 8>, <&blsp_dma 9>;
302 dma-names = "tx", "rx";
307 compatible = "qcom,ipq5332-dwc3", "qcom,dwc3";
308 reg = <0x08af8800 0x400>;
310 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
311 interrupt-names = "hs_phy_irq";
313 clocks = <&gcc GCC_USB0_MASTER_CLK>,
314 <&gcc GCC_SNOC_USB_CLK>,
315 <&gcc GCC_USB0_SLEEP_CLK>,
316 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
317 clock-names = "core",
322 resets = <&gcc GCC_USB_BCR>;
324 qcom,select-utmi-as-pipe-clk;
326 #address-cells = <1>;
332 usb_dwc: usb@8a00000 {
333 compatible = "snps,dwc3";
334 reg = <0x08a00000 0xe000>;
335 clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
337 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
338 phy-names = "usb2-phy";
341 snps,is-utmi-l1-suspend;
342 snps,hird-threshold = /bits/ 8 <0x0>;
343 snps,dis_u2_susphy_quirk;
344 snps,dis_u3_susphy_quirk;
348 intc: interrupt-controller@b000000 {
349 compatible = "qcom,msm-qgic2";
350 reg = <0x0b000000 0x1000>, /* GICD */
351 <0x0b002000 0x1000>, /* GICC */
352 <0x0b001000 0x1000>, /* GICH */
353 <0x0b004000 0x1000>; /* GICV */
354 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
355 interrupt-controller;
356 #interrupt-cells = <3>;
357 #address-cells = <1>;
359 ranges = <0 0x0b00c000 0x3000>;
362 compatible = "arm,gic-v2m-frame";
363 reg = <0x00000000 0xffd>;
368 compatible = "arm,gic-v2m-frame";
369 reg = <0x00001000 0xffd>;
374 compatible = "arm,gic-v2m-frame";
375 reg = <0x00002000 0xffd>;
380 watchdog: watchdog@b017000 {
381 compatible = "qcom,apss-wdt-ipq5332", "qcom,kpss-wdt";
382 reg = <0x0b017000 0x1000>;
383 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
384 clocks = <&sleep_clk>;
388 apcs_glb: mailbox@b111000 {
389 compatible = "qcom,ipq5332-apcs-apps-global",
390 "qcom,ipq6018-apcs-apps-global";
391 reg = <0x0b111000 0x1000>;
393 clocks = <&a53pll>, <&xo_board>;
394 clock-names = "pll", "xo";
398 a53pll: clock@b116000 {
399 compatible = "qcom,ipq5332-a53pll";
400 reg = <0x0b116000 0x40>;
402 clocks = <&xo_board>;
407 compatible = "arm,armv7-timer-mem";
408 reg = <0x0b120000 0x1000>;
409 #address-cells = <1>;
414 reg = <0x0b121000 0x1000>,
416 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
417 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
422 reg = <0x0b123000 0x1000>;
423 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
429 reg = <0x0b124000 0x1000>;
430 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
436 reg = <0x0b125000 0x1000>;
437 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
443 reg = <0x0b126000 0x1000>;
444 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
450 reg = <0x0b127000 0x1000>;
451 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
457 reg = <0x0b128000 0x1000>;
458 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
466 compatible = "arm,armv8-timer";
467 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
468 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
469 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
470 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;