dts/upstream/src/arm/rockchip/rv1126.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
   4  */
   5
   6 #include <dt-bindings/clock/rockchip,rv1126-cru.h>
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/interrupt-controller/irq.h>
  10 #include <dt-bindings/pinctrl/rockchip.h>
  11 #include <dt-bindings/power/rockchip,rv1126-power.h>
  12 #include <dt-bindings/soc/rockchip,boot-mode.h>
  13
  14 / {
  15         #address-cells = <1>;
  16         #size-cells = <1>;
  17
  18         compatible = "rockchip,rv1126";
  19
  20         interrupt-parent = <&gic>;
  21
  22         aliases {
  23                 i2c0 = &i2c0;
  24         };
  25
  26         cpus {
  27                 #address-cells = <1>;
  28                 #size-cells = <0>;
  29
  30                 cpu0: cpu@f00 {
  31                         device_type = "cpu";
  32                         compatible = "arm,cortex-a7";
  33                         reg = <0xf00>;
  34                         enable-method = "psci";
  35                         clocks = <&cru ARMCLK>;
  36                 };
  37
  38                 cpu1: cpu@f01 {
  39                         device_type = "cpu";
  40                         compatible = "arm,cortex-a7";
  41                         reg = <0xf01>;
  42                         enable-method = "psci";
  43                         clocks = <&cru ARMCLK>;
  44                 };
  45
  46                 cpu2: cpu@f02 {
  47                         device_type = "cpu";
  48                         compatible = "arm,cortex-a7";
  49                         reg = <0xf02>;
  50                         enable-method = "psci";
  51                         clocks = <&cru ARMCLK>;
  52                 };
  53
  54                 cpu3: cpu@f03 {
  55                         device_type = "cpu";
  56                         compatible = "arm,cortex-a7";
  57                         reg = <0xf03>;
  58                         enable-method = "psci";
  59                         clocks = <&cru ARMCLK>;
  60                 };
  61         };
  62
  63         arm-pmu {
  64                 compatible = "arm,cortex-a7-pmu";
  65                 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
  66                              <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
  67                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
  68                              <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
  69                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  70         };
  71
  72         psci {
  73                 compatible = "arm,psci-1.0";
  74                 method = "smc";
  75         };
  76
  77         timer {
  78                 compatible = "arm,armv7-timer";
  79                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  80                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  81                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  82                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  83                 clock-frequency = <24000000>;
  84         };
  85
  86         display_subsystem {
  87                 compatible = "rockchip,display-subsystem";
  88                 ports = <&vop_out>;
  89         };
  90
  91         xin24m: oscillator {
  92                 compatible = "fixed-clock";
  93                 clock-frequency = <24000000>;
  94                 clock-output-names = "xin24m";
  95                 #clock-cells = <0>;
  96         };
  97
  98         grf: syscon@fe000000 {
  99                 compatible = "rockchip,rv1126-grf", "syscon", "simple-mfd";
 100                 reg = <0xfe000000 0x20000>;
 101         };
 102
 103         pmugrf: syscon@fe020000 {
 104                 compatible = "rockchip,rv1126-pmugrf", "syscon", "simple-mfd";
 105                 reg = <0xfe020000 0x1000>;
 106
 107                 pmu_io_domains: io-domains {
 108                         compatible = "rockchip,rv1126-pmu-io-voltage-domain";
 109                         status = "disabled";
 110                 };
 111         };
 112
 113         qos_emmc: qos@fe860000 {
 114                 compatible = "rockchip,rv1126-qos", "syscon";
 115                 reg = <0xfe860000 0x20>;
 116         };
 117
 118         qos_nandc: qos@fe860080 {
 119                 compatible = "rockchip,rv1126-qos", "syscon";
 120                 reg = <0xfe860080 0x20>;
 121         };
 122
 123         qos_sfc: qos@fe860200 {
 124                 compatible = "rockchip,rv1126-qos", "syscon";
 125                 reg = <0xfe860200 0x20>;
 126         };
 127
 128         qos_sdio: qos@fe86c000 {
 129                 compatible = "rockchip,rv1126-qos", "syscon";
 130                 reg = <0xfe86c000 0x20>;
 131         };
 132
 133         qos_iep: qos@fe8a0000 {
 134                 compatible = "rockchip,rv1126-qos", "syscon";
 135                 reg = <0xfe8a0000 0x20>;
 136         };
 137
 138         qos_rga_rd: qos@fe8a0080 {
 139                 compatible = "rockchip,rv1126-qos", "syscon";
 140                 reg = <0xfe8a0080 0x20>;
 141         };
 142
 143         qos_rga_wr: qos@fe8a0100 {
 144                 compatible = "rockchip,rv1126-qos", "syscon";
 145                 reg = <0xfe8a0100 0x20>;
 146         };
 147
 148         qos_vop: qos@fe8a0180 {
 149                 compatible = "rockchip,rv1126-qos", "syscon";
 150                 reg = <0xfe8a0180 0x20>;
 151         };
 152
 153         gic: interrupt-controller@feff0000 {
 154                 compatible = "arm,gic-400";
 155                 interrupt-controller;
 156                 #interrupt-cells = <3>;
 157                 #address-cells = <0>;
 158
 159                 reg = <0xfeff1000 0x1000>,
 160                       <0xfeff2000 0x2000>,
 161                       <0xfeff4000 0x2000>,
 162                       <0xfeff6000 0x2000>;
 163                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 164         };
 165
 166         pmu: power-management@ff3e0000 {
 167                 compatible = "rockchip,rv1126-pmu", "syscon", "simple-mfd";
 168                 reg = <0xff3e0000 0x1000>;
 169
 170                 power: power-controller {
 171                         compatible = "rockchip,rv1126-power-controller";
 172                         #power-domain-cells = <1>;
 173                         #address-cells = <1>;
 174                         #size-cells = <0>;
 175
 176                         power-domain@RV1126_PD_NVM {
 177                                 reg = <RV1126_PD_NVM>;
 178                                 clocks = <&cru HCLK_EMMC>,
 179                                          <&cru CLK_EMMC>,
 180                                          <&cru HCLK_NANDC>,
 181                                          <&cru CLK_NANDC>,
 182                                          <&cru HCLK_SFC>,
 183                                          <&cru HCLK_SFCXIP>,
 184                                          <&cru SCLK_SFC>;
 185                                 pm_qos = <&qos_emmc>,
 186                                          <&qos_nandc>,
 187                                          <&qos_sfc>;
 188                                 #power-domain-cells = <0>;
 189                         };
 190
 191                         power-domain@RV1126_PD_SDIO {
 192                                 reg = <RV1126_PD_SDIO>;
 193                                 clocks = <&cru HCLK_SDIO>,
 194                                          <&cru CLK_SDIO>;
 195                                 pm_qos = <&qos_sdio>;
 196                                 #power-domain-cells = <0>;
 197                         };
 198
 199                         power-domain@RV1126_PD_VO {
 200                                 reg = <RV1126_PD_VO>;
 201                                 clocks = <&cru ACLK_RGA>,
 202                                          <&cru HCLK_RGA>,
 203                                          <&cru CLK_RGA_CORE>,
 204                                          <&cru ACLK_VOP>,
 205                                          <&cru HCLK_VOP>,
 206                                          <&cru DCLK_VOP>,
 207                                          <&cru PCLK_DSIHOST>,
 208                                          <&cru ACLK_IEP>,
 209                                          <&cru HCLK_IEP>,
 210                                          <&cru CLK_IEP_CORE>;
 211                                 pm_qos = <&qos_rga_rd>,
 212                                          <&qos_rga_wr>,
 213                                          <&qos_vop>,
 214                                          <&qos_iep>;
 215                                 #power-domain-cells = <0>;
 216                         };
 217                 };
 218         };
 219
 220         i2c0: i2c@ff3f0000 {
 221                 compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
 222                 reg = <0xff3f0000 0x1000>;
 223                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 224                 rockchip,grf = <&pmugrf>;
 225                 clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>;
 226                 clock-names = "i2c", "pclk";
 227                 pinctrl-names = "default";
 228                 pinctrl-0 = <&i2c0_xfer>;
 229                 #address-cells = <1>;
 230                 #size-cells = <0>;
 231                 status = "disabled";
 232         };
 233
 234         uart1: serial@ff410000 {
 235                 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
 236                 reg = <0xff410000 0x100>;
 237                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 238                 clock-frequency = <24000000>;
 239                 clocks = <&pmucru SCLK_UART1>, <&pmucru PCLK_UART1>;
 240                 clock-names = "baudclk", "apb_pclk";
 241                 dmas = <&dmac 7>, <&dmac 6>;
 242                 dma-names = "tx", "rx";
 243                 pinctrl-names = "default";
 244                 pinctrl-0 = <&uart1m0_xfer>;
 245                 reg-shift = <2>;
 246                 reg-io-width = <4>;
 247                 status = "disabled";
 248         };
 249
 250         pwm2: pwm@ff430020 {
 251                 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
 252                 reg = <0xff430020 0x10>;
 253                 clock-names = "pwm", "pclk";
 254                 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
 255                 pinctrl-names = "default";
 256                 pinctrl-0 = <&pwm2m0_pins>;
 257                 #pwm-cells = <3>;
 258                 status = "disabled";
 259         };
 260
 261         pmucru: clock-controller@ff480000 {
 262                 compatible = "rockchip,rv1126-pmucru";
 263                 reg = <0xff480000 0x1000>;
 264                 rockchip,grf = <&grf>;
 265                 #clock-cells = <1>;
 266                 #reset-cells = <1>;
 267         };
 268
 269         cru: clock-controller@ff490000 {
 270                 compatible = "rockchip,rv1126-cru";
 271                 reg = <0xff490000 0x1000>;
 272                 clocks = <&xin24m>;
 273                 clock-names = "xin24m";
 274                 rockchip,grf = <&grf>;
 275                 #clock-cells = <1>;
 276                 #reset-cells = <1>;
 277         };
 278
 279         dmac: dma-controller@ff4e0000 {
 280                 compatible = "arm,pl330", "arm,primecell";
 281                 reg = <0xff4e0000 0x4000>;
 282                 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 283                              <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 284                 #dma-cells = <1>;
 285                 arm,pl330-periph-burst;
 286                 clocks = <&cru ACLK_DMAC>;
 287                 clock-names = "apb_pclk";
 288         };
 289
 290         pwm11: pwm@ff550030 {
 291                 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
 292                 reg = <0xff550030 0x10>;
 293                 clock-names = "pwm", "pclk";
 294                 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
 295                 pinctrl-0 = <&pwm11m0_pins>;
 296                 pinctrl-names = "default";
 297                 #pwm-cells = <3>;
 298                 status = "disabled";
 299         };
 300
 301         uart0: serial@ff560000 {
 302                 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
 303                 reg = <0xff560000 0x100>;
 304                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 305                 clock-frequency = <24000000>;
 306                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 307                 clock-names = "baudclk", "apb_pclk";
 308                 dmas = <&dmac 5>, <&dmac 4>;
 309                 dma-names = "tx", "rx";
 310                 pinctrl-names = "default";
 311                 pinctrl-0 = <&uart0_xfer>;
 312                 reg-shift = <2>;
 313                 reg-io-width = <4>;
 314                 status = "disabled";
 315         };
 316
 317         uart2: serial@ff570000 {
 318                 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
 319                 reg = <0xff570000 0x100>;
 320                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 321                 clock-frequency = <24000000>;
 322                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 323                 clock-names = "baudclk", "apb_pclk";
 324                 dmas = <&dmac 9>, <&dmac 8>;
 325                 dma-names = "tx", "rx";
 326                 pinctrl-names = "default";
 327                 pinctrl-0 = <&uart2m1_xfer>;
 328                 reg-shift = <2>;
 329                 reg-io-width = <4>;
 330                 status = "disabled";
 331         };
 332
 333         uart3: serial@ff580000 {
 334                 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
 335                 reg = <0xff580000 0x100>;
 336                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 337                 clock-frequency = <24000000>;
 338                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 339                 clock-names = "baudclk", "apb_pclk";
 340                 dmas = <&dmac 11>, <&dmac 10>;
 341                 dma-names = "tx", "rx";
 342                 pinctrl-names = "default";
 343                 pinctrl-0 = <&uart3m0_xfer>;
 344                 reg-shift = <2>;
 345                 reg-io-width = <4>;
 346                 status = "disabled";
 347         };
 348
 349         uart4: serial@ff590000 {
 350                 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
 351                 reg = <0xff590000 0x100>;
 352                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 353                 clock-frequency = <24000000>;
 354                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 355                 clock-names = "baudclk", "apb_pclk";
 356                 dmas = <&dmac 13>, <&dmac 12>;
 357                 dma-names = "tx", "rx";
 358                 pinctrl-names = "default";
 359                 pinctrl-0 = <&uart4m0_xfer>;
 360                 reg-shift = <2>;
 361                 reg-io-width = <4>;
 362                 status = "disabled";
 363         };
 364
 365         uart5: serial@ff5a0000 {
 366                 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
 367                 reg = <0xff5a0000 0x100>;
 368                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 369                 clock-frequency = <24000000>;
 370                 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
 371                 clock-names = "baudclk", "apb_pclk";
 372                 dmas = <&dmac 15>, <&dmac 14>;
 373                 dma-names = "tx", "rx";
 374                 pinctrl-names = "default";
 375                 pinctrl-0 = <&uart5m0_xfer>;
 376                 reg-shift = <2>;
 377                 reg-io-width = <4>;
 378                 status = "disabled";
 379         };
 380
 381         saradc: adc@ff5e0000 {
 382                 compatible = "rockchip,rv1126-saradc", "rockchip,rk3399-saradc";
 383                 reg = <0xff5e0000 0x100>;
 384                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 385                 #io-channel-cells = <1>;
 386                 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
 387                 clock-names = "saradc", "apb_pclk";
 388                 resets = <&cru SRST_SARADC_P>;
 389                 reset-names = "saradc-apb";
 390                 status = "disabled";
 391         };
 392
 393         timer0: timer@ff660000 {
 394                 compatible = "rockchip,rv1126-timer", "rockchip,rk3288-timer";
 395                 reg = <0xff660000 0x20>;
 396                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 397                 clocks = <&cru PCLK_TIMER>, <&cru CLK_TIMER0>;
 398                 clock-names = "pclk", "timer";
 399         };
 400
 401         vop: vop@ffb00000 {
 402                 compatible = "rockchip,rv1126-vop";
 403                 reg = <0xffb00000 0x200>, <0xffb00a00 0x400>;
 404                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 405                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 406                 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
 407                 reset-names = "axi", "ahb", "dclk";
 408                 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
 409                 iommus = <&vop_mmu>;
 410                 power-domains = <&power RV1126_PD_VO>;
 411                 status = "disabled";
 412
 413                 vop_out: port {
 414                         #address-cells = <1>;
 415                         #size-cells = <0>;
 416
 417                         vop_out_rgb: endpoint@0 {
 418                                 reg = <0>;
 419                         };
 420
 421                         vop_out_dsi: endpoint@1 {
 422                                 reg = <1>;
 423                         };
 424                 };
 425         };
 426
 427         vop_mmu: iommu@ffb00f00 {
 428                 compatible = "rockchip,iommu";
 429                 reg = <0xffb00f00 0x100>;
 430                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 431                 clock-names = "aclk", "iface";
 432                 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
 433                 #iommu-cells = <0>;
 434                 power-domains = <&power RV1126_PD_VO>;
 435                 status = "disabled";
 436         };
 437
 438         gmac: ethernet@ffc40000 {
 439                 compatible = "rockchip,rv1126-gmac", "snps,dwmac-4.20a";
 440                 reg = <0xffc40000 0x4000>;
 441                 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
 442                              <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 443                 interrupt-names = "macirq", "eth_wake_irq";
 444                 rockchip,grf = <&grf>;
 445                 clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>,
 446                          <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_REF>,
 447                          <&cru ACLK_GMAC>, <&cru PCLK_GMAC>,
 448                          <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_PTPREF>;
 449                 clock-names = "stmmaceth", "mac_clk_rx",
 450                               "mac_clk_tx", "clk_mac_ref",
 451                               "aclk_mac", "pclk_mac",
 452                               "clk_mac_speed", "ptp_ref";
 453                 resets = <&cru SRST_GMAC_A>;
 454                 reset-names = "stmmaceth";
 455
 456                 snps,mixed-burst;
 457                 snps,tso;
 458
 459                 snps,axi-config = <&stmmac_axi_setup>;
 460                 snps,mtl-rx-config = <&mtl_rx_setup>;
 461                 snps,mtl-tx-config = <&mtl_tx_setup>;
 462                 status = "disabled";
 463
 464                 mdio: mdio {
 465                         compatible = "snps,dwmac-mdio";
 466                         #address-cells = <0x1>;
 467                         #size-cells = <0x0>;
 468                 };
 469
 470                 stmmac_axi_setup: stmmac-axi-config {
 471                         snps,wr_osr_lmt = <4>;
 472                         snps,rd_osr_lmt = <8>;
 473                         snps,blen = <0 0 0 0 16 8 4>;
 474                 };
 475
 476                 mtl_rx_setup: rx-queues-config {
 477                         snps,rx-queues-to-use = <1>;
 478                         queue0 {};
 479                 };
 480
 481                 mtl_tx_setup: tx-queues-config {
 482                         snps,tx-queues-to-use = <1>;
 483                         queue0 {};
 484                 };
 485         };
 486
 487         emmc: mmc@ffc50000 {
 488                 compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
 489                 reg = <0xffc50000 0x4000>;
 490                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 491                 clocks = <&cru HCLK_EMMC>, <&cru CLK_EMMC>,
 492                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 493                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 494                 fifo-depth = <0x100>;
 495                 max-frequency = <200000000>;
 496                 power-domains = <&power RV1126_PD_NVM>;
 497                 status = "disabled";
 498         };
 499
 500         sdmmc: mmc@ffc60000 {
 501                 compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
 502                 reg = <0xffc60000 0x4000>;
 503                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 504                 clocks = <&cru HCLK_SDMMC>, <&cru CLK_SDMMC>,
 505                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 506                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 507                 fifo-depth = <0x100>;
 508                 max-frequency = <200000000>;
 509                 status = "disabled";
 510         };
 511
 512         sdio: mmc@ffc70000 {
 513                 compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
 514                 reg = <0xffc70000 0x4000>;
 515                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 516                 clocks = <&cru HCLK_SDIO>, <&cru CLK_SDIO>,
 517                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 518                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 519                 fifo-depth = <0x100>;
 520                 max-frequency = <200000000>;
 521                 power-domains = <&power RV1126_PD_SDIO>;
 522                 status = "disabled";
 523         };
 524
 525         sfc: spi@ffc90000  {
 526                 compatible = "rockchip,sfc";
 527                 reg = <0xffc90000 0x4000>;
 528                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 529                 assigned-clocks = <&cru SCLK_SFC>;
 530                 assigned-clock-rates = <80000000>;
 531                 clock-names = "clk_sfc", "hclk_sfc";
 532                 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
 533                 power-domains = <&power RV1126_PD_NVM>;
 534                 status = "disabled";
 535         };
 536
 537         pinctrl: pinctrl {
 538                 compatible = "rockchip,rv1126-pinctrl";
 539                 rockchip,grf = <&grf>;
 540                 rockchip,pmu = <&pmugrf>;
 541                 #address-cells = <1>;
 542                 #size-cells = <1>;
 543                 ranges;
 544
 545                 gpio0: gpio@ff460000 {
 546                         compatible = "rockchip,gpio-bank";
 547                         reg = <0xff460000 0x100>;
 548                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 549                         clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>;
 550                         gpio-controller;
 551                         #gpio-cells = <2>;
 552                         interrupt-controller;
 553                         #interrupt-cells = <2>;
 554                 };
 555
 556                 gpio1: gpio@ff620000 {
 557                         compatible = "rockchip,gpio-bank";
 558                         reg = <0xff620000 0x100>;
 559                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 560                         clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
 561                         gpio-controller;
 562                         #gpio-cells = <2>;
 563                         interrupt-controller;
 564                         #interrupt-cells = <2>;
 565                 };
 566
 567                 gpio2: gpio@ff630000 {
 568                         compatible = "rockchip,gpio-bank";
 569                         reg = <0xff630000 0x100>;
 570                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 571                         clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
 572                         gpio-controller;
 573                         #gpio-cells = <2>;
 574                         interrupt-controller;
 575                         #interrupt-cells = <2>;
 576                 };
 577
 578                 gpio3: gpio@ff640000 {
 579                         compatible = "rockchip,gpio-bank";
 580                         reg = <0xff640000 0x100>;
 581                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 582                         clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
 583                         gpio-controller;
 584                         #gpio-cells = <2>;
 585                         interrupt-controller;
 586                         #interrupt-cells = <2>;
 587                 };
 588
 589                 gpio4: gpio@ff650000 {
 590                         compatible = "rockchip,gpio-bank";
 591                         reg = <0xff650000 0x100>;
 592                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 593                         clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
 594                         gpio-controller;
 595                         #gpio-cells = <2>;
 596                         interrupt-controller;
 597                         #interrupt-cells = <2>;
 598                 };
 599         };
 600 };
 601
 602 #include "rv1126-pinctrl.dtsi"