arch/arm/mach-imx/imx8m/clock_imx8mm.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2018-2019 NXP
   4  *
   5  * Peng Fan <[email protected]>
   6  */
   7
   8 #include <common.h>
   9 #include <asm/arch/clock.h>
  10 #include <asm/arch/imx-regs.h>
  11 #include <asm/arch/sys_proto.h>
  12 #include <asm/global_data.h>
  13 #include <asm/io.h>
  14 #include <div64.h>
  15 #include <errno.h>
  16 #include <linux/bitops.h>
  17 #include <linux/delay.h>
  18
  19 DECLARE_GLOBAL_DATA_PTR;
  20
  21 static struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
  22
  23 static u32 get_root_clk(enum clk_root_index clock_id);
  24
  25 #ifdef CONFIG_IMX_HAB
  26 void hab_caam_clock_enable(unsigned char enable)
  27 {
  28         /* The CAAM clock is always on for iMX8M */
  29 }
  30 #endif
  31
  32 void enable_ocotp_clk(unsigned char enable)
  33 {
  34         clock_enable(CCGR_OCOTP, !!enable);
  35 }
  36
  37 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
  38 {
  39         /* 0 - 3 is valid i2c num */
  40         if (i2c_num > 3)
  41                 return -EINVAL;
  42
  43         clock_enable(CCGR_I2C1 + i2c_num, !!enable);
  44
  45         return 0;
  46 }
  47
  48 #ifdef CONFIG_SPL_BUILD
  49 static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = {
  50         PLL_1443X_RATE(1000000000U, 250, 3, 1, 0),
  51         PLL_1443X_RATE(800000000U, 300, 9, 0, 0),
  52         PLL_1443X_RATE(750000000U, 250, 8, 0, 0),
  53         PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
  54         PLL_1443X_RATE(600000000U, 300, 3, 2, 0),
  55         PLL_1443X_RATE(594000000U, 99, 1, 2, 0),
  56         PLL_1443X_RATE(400000000U, 300, 9, 1, 0),
  57         PLL_1443X_RATE(266666667U, 400, 9, 2, 0),
  58         PLL_1443X_RATE(167000000U, 334, 3, 4, 0),
  59         PLL_1443X_RATE(100000000U, 300, 9, 3, 0),
  60 };
  61
  62 static int fracpll_configure(enum pll_clocks pll, u32 freq)
  63 {
  64         int i;
  65         u32 tmp, div_val;
  66         void *pll_base;
  67         struct imx_int_pll_rate_table *rate;
  68
  69         for (i = 0; i < ARRAY_SIZE(imx8mm_fracpll_tbl); i++) {
  70                 if (freq == imx8mm_fracpll_tbl[i].rate)
  71                         break;
  72         }
  73
  74         if (i == ARRAY_SIZE(imx8mm_fracpll_tbl)) {
  75                 printf("%s: No matched freq table %u\n", __func__, freq);
  76                 return -EINVAL;
  77         }
  78
  79         rate = &imx8mm_fracpll_tbl[i];
  80
  81         switch (pll) {
  82         case ANATOP_DRAM_PLL:
  83                 setbits_le32(GPC_BASE_ADDR + 0xEC, 1 << 7);
  84                 setbits_le32(GPC_BASE_ADDR + 0xF8, 1 << 5);
  85                 writel(SRC_DDR1_ENABLE_MASK, SRC_BASE_ADDR + 0x1004);
  86
  87                 pll_base = &ana_pll->dram_pll_gnrl_ctl;
  88                 break;
  89         case ANATOP_VIDEO_PLL:
  90                 pll_base = &ana_pll->video_pll1_gnrl_ctl;
  91                 break;
  92         default:
  93                 return 0;
  94         }
  95         /* Bypass clock and set lock to pll output lock */
  96         tmp = readl(pll_base);
  97         tmp |= BYPASS_MASK;
  98         writel(tmp, pll_base);
  99
 100         /* Enable RST */
 101         tmp &= ~RST_MASK;
 102         writel(tmp, pll_base);
 103
 104         div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) |
 105                 (rate->sdiv << SDIV_SHIFT);
 106         writel(div_val, pll_base + 4);
 107         writel(rate->kdiv << KDIV_SHIFT, pll_base + 8);
 108
 109         __udelay(100);
 110
 111         /* Disable RST */
 112         tmp |= RST_MASK;
 113         writel(tmp, pll_base);
 114
 115         /* Wait Lock*/
 116         while (!(readl(pll_base) & LOCK_STATUS))
 117                 ;
 118
 119         /* Bypass */
 120         tmp &= ~BYPASS_MASK;
 121         writel(tmp, pll_base);
 122
 123         return 0;
 124 }
 125
 126 void dram_pll_init(ulong pll_val)
 127 {
 128         fracpll_configure(ANATOP_DRAM_PLL, pll_val);
 129 }
 130
 131 static struct dram_bypass_clk_setting imx8mm_dram_bypass_tbl[] = {
 132         DRAM_BYPASS_ROOT_CONFIG(MHZ(100), 2, CLK_ROOT_PRE_DIV1, 2,
 133                                 CLK_ROOT_PRE_DIV2),
 134         DRAM_BYPASS_ROOT_CONFIG(MHZ(250), 3, CLK_ROOT_PRE_DIV2, 2,
 135                                 CLK_ROOT_PRE_DIV2),
 136         DRAM_BYPASS_ROOT_CONFIG(MHZ(400), 1, CLK_ROOT_PRE_DIV2, 3,
 137                                 CLK_ROOT_PRE_DIV2),
 138 };
 139
 140 void dram_enable_bypass(ulong clk_val)
 141 {
 142         int i;
 143         struct dram_bypass_clk_setting *config;
 144
 145         for (i = 0; i < ARRAY_SIZE(imx8mm_dram_bypass_tbl); i++) {
 146                 if (clk_val == imx8mm_dram_bypass_tbl[i].clk)
 147                         break;
 148         }
 149
 150         if (i == ARRAY_SIZE(imx8mm_dram_bypass_tbl)) {
 151                 printf("%s: No matched freq table %lu\n", __func__, clk_val);
 152                 return;
 153         }
 154
 155         config = &imx8mm_dram_bypass_tbl[i];
 156
 157         clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON |
 158                              CLK_ROOT_SOURCE_SEL(config->alt_root_sel) |
 159                              CLK_ROOT_PRE_DIV(config->alt_pre_div));
 160         clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
 161                              CLK_ROOT_SOURCE_SEL(config->apb_root_sel) |
 162                              CLK_ROOT_PRE_DIV(config->apb_pre_div));
 163         clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
 164                              CLK_ROOT_SOURCE_SEL(1));
 165 }
 166
 167 void dram_disable_bypass(void)
 168 {
 169         clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
 170                              CLK_ROOT_SOURCE_SEL(0));
 171         clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
 172                              CLK_ROOT_SOURCE_SEL(4) |
 173                              CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV5));
 174 }
 175 #endif
 176
 177 int intpll_configure(enum pll_clocks pll, ulong freq)
 178 {
 179         void __iomem *pll_gnrl_ctl, __iomem *pll_div_ctl;
 180         u32 pll_div_ctl_val, pll_clke_masks;
 181
 182         switch (pll) {
 183         case ANATOP_SYSTEM_PLL1:
 184                 pll_gnrl_ctl = &ana_pll->sys_pll1_gnrl_ctl;
 185                 pll_div_ctl = &ana_pll->sys_pll1_div_ctl;
 186                 pll_clke_masks = INTPLL_DIV20_CLKE_MASK |
 187                         INTPLL_DIV10_CLKE_MASK | INTPLL_DIV8_CLKE_MASK |
 188                         INTPLL_DIV6_CLKE_MASK | INTPLL_DIV5_CLKE_MASK |
 189                         INTPLL_DIV4_CLKE_MASK | INTPLL_DIV3_CLKE_MASK |
 190                         INTPLL_DIV2_CLKE_MASK | INTPLL_CLKE_MASK;
 191                 break;
 192         case ANATOP_SYSTEM_PLL2:
 193                 pll_gnrl_ctl = &ana_pll->sys_pll2_gnrl_ctl;
 194                 pll_div_ctl = &ana_pll->sys_pll2_div_ctl;
 195                 pll_clke_masks = INTPLL_DIV20_CLKE_MASK |
 196                         INTPLL_DIV10_CLKE_MASK | INTPLL_DIV8_CLKE_MASK |
 197                         INTPLL_DIV6_CLKE_MASK | INTPLL_DIV5_CLKE_MASK |
 198                         INTPLL_DIV4_CLKE_MASK | INTPLL_DIV3_CLKE_MASK |
 199                         INTPLL_DIV2_CLKE_MASK | INTPLL_CLKE_MASK;
 200                 break;
 201         case ANATOP_SYSTEM_PLL3:
 202                 pll_gnrl_ctl = &ana_pll->sys_pll3_gnrl_ctl;
 203                 pll_div_ctl = &ana_pll->sys_pll3_div_ctl;
 204                 pll_clke_masks = INTPLL_CLKE_MASK;
 205                 break;
 206         case ANATOP_ARM_PLL:
 207                 pll_gnrl_ctl = &ana_pll->arm_pll_gnrl_ctl;
 208                 pll_div_ctl = &ana_pll->arm_pll_div_ctl;
 209                 pll_clke_masks = INTPLL_CLKE_MASK;
 210                 break;
 211         case ANATOP_GPU_PLL:
 212                 pll_gnrl_ctl = &ana_pll->gpu_pll_gnrl_ctl;
 213                 pll_div_ctl = &ana_pll->gpu_pll_div_ctl;
 214                 pll_clke_masks = INTPLL_CLKE_MASK;
 215                 break;
 216         case ANATOP_VPU_PLL:
 217                 pll_gnrl_ctl = &ana_pll->vpu_pll_gnrl_ctl;
 218                 pll_div_ctl = &ana_pll->vpu_pll_div_ctl;
 219                 pll_clke_masks = INTPLL_CLKE_MASK;
 220                 break;
 221         default:
 222                 return -EINVAL;
 223         };
 224
 225         switch (freq) {
 226         case MHZ(600):
 227                 /* 24 * 0x12c / 3 / 2 ^ 2 */
 228                 pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0x12c) |
 229                         INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(2);
 230                 break;
 231         case MHZ(750):
 232                 /* 24 * 0xfa / 2 / 2 ^ 2 */
 233                 pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xfa) |
 234                         INTPLL_PRE_DIV_VAL(2) | INTPLL_POST_DIV_VAL(2);
 235                 break;
 236         case MHZ(800):
 237                 /* 24 * 0x190 / 3 / 2 ^ 2 */
 238                 pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0x190) |
 239                         INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(2);
 240                 break;
 241         case MHZ(1000):
 242                 /* 24 * 0xfa / 3 / 2 ^ 1 */
 243                 pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xfa) |
 244                         INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(1);
 245                 break;
 246         case MHZ(1200):
 247                 /* 24 * 0xc8 / 2 / 2 ^ 1 */
 248                 pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xc8) |
 249                         INTPLL_PRE_DIV_VAL(2) | INTPLL_POST_DIV_VAL(1);
 250                 break;
 251         case MHZ(2000):
 252                 /* 24 * 0xfa / 3 / 2 ^ 0 */
 253                 pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xfa) |
 254                         INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(0);
 255                 break;
 256         default:
 257                 return -EINVAL;
 258         };
 259         /* Bypass clock and set lock to pll output lock */
 260         setbits_le32(pll_gnrl_ctl, INTPLL_BYPASS_MASK | INTPLL_LOCK_SEL_MASK);
 261         /* Enable reset */
 262         clrbits_le32(pll_gnrl_ctl, INTPLL_RST_MASK);
 263         /* Configure */
 264         writel(pll_div_ctl_val, pll_div_ctl);
 265
 266         __udelay(100);
 267
 268         /* Disable reset */
 269         setbits_le32(pll_gnrl_ctl, INTPLL_RST_MASK);
 270         /* Wait Lock */
 271         while (!(readl(pll_gnrl_ctl) & INTPLL_LOCK_MASK))
 272                 ;
 273         /* Clear bypass */
 274         clrbits_le32(pll_gnrl_ctl, INTPLL_BYPASS_MASK);
 275         setbits_le32(pll_gnrl_ctl, pll_clke_masks);
 276
 277         return 0;
 278 }
 279
 280 void init_uart_clk(u32 index)
 281 {
 282         /*
 283          * set uart clock root
 284          * 24M OSC
 285          */
 286         switch (index) {
 287         case 0:
 288                 clock_enable(CCGR_UART1, 0);
 289                 clock_set_target_val(UART1_CLK_ROOT, CLK_ROOT_ON |
 290                                      CLK_ROOT_SOURCE_SEL(0));
 291                 clock_enable(CCGR_UART1, 1);
 292                 return;
 293         case 1:
 294                 clock_enable(CCGR_UART2, 0);
 295                 clock_set_target_val(UART2_CLK_ROOT, CLK_ROOT_ON |
 296                                      CLK_ROOT_SOURCE_SEL(0));
 297                 clock_enable(CCGR_UART2, 1);
 298                 return;
 299         case 2:
 300                 clock_enable(CCGR_UART3, 0);
 301                 clock_set_target_val(UART3_CLK_ROOT, CLK_ROOT_ON |
 302                                      CLK_ROOT_SOURCE_SEL(0));
 303                 clock_enable(CCGR_UART3, 1);
 304                 return;
 305         case 3:
 306                 clock_enable(CCGR_UART4, 0);
 307                 clock_set_target_val(UART4_CLK_ROOT, CLK_ROOT_ON |
 308                                      CLK_ROOT_SOURCE_SEL(0));
 309                 clock_enable(CCGR_UART4, 1);
 310                 return;
 311         default:
 312                 printf("Invalid uart index\n");
 313                 return;
 314         }
 315 }
 316
 317 void init_wdog_clk(void)
 318 {
 319         clock_enable(CCGR_WDOG1, 0);
 320         clock_enable(CCGR_WDOG2, 0);
 321         clock_enable(CCGR_WDOG3, 0);
 322         clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
 323                              CLK_ROOT_SOURCE_SEL(0));
 324         clock_enable(CCGR_WDOG1, 1);
 325         clock_enable(CCGR_WDOG2, 1);
 326         clock_enable(CCGR_WDOG3, 1);
 327 }
 328
 329 void init_clk_usdhc(u32 index)
 330 {
 331         /*
 332          * set usdhc clock root
 333          * sys pll1 400M
 334          */
 335         switch (index) {
 336         case 0:
 337                 clock_enable(CCGR_USDHC1, 0);
 338                 clock_set_target_val(USDHC1_CLK_ROOT, CLK_ROOT_ON |
 339                                      CLK_ROOT_SOURCE_SEL(1));
 340                 clock_enable(CCGR_USDHC1, 1);
 341                 return;
 342         case 1:
 343                 clock_enable(CCGR_USDHC2, 0);
 344                 clock_set_target_val(USDHC2_CLK_ROOT, CLK_ROOT_ON |
 345                                      CLK_ROOT_SOURCE_SEL(1));
 346                 clock_enable(CCGR_USDHC2, 1);
 347                 return;
 348         case 2:
 349                 clock_enable(CCGR_USDHC3, 0);
 350                 clock_set_target_val(USDHC3_CLK_ROOT, CLK_ROOT_ON |
 351                                      CLK_ROOT_SOURCE_SEL(1));
 352                 clock_enable(CCGR_USDHC3, 1);
 353                 return;
 354         default:
 355                 printf("Invalid usdhc index\n");
 356                 return;
 357         }
 358 }
 359
 360 void init_clk_ecspi(u32 index)
 361 {
 362         switch (index) {
 363         case 0:
 364                 clock_enable(CCGR_ECSPI1, 0);
 365                 clock_set_target_val(ECSPI1_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0));
 366                 clock_enable(CCGR_ECSPI1, 1);
 367                 return;
 368         case 1:
 369                 clock_enable(CCGR_ECSPI2, 0);
 370                 clock_set_target_val(ECSPI2_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0));
 371                 clock_enable(CCGR_ECSPI2, 1);
 372                 return;
 373         case 2:
 374                 clock_enable(CCGR_ECSPI3, 0);
 375                 clock_set_target_val(ECSPI3_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0));
 376                 clock_enable(CCGR_ECSPI3, 1);
 377                 return;
 378         default:
 379                 printf("Invalid ecspi index\n");
 380                 return;
 381         }
 382 }
 383
 384 void init_nand_clk(void)
 385 {
 386         /*
 387          * set rawnand root
 388          * sys pll1 400M
 389          */
 390         clock_enable(CCGR_RAWNAND, 0);
 391         clock_set_target_val(NAND_CLK_ROOT, CLK_ROOT_ON |
 392                 CLK_ROOT_SOURCE_SEL(3) | CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4)); /* 100M */
 393         clock_enable(CCGR_RAWNAND, 1);
 394 }
 395
 396 int clock_init(void)
 397 {
 398         u32 val_cfg0;
 399
 400         /*
 401          * The gate is not exported to clk tree, so configure them here.
 402          * According to ANAMIX SPEC
 403          * sys pll1 fixed at 800MHz
 404          * sys pll2 fixed at 1GHz
 405          * Here we only enable the outputs.
 406          */
 407         val_cfg0 = readl(&ana_pll->sys_pll1_gnrl_ctl);
 408         val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK |
 409                 INTPLL_DIV3_CLKE_MASK | INTPLL_DIV4_CLKE_MASK |
 410                 INTPLL_DIV5_CLKE_MASK | INTPLL_DIV6_CLKE_MASK |
 411                 INTPLL_DIV8_CLKE_MASK | INTPLL_DIV10_CLKE_MASK |
 412                 INTPLL_DIV20_CLKE_MASK;
 413         writel(val_cfg0, &ana_pll->sys_pll1_gnrl_ctl);
 414
 415         val_cfg0 = readl(&ana_pll->sys_pll2_gnrl_ctl);
 416         val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK |
 417                 INTPLL_DIV3_CLKE_MASK | INTPLL_DIV4_CLKE_MASK |
 418                 INTPLL_DIV5_CLKE_MASK | INTPLL_DIV6_CLKE_MASK |
 419                 INTPLL_DIV8_CLKE_MASK | INTPLL_DIV10_CLKE_MASK |
 420                 INTPLL_DIV20_CLKE_MASK;
 421         writel(val_cfg0, &ana_pll->sys_pll2_gnrl_ctl);
 422
 423         /* Configure ARM at 1.2GHz */
 424         clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
 425                              CLK_ROOT_SOURCE_SEL(2));
 426
 427         intpll_configure(ANATOP_ARM_PLL, MHZ(1200));
 428
 429         /* Bypass CCM A53 ROOT, Switch to ARM PLL -> MUX-> CPU */
 430         clock_set_target_val(CORE_SEL_CFG, CLK_ROOT_SOURCE_SEL(1));
 431
 432         if (is_imx8mn() || is_imx8mp())
 433                 intpll_configure(ANATOP_SYSTEM_PLL3, MHZ(600));
 434         else
 435                 intpll_configure(ANATOP_SYSTEM_PLL3, MHZ(750));
 436
 437 #ifdef CONFIG_IMX8MP
 438         /* 8MP ROM already set NOC to 800Mhz, only need to configure NOC_IO clk to 600Mhz */
 439         /* 8MP ROM already set GIC to 400Mhz, system_pll1_800m with div = 2 */
 440         clock_set_target_val(NOC_IO_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(2));
 441 #else
 442         clock_set_target_val(NOC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(2));
 443
 444         /* config GIC to sys_pll2_100m */
 445         clock_enable(CCGR_GIC, 0);
 446         clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON |
 447                              CLK_ROOT_SOURCE_SEL(3));
 448         clock_enable(CCGR_GIC, 1);
 449 #endif
 450
 451         clock_set_target_val(NAND_USDHC_BUS_CLK_ROOT, CLK_ROOT_ON |
 452                              CLK_ROOT_SOURCE_SEL(1));
 453
 454         clock_enable(CCGR_DDR1, 0);
 455         clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON |
 456                              CLK_ROOT_SOURCE_SEL(1));
 457         clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
 458                              CLK_ROOT_SOURCE_SEL(1));
 459         clock_enable(CCGR_DDR1, 1);
 460
 461         init_wdog_clk();
 462
 463         clock_enable(CCGR_TEMP_SENSOR, 1);
 464
 465         clock_enable(CCGR_SEC_DEBUG, 1);
 466
 467         return 0;
 468 };
 469
 470 u32 imx_get_uartclk(void)
 471 {
 472         return 24000000U;
 473 }
 474
 475 static u32 decode_intpll(enum clk_root_src intpll)
 476 {
 477         u32 pll_gnrl_ctl, pll_div_ctl, pll_clke_mask;
 478         u32 main_div, pre_div, post_div, div;
 479         u64 freq;
 480
 481         switch (intpll) {
 482         case ARM_PLL_CLK:
 483                 pll_gnrl_ctl = readl(&ana_pll->arm_pll_gnrl_ctl);
 484                 pll_div_ctl = readl(&ana_pll->arm_pll_div_ctl);
 485                 break;
 486         case GPU_PLL_CLK:
 487                 pll_gnrl_ctl = readl(&ana_pll->gpu_pll_gnrl_ctl);
 488                 pll_div_ctl = readl(&ana_pll->gpu_pll_div_ctl);
 489                 break;
 490         case VPU_PLL_CLK:
 491                 pll_gnrl_ctl = readl(&ana_pll->vpu_pll_gnrl_ctl);
 492                 pll_div_ctl = readl(&ana_pll->vpu_pll_div_ctl);
 493                 break;
 494         case SYSTEM_PLL1_800M_CLK:
 495         case SYSTEM_PLL1_400M_CLK:
 496         case SYSTEM_PLL1_266M_CLK:
 497         case SYSTEM_PLL1_200M_CLK:
 498         case SYSTEM_PLL1_160M_CLK:
 499         case SYSTEM_PLL1_133M_CLK:
 500         case SYSTEM_PLL1_100M_CLK:
 501         case SYSTEM_PLL1_80M_CLK:
 502         case SYSTEM_PLL1_40M_CLK:
 503                 pll_gnrl_ctl = readl(&ana_pll->sys_pll1_gnrl_ctl);
 504                 pll_div_ctl = readl(&ana_pll->sys_pll1_div_ctl);
 505                 break;
 506         case SYSTEM_PLL2_1000M_CLK:
 507         case SYSTEM_PLL2_500M_CLK:
 508         case SYSTEM_PLL2_333M_CLK:
 509         case SYSTEM_PLL2_250M_CLK:
 510         case SYSTEM_PLL2_200M_CLK:
 511         case SYSTEM_PLL2_166M_CLK:
 512         case SYSTEM_PLL2_125M_CLK:
 513         case SYSTEM_PLL2_100M_CLK:
 514         case SYSTEM_PLL2_50M_CLK:
 515                 pll_gnrl_ctl = readl(&ana_pll->sys_pll2_gnrl_ctl);
 516                 pll_div_ctl = readl(&ana_pll->sys_pll2_div_ctl);
 517                 break;
 518         case SYSTEM_PLL3_CLK:
 519                 pll_gnrl_ctl = readl(&ana_pll->sys_pll3_gnrl_ctl);
 520                 pll_div_ctl = readl(&ana_pll->sys_pll3_div_ctl);
 521                 break;
 522         default:
 523                 return -EINVAL;
 524         }
 525
 526         /* Only support SYS_XTAL 24M, PAD_CLK not take into consideration */
 527         if ((pll_gnrl_ctl & INTPLL_REF_CLK_SEL_MASK) != 0)
 528                 return 0;
 529
 530         if ((pll_gnrl_ctl & INTPLL_RST_MASK) == 0)
 531                 return 0;
 532
 533         /*
 534          * When BYPASS is equal to 1, PLL enters the bypass mode
 535          * regardless of the values of RESETB
 536          */
 537         if (pll_gnrl_ctl & INTPLL_BYPASS_MASK)
 538                 return 24000000u;
 539
 540         if (!(pll_gnrl_ctl & INTPLL_LOCK_MASK)) {
 541                 puts("pll not locked\n");
 542                 return 0;
 543         }
 544
 545         switch (intpll) {
 546         case ARM_PLL_CLK:
 547         case GPU_PLL_CLK:
 548         case VPU_PLL_CLK:
 549         case SYSTEM_PLL3_CLK:
 550         case SYSTEM_PLL1_800M_CLK:
 551         case SYSTEM_PLL2_1000M_CLK:
 552                 pll_clke_mask = INTPLL_CLKE_MASK;
 553                 div = 1;
 554                 break;
 555
 556         case SYSTEM_PLL1_400M_CLK:
 557         case SYSTEM_PLL2_500M_CLK:
 558                 pll_clke_mask = INTPLL_DIV2_CLKE_MASK;
 559                 div = 2;
 560                 break;
 561
 562         case SYSTEM_PLL1_266M_CLK:
 563         case SYSTEM_PLL2_333M_CLK:
 564                 pll_clke_mask = INTPLL_DIV3_CLKE_MASK;
 565                 div = 3;
 566                 break;
 567
 568         case SYSTEM_PLL1_200M_CLK:
 569         case SYSTEM_PLL2_250M_CLK:
 570                 pll_clke_mask = INTPLL_DIV4_CLKE_MASK;
 571                 div = 4;
 572                 break;
 573
 574         case SYSTEM_PLL1_160M_CLK:
 575         case SYSTEM_PLL2_200M_CLK:
 576                 pll_clke_mask = INTPLL_DIV5_CLKE_MASK;
 577                 div = 5;
 578                 break;
 579
 580         case SYSTEM_PLL1_133M_CLK:
 581         case SYSTEM_PLL2_166M_CLK:
 582                 pll_clke_mask = INTPLL_DIV6_CLKE_MASK;
 583                 div = 6;
 584                 break;
 585
 586         case SYSTEM_PLL1_100M_CLK:
 587         case SYSTEM_PLL2_125M_CLK:
 588                 pll_clke_mask = INTPLL_DIV8_CLKE_MASK;
 589                 div = 8;
 590                 break;
 591
 592         case SYSTEM_PLL1_80M_CLK:
 593         case SYSTEM_PLL2_100M_CLK:
 594                 pll_clke_mask = INTPLL_DIV10_CLKE_MASK;
 595                 div = 10;
 596                 break;
 597
 598         case SYSTEM_PLL1_40M_CLK:
 599         case SYSTEM_PLL2_50M_CLK:
 600                 pll_clke_mask = INTPLL_DIV20_CLKE_MASK;
 601                 div = 20;
 602                 break;
 603         default:
 604                 return -EINVAL;
 605         }
 606
 607         if ((pll_gnrl_ctl & pll_clke_mask) == 0)
 608                 return 0;
 609
 610         main_div = (pll_div_ctl & INTPLL_MAIN_DIV_MASK) >>
 611                 INTPLL_MAIN_DIV_SHIFT;
 612         pre_div = (pll_div_ctl & INTPLL_PRE_DIV_MASK) >>
 613                 INTPLL_PRE_DIV_SHIFT;
 614         post_div = (pll_div_ctl & INTPLL_POST_DIV_MASK) >>
 615                 INTPLL_POST_DIV_SHIFT;
 616
 617         /* FFVCO = (m * FFIN) / p, FFOUT = (m * FFIN) / (p * 2^s) */
 618         freq = 24000000ULL * main_div;
 619         return lldiv(freq, pre_div * (1 << post_div) * div);
 620 }
 621
 622 static u32 decode_fracpll(enum clk_root_src frac_pll)
 623 {
 624         u32 pll_gnrl_ctl, pll_fdiv_ctl0, pll_fdiv_ctl1;
 625         u32 main_div, pre_div, post_div, k;
 626
 627         switch (frac_pll) {
 628         case DRAM_PLL1_CLK:
 629                 pll_gnrl_ctl = readl(&ana_pll->dram_pll_gnrl_ctl);
 630                 pll_fdiv_ctl0 = readl(&ana_pll->dram_pll_fdiv_ctl0);
 631                 pll_fdiv_ctl1 = readl(&ana_pll->dram_pll_fdiv_ctl1);
 632                 break;
 633         case AUDIO_PLL1_CLK:
 634                 pll_gnrl_ctl = readl(&ana_pll->audio_pll1_gnrl_ctl);
 635                 pll_fdiv_ctl0 = readl(&ana_pll->audio_pll1_fdiv_ctl0);
 636                 pll_fdiv_ctl1 = readl(&ana_pll->audio_pll1_fdiv_ctl1);
 637                 break;
 638         case AUDIO_PLL2_CLK:
 639                 pll_gnrl_ctl = readl(&ana_pll->audio_pll2_gnrl_ctl);
 640                 pll_fdiv_ctl0 = readl(&ana_pll->audio_pll2_fdiv_ctl0);
 641                 pll_fdiv_ctl1 = readl(&ana_pll->audio_pll2_fdiv_ctl1);
 642                 break;
 643         case VIDEO_PLL_CLK:
 644                 pll_gnrl_ctl = readl(&ana_pll->video_pll1_gnrl_ctl);
 645                 pll_fdiv_ctl0 = readl(&ana_pll->video_pll1_fdiv_ctl0);
 646                 pll_fdiv_ctl1 = readl(&ana_pll->video_pll1_fdiv_ctl1);
 647                 break;
 648         default:
 649                 printf("Unsupported clk_root_src %d\n", frac_pll);
 650                 return 0;
 651         }
 652
 653         /* Only support SYS_XTAL 24M, PAD_CLK not take into consideration */
 654         if ((pll_gnrl_ctl & GENMASK(1, 0)) != 0)
 655                 return 0;
 656
 657         if ((pll_gnrl_ctl & RST_MASK) == 0)
 658                 return 0;
 659         /*
 660          * When BYPASS is equal to 1, PLL enters the bypass mode
 661          * regardless of the values of RESETB
 662          */
 663         if (pll_gnrl_ctl & BYPASS_MASK)
 664                 return 24000000u;
 665
 666         if (!(pll_gnrl_ctl & LOCK_STATUS)) {
 667                 puts("pll not locked\n");
 668                 return 0;
 669         }
 670
 671         if (!(pll_gnrl_ctl & CLKE_MASK))
 672                 return 0;
 673
 674         main_div = (pll_fdiv_ctl0 & MDIV_MASK) >>
 675                 MDIV_SHIFT;
 676         pre_div = (pll_fdiv_ctl0 & PDIV_MASK) >>
 677                 PDIV_SHIFT;
 678         post_div = (pll_fdiv_ctl0 & SDIV_MASK) >>
 679                 SDIV_SHIFT;
 680
 681         k = pll_fdiv_ctl1 & KDIV_MASK;
 682
 683         return lldiv((main_div * 65536 + k) * 24000000ULL,
 684                      65536 * pre_div * (1 << post_div));
 685 }
 686
 687 static u32 get_root_src_clk(enum clk_root_src root_src)
 688 {
 689         switch (root_src) {
 690         case OSC_24M_CLK:
 691                 return 24000000u;
 692         case OSC_HDMI_CLK:
 693                 return 26000000u;
 694         case OSC_32K_CLK:
 695                 return 32000u;
 696         case ARM_PLL_CLK:
 697         case GPU_PLL_CLK:
 698         case VPU_PLL_CLK:
 699         case SYSTEM_PLL1_800M_CLK:
 700         case SYSTEM_PLL1_400M_CLK:
 701         case SYSTEM_PLL1_266M_CLK:
 702         case SYSTEM_PLL1_200M_CLK:
 703         case SYSTEM_PLL1_160M_CLK:
 704         case SYSTEM_PLL1_133M_CLK:
 705         case SYSTEM_PLL1_100M_CLK:
 706         case SYSTEM_PLL1_80M_CLK:
 707         case SYSTEM_PLL1_40M_CLK:
 708         case SYSTEM_PLL2_1000M_CLK:
 709         case SYSTEM_PLL2_500M_CLK:
 710         case SYSTEM_PLL2_333M_CLK:
 711         case SYSTEM_PLL2_250M_CLK:
 712         case SYSTEM_PLL2_200M_CLK:
 713         case SYSTEM_PLL2_166M_CLK:
 714         case SYSTEM_PLL2_125M_CLK:
 715         case SYSTEM_PLL2_100M_CLK:
 716         case SYSTEM_PLL2_50M_CLK:
 717         case SYSTEM_PLL3_CLK:
 718                 return decode_intpll(root_src);
 719         case DRAM_PLL1_CLK:
 720         case AUDIO_PLL1_CLK:
 721         case AUDIO_PLL2_CLK:
 722         case VIDEO_PLL_CLK:
 723                 return decode_fracpll(root_src);
 724         case ARM_A53_ALT_CLK:
 725                 return get_root_clk(ARM_A53_CLK_ROOT);
 726         default:
 727                 return 0;
 728         }
 729
 730         return 0;
 731 }
 732
 733 static u32 get_root_clk(enum clk_root_index clock_id)
 734 {
 735         enum clk_root_src root_src;
 736         u32 post_podf, pre_podf, root_src_clk;
 737
 738         if (clock_root_enabled(clock_id) <= 0)
 739                 return 0;
 740
 741         if (clock_get_prediv(clock_id, &pre_podf) < 0)
 742                 return 0;
 743
 744         if (clock_get_postdiv(clock_id, &post_podf) < 0)
 745                 return 0;
 746
 747         if (clock_get_src(clock_id, &root_src) < 0)
 748                 return 0;
 749
 750         root_src_clk = get_root_src_clk(root_src);
 751
 752         return root_src_clk / (post_podf + 1) / (pre_podf + 1);
 753 }
 754
 755 u32 get_arm_core_clk(void)
 756 {
 757         enum clk_root_src root_src;
 758         u32 root_src_clk;
 759
 760         if (clock_get_src(CORE_SEL_CFG, &root_src) < 0)
 761                 return 0;
 762
 763         root_src_clk = get_root_src_clk(root_src);
 764
 765         return root_src_clk;
 766 }
 767
 768 u32 mxc_get_clock(enum mxc_clock clk)
 769 {
 770         u32 val;
 771
 772         switch (clk) {
 773         case MXC_ARM_CLK:
 774                 return get_arm_core_clk();
 775         case MXC_IPG_CLK:
 776                 clock_get_target_val(IPG_CLK_ROOT, &val);
 777                 val = val & 0x3;
 778                 return get_root_clk(AHB_CLK_ROOT) / 2 / (val + 1);
 779         case MXC_CSPI_CLK:
 780                 return get_root_clk(ECSPI1_CLK_ROOT);
 781         case MXC_ESDHC_CLK:
 782                 return get_root_clk(USDHC1_CLK_ROOT);
 783         case MXC_ESDHC2_CLK:
 784                 return get_root_clk(USDHC2_CLK_ROOT);
 785         case MXC_ESDHC3_CLK:
 786                 return get_root_clk(USDHC3_CLK_ROOT);
 787         case MXC_I2C_CLK:
 788                 return get_root_clk(I2C1_CLK_ROOT);
 789         case MXC_UART_CLK:
 790                 return get_root_clk(UART1_CLK_ROOT);
 791         case MXC_QSPI_CLK:
 792                 return get_root_clk(QSPI_CLK_ROOT);
 793         default:
 794                 printf("Unsupported mxc_clock %d\n", clk);
 795                 break;
 796         }
 797
 798         return 0;
 799 }
 800
 801 #ifdef CONFIG_DWC_ETH_QOS
 802 int set_clk_eqos(enum enet_freq type)
 803 {
 804         u32 target;
 805         u32 enet1_ref;
 806
 807         switch (type) {
 808         case ENET_125MHZ:
 809                 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
 810                 break;
 811         case ENET_50MHZ:
 812                 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
 813                 break;
 814         case ENET_25MHZ:
 815                 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
 816                 break;
 817         default:
 818                 return -EINVAL;
 819         }
 820
 821         /* disable the clock first */
 822         clock_enable(CCGR_QOS_ETHENET, 0);
 823         clock_enable(CCGR_SDMA2, 0);
 824
 825         /* set enet axi clock 266Mhz */
 826         target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M |
 827                  CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
 828                  CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
 829         clock_set_target_val(ENET_AXI_CLK_ROOT, target);
 830
 831         target = CLK_ROOT_ON | enet1_ref |
 832                  CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
 833                  CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
 834         clock_set_target_val(ENET_QOS_CLK_ROOT, target);
 835
 836         target = CLK_ROOT_ON |
 837                 ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
 838                 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
 839                 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
 840         clock_set_target_val(ENET_QOS_TIMER_CLK_ROOT, target);
 841
 842         /* enable clock */
 843         clock_enable(CCGR_QOS_ETHENET, 1);
 844         clock_enable(CCGR_SDMA2, 1);
 845
 846         return 0;
 847 }
 848
 849 int imx_eqos_txclk_set_rate(ulong rate)
 850 {
 851         u32 val;
 852         u32 eqos_post_div;
 853
 854         /* disable the clock first */
 855         clock_enable(CCGR_QOS_ETHENET, 0);
 856         clock_enable(CCGR_SDMA2, 0);
 857
 858         switch (rate) {
 859         case 125000000:
 860                 eqos_post_div = 1;
 861                 break;
 862         case 25000000:
 863                 eqos_post_div = 125000000 / 25000000;
 864                 break;
 865         case 2500000:
 866                 eqos_post_div = 125000000 / 2500000;
 867                 break;
 868         default:
 869                 return -EINVAL;
 870         }
 871
 872         clock_get_target_val(ENET_QOS_CLK_ROOT, &val);
 873         val &= ~(CLK_ROOT_PRE_DIV_MASK | CLK_ROOT_POST_DIV_MASK);
 874         val |= CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
 875                CLK_ROOT_POST_DIV(eqos_post_div - 1);
 876         clock_set_target_val(ENET_QOS_CLK_ROOT, val);
 877
 878         /* enable clock */
 879         clock_enable(CCGR_QOS_ETHENET, 1);
 880         clock_enable(CCGR_SDMA2, 1);
 881
 882         return 0;
 883 }
 884
 885 u32 imx_get_eqos_csr_clk(void)
 886 {
 887         return get_root_clk(ENET_AXI_CLK_ROOT);
 888 }
 889 #endif
 890
 891 #ifdef CONFIG_FEC_MXC
 892 int set_clk_enet(enum enet_freq type)
 893 {
 894         u32 target;
 895         u32 enet1_ref;
 896
 897         switch (type) {
 898         case ENET_125MHZ:
 899                 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
 900                 break;
 901         case ENET_50MHZ:
 902                 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
 903                 break;
 904         case ENET_25MHZ:
 905                 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
 906                 break;
 907         default:
 908                 return -EINVAL;
 909         }
 910
 911         /* disable the clock first */
 912         clock_enable(CCGR_ENET1, 0);
 913         clock_enable(CCGR_SIM_ENET, 0);
 914
 915         /* set enet axi clock 266Mhz */
 916         target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M |
 917                  CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
 918                  CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
 919         clock_set_target_val(ENET_AXI_CLK_ROOT, target);
 920
 921         target = CLK_ROOT_ON | enet1_ref |
 922                  CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
 923                  CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
 924         clock_set_target_val(ENET_REF_CLK_ROOT, target);
 925
 926         target = CLK_ROOT_ON |
 927                 ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
 928                 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
 929                 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
 930         clock_set_target_val(ENET_TIMER_CLK_ROOT, target);
 931
 932         /* enable clock */
 933         clock_enable(CCGR_SIM_ENET, 1);
 934         clock_enable(CCGR_ENET1, 1);
 935
 936         return 0;
 937 }
 938 #endif