arch/arm/mach-imx/imx8m/clock_imx8mm.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2018-2019 NXP
   4  *
   5  * Peng Fan <[email protected]>
   6  */
   7
   8 #include <common.h>
   9 #include <asm/arch/clock.h>
  10 #include <asm/arch/imx-regs.h>
  11 #include <asm/arch/sys_proto.h>
  12 #include <asm/global_data.h>
  13 #include <asm/io.h>
  14 #include <div64.h>
  15 #include <errno.h>
  16 #include <linux/bitops.h>
  17 #include <linux/delay.h>
  18 #include <phy.h>
  19
  20 DECLARE_GLOBAL_DATA_PTR;
  21
  22 static struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
  23
  24 static u32 get_root_clk(enum clk_root_index clock_id);
  25
  26 #ifdef CONFIG_IMX_HAB
  27 void hab_caam_clock_enable(unsigned char enable)
  28 {
  29         /* The CAAM clock is always on for iMX8M */
  30 }
  31 #endif
  32
  33 void enable_ocotp_clk(unsigned char enable)
  34 {
  35         clock_enable(CCGR_OCOTP, !!enable);
  36 }
  37
  38 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
  39 {
  40         u8 i2c_ccgr[] = {
  41                         CCGR_I2C1, CCGR_I2C2, CCGR_I2C3, CCGR_I2C4,
  42 #if (IS_ENABLED(CONFIG_IMX8MP))
  43                         CCGR_I2C5_8MP, CCGR_I2C6_8MP
  44 #endif
  45         };
  46
  47         if (i2c_num >= ARRAY_SIZE(i2c_ccgr))
  48                 return -EINVAL;
  49
  50         clock_enable(i2c_ccgr[i2c_num], !!enable);
  51
  52         return 0;
  53 }
  54
  55 #ifdef CONFIG_SPL_BUILD
  56 static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = {
  57         PLL_1443X_RATE(1000000000U, 250, 3, 1, 0),
  58         PLL_1443X_RATE(933000000U, 311, 4, 1, 0),
  59         PLL_1443X_RATE(800000000U, 300, 9, 0, 0),
  60         PLL_1443X_RATE(750000000U, 250, 8, 0, 0),
  61         PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
  62         PLL_1443X_RATE(600000000U, 300, 3, 2, 0),
  63         PLL_1443X_RATE(594000000U, 99, 1, 2, 0),
  64         PLL_1443X_RATE(400000000U, 300, 9, 1, 0),
  65         PLL_1443X_RATE(266000000U, 400, 9, 2, 0),
  66         PLL_1443X_RATE(167000000U, 334, 3, 4, 0),
  67         PLL_1443X_RATE(100000000U, 300, 9, 3, 0),
  68 };
  69
  70 static int fracpll_configure(enum pll_clocks pll, u32 freq)
  71 {
  72         int i;
  73         u32 tmp, div_val;
  74         void *pll_base;
  75         struct imx_int_pll_rate_table *rate;
  76
  77         for (i = 0; i < ARRAY_SIZE(imx8mm_fracpll_tbl); i++) {
  78                 if (freq == imx8mm_fracpll_tbl[i].rate)
  79                         break;
  80         }
  81
  82         if (i == ARRAY_SIZE(imx8mm_fracpll_tbl)) {
  83                 printf("%s: No matched freq table %u\n", __func__, freq);
  84                 return -EINVAL;
  85         }
  86
  87         rate = &imx8mm_fracpll_tbl[i];
  88
  89         switch (pll) {
  90         case ANATOP_DRAM_PLL:
  91                 setbits_le32(GPC_BASE_ADDR + 0xEC, 1 << 7);
  92                 setbits_le32(GPC_BASE_ADDR + 0xF8, 1 << 5);
  93
  94                 pll_base = &ana_pll->dram_pll_gnrl_ctl;
  95                 break;
  96         case ANATOP_VIDEO_PLL:
  97                 pll_base = &ana_pll->video_pll1_gnrl_ctl;
  98                 break;
  99         default:
 100                 return 0;
 101         }
 102         /* Bypass clock and set lock to pll output lock */
 103         tmp = readl(pll_base);
 104         tmp |= BYPASS_MASK;
 105         writel(tmp, pll_base);
 106
 107         /* Enable RST */
 108         tmp &= ~RST_MASK;
 109         writel(tmp, pll_base);
 110
 111         div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) |
 112                 (rate->sdiv << SDIV_SHIFT);
 113         writel(div_val, pll_base + 4);
 114         writel(rate->kdiv << KDIV_SHIFT, pll_base + 8);
 115
 116         __udelay(100);
 117
 118         /* Disable RST */
 119         tmp |= RST_MASK;
 120         writel(tmp, pll_base);
 121
 122         /* Wait Lock*/
 123         while (!(readl(pll_base) & LOCK_STATUS))
 124                 ;
 125
 126         /* Bypass */
 127         tmp &= ~BYPASS_MASK;
 128         writel(tmp, pll_base);
 129
 130         return 0;
 131 }
 132
 133 void dram_pll_init(ulong pll_val)
 134 {
 135         fracpll_configure(ANATOP_DRAM_PLL, pll_val);
 136 }
 137
 138 static struct dram_bypass_clk_setting imx8mm_dram_bypass_tbl[] = {
 139         DRAM_BYPASS_ROOT_CONFIG(MHZ(100), 2, CLK_ROOT_PRE_DIV1, 2,
 140                                 CLK_ROOT_PRE_DIV2),
 141         DRAM_BYPASS_ROOT_CONFIG(MHZ(250), 3, CLK_ROOT_PRE_DIV2, 2,
 142                                 CLK_ROOT_PRE_DIV2),
 143         DRAM_BYPASS_ROOT_CONFIG(MHZ(400), 1, CLK_ROOT_PRE_DIV2, 3,
 144                                 CLK_ROOT_PRE_DIV2),
 145 };
 146
 147 void dram_enable_bypass(ulong clk_val)
 148 {
 149         int i;
 150         struct dram_bypass_clk_setting *config;
 151
 152         for (i = 0; i < ARRAY_SIZE(imx8mm_dram_bypass_tbl); i++) {
 153                 if (clk_val == imx8mm_dram_bypass_tbl[i].clk)
 154                         break;
 155         }
 156
 157         if (i == ARRAY_SIZE(imx8mm_dram_bypass_tbl)) {
 158                 printf("%s: No matched freq table %lu\n", __func__, clk_val);
 159                 return;
 160         }
 161
 162         config = &imx8mm_dram_bypass_tbl[i];
 163
 164         clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON |
 165                              CLK_ROOT_SOURCE_SEL(config->alt_root_sel) |
 166                              CLK_ROOT_PRE_DIV(config->alt_pre_div));
 167         clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
 168                              CLK_ROOT_SOURCE_SEL(config->apb_root_sel) |
 169                              CLK_ROOT_PRE_DIV(config->apb_pre_div));
 170         clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
 171                              CLK_ROOT_SOURCE_SEL(1));
 172 }
 173
 174 void dram_disable_bypass(void)
 175 {
 176         clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
 177                              CLK_ROOT_SOURCE_SEL(0));
 178         clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
 179                              CLK_ROOT_SOURCE_SEL(4) |
 180                              CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV5));
 181 }
 182 #endif
 183
 184 int intpll_configure(enum pll_clocks pll, ulong freq)
 185 {
 186         void __iomem *pll_gnrl_ctl, __iomem *pll_div_ctl;
 187         u32 pll_div_ctl_val, pll_clke_masks;
 188
 189         switch (pll) {
 190         case ANATOP_SYSTEM_PLL1:
 191                 pll_gnrl_ctl = &ana_pll->sys_pll1_gnrl_ctl;
 192                 pll_div_ctl = &ana_pll->sys_pll1_div_ctl;
 193                 pll_clke_masks = INTPLL_DIV20_CLKE_MASK |
 194                         INTPLL_DIV10_CLKE_MASK | INTPLL_DIV8_CLKE_MASK |
 195                         INTPLL_DIV6_CLKE_MASK | INTPLL_DIV5_CLKE_MASK |
 196                         INTPLL_DIV4_CLKE_MASK | INTPLL_DIV3_CLKE_MASK |
 197                         INTPLL_DIV2_CLKE_MASK | INTPLL_CLKE_MASK;
 198                 break;
 199         case ANATOP_SYSTEM_PLL2:
 200                 pll_gnrl_ctl = &ana_pll->sys_pll2_gnrl_ctl;
 201                 pll_div_ctl = &ana_pll->sys_pll2_div_ctl;
 202                 pll_clke_masks = INTPLL_DIV20_CLKE_MASK |
 203                         INTPLL_DIV10_CLKE_MASK | INTPLL_DIV8_CLKE_MASK |
 204                         INTPLL_DIV6_CLKE_MASK | INTPLL_DIV5_CLKE_MASK |
 205                         INTPLL_DIV4_CLKE_MASK | INTPLL_DIV3_CLKE_MASK |
 206                         INTPLL_DIV2_CLKE_MASK | INTPLL_CLKE_MASK;
 207                 break;
 208         case ANATOP_SYSTEM_PLL3:
 209                 pll_gnrl_ctl = &ana_pll->sys_pll3_gnrl_ctl;
 210                 pll_div_ctl = &ana_pll->sys_pll3_div_ctl;
 211                 pll_clke_masks = INTPLL_CLKE_MASK;
 212                 break;
 213         case ANATOP_ARM_PLL:
 214                 pll_gnrl_ctl = &ana_pll->arm_pll_gnrl_ctl;
 215                 pll_div_ctl = &ana_pll->arm_pll_div_ctl;
 216                 pll_clke_masks = INTPLL_CLKE_MASK;
 217                 break;
 218         case ANATOP_GPU_PLL:
 219                 pll_gnrl_ctl = &ana_pll->gpu_pll_gnrl_ctl;
 220                 pll_div_ctl = &ana_pll->gpu_pll_div_ctl;
 221                 pll_clke_masks = INTPLL_CLKE_MASK;
 222                 break;
 223         case ANATOP_VPU_PLL:
 224                 pll_gnrl_ctl = &ana_pll->vpu_pll_gnrl_ctl;
 225                 pll_div_ctl = &ana_pll->vpu_pll_div_ctl;
 226                 pll_clke_masks = INTPLL_CLKE_MASK;
 227                 break;
 228         default:
 229                 return -EINVAL;
 230         };
 231
 232         switch (freq) {
 233         case MHZ(600):
 234                 /* 24 * 0x12c / 3 / 2 ^ 2 */
 235                 pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0x12c) |
 236                         INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(2);
 237                 break;
 238         case MHZ(750):
 239                 /* 24 * 0xfa / 2 / 2 ^ 2 */
 240                 pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xfa) |
 241                         INTPLL_PRE_DIV_VAL(2) | INTPLL_POST_DIV_VAL(2);
 242                 break;
 243         case MHZ(800):
 244                 /* 24 * 0x190 / 3 / 2 ^ 2 */
 245                 pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0x190) |
 246                         INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(2);
 247                 break;
 248         case MHZ(1000):
 249                 /* 24 * 0xfa / 3 / 2 ^ 1 */
 250                 pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xfa) |
 251                         INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(1);
 252                 break;
 253         case MHZ(1200):
 254                 /* 24 * 0x12c / 3 / 2 ^ 1 */
 255                 pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0x12c) |
 256                         INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(1);
 257                 break;
 258         case MHZ(1400):
 259                 /* 24 * 0x15e / 3 / 2 ^ 1 */
 260                 pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0x15e) |
 261                         INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(1);
 262                 break;
 263         case MHZ(1500):
 264                 /* 24 * 0x177 / 3 / 2 ^ 1 */
 265                 pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0x177) |
 266                         INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(1);
 267                 break;
 268         case MHZ(1600):
 269                 /* 24 * 0xc8 / 3 / 2 ^ 0 */
 270                 pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xc8) |
 271                         INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(0);
 272                 break;
 273         case MHZ(1800):
 274                 /* 24 * 0xe1 / 3 / 2 ^ 0 */
 275                 pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xe1) |
 276                         INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(0);
 277                 break;
 278         case MHZ(2000):
 279                 /* 24 * 0xfa / 3 / 2 ^ 0 */
 280                 pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xfa) |
 281                         INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(0);
 282                 break;
 283         default:
 284                 return -EINVAL;
 285         };
 286         /* Bypass clock and set lock to pll output lock */
 287         setbits_le32(pll_gnrl_ctl, INTPLL_BYPASS_MASK | INTPLL_LOCK_SEL_MASK);
 288         /* Enable reset */
 289         clrbits_le32(pll_gnrl_ctl, INTPLL_RST_MASK);
 290         /* Configure */
 291         writel(pll_div_ctl_val, pll_div_ctl);
 292
 293         __udelay(100);
 294
 295         /* Disable reset */
 296         setbits_le32(pll_gnrl_ctl, INTPLL_RST_MASK);
 297         /* Wait Lock */
 298         while (!(readl(pll_gnrl_ctl) & INTPLL_LOCK_MASK))
 299                 ;
 300         /* Clear bypass */
 301         clrbits_le32(pll_gnrl_ctl, INTPLL_BYPASS_MASK);
 302         setbits_le32(pll_gnrl_ctl, pll_clke_masks);
 303
 304         return 0;
 305 }
 306
 307 void init_uart_clk(u32 index)
 308 {
 309         /*
 310          * set uart clock root
 311          * 24M OSC
 312          */
 313         switch (index) {
 314         case 0:
 315                 clock_enable(CCGR_UART1, 0);
 316                 clock_set_target_val(UART1_CLK_ROOT, CLK_ROOT_ON |
 317                                      CLK_ROOT_SOURCE_SEL(0));
 318                 clock_enable(CCGR_UART1, 1);
 319                 return;
 320         case 1:
 321                 clock_enable(CCGR_UART2, 0);
 322                 clock_set_target_val(UART2_CLK_ROOT, CLK_ROOT_ON |
 323                                      CLK_ROOT_SOURCE_SEL(0));
 324                 clock_enable(CCGR_UART2, 1);
 325                 return;
 326         case 2:
 327                 clock_enable(CCGR_UART3, 0);
 328                 clock_set_target_val(UART3_CLK_ROOT, CLK_ROOT_ON |
 329                                      CLK_ROOT_SOURCE_SEL(0));
 330                 clock_enable(CCGR_UART3, 1);
 331                 return;
 332         case 3:
 333                 clock_enable(CCGR_UART4, 0);
 334                 clock_set_target_val(UART4_CLK_ROOT, CLK_ROOT_ON |
 335                                      CLK_ROOT_SOURCE_SEL(0));
 336                 clock_enable(CCGR_UART4, 1);
 337                 return;
 338         default:
 339                 printf("Invalid uart index\n");
 340                 return;
 341         }
 342 }
 343
 344 void init_wdog_clk(void)
 345 {
 346         clock_enable(CCGR_WDOG1, 0);
 347         clock_enable(CCGR_WDOG2, 0);
 348         clock_enable(CCGR_WDOG3, 0);
 349         clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
 350                              CLK_ROOT_SOURCE_SEL(0));
 351         clock_enable(CCGR_WDOG1, 1);
 352         clock_enable(CCGR_WDOG2, 1);
 353         clock_enable(CCGR_WDOG3, 1);
 354 }
 355
 356 void init_clk_usdhc(u32 index)
 357 {
 358         /*
 359          * set usdhc clock root
 360          * sys pll1 400M
 361          */
 362         switch (index) {
 363         case 0:
 364                 clock_enable(CCGR_USDHC1, 0);
 365                 clock_set_target_val(USDHC1_CLK_ROOT, CLK_ROOT_ON |
 366                                      CLK_ROOT_SOURCE_SEL(1));
 367                 clock_enable(CCGR_USDHC1, 1);
 368                 return;
 369         case 1:
 370                 clock_enable(CCGR_USDHC2, 0);
 371                 clock_set_target_val(USDHC2_CLK_ROOT, CLK_ROOT_ON |
 372                                      CLK_ROOT_SOURCE_SEL(1));
 373                 clock_enable(CCGR_USDHC2, 1);
 374                 return;
 375         case 2:
 376                 clock_enable(CCGR_USDHC3, 0);
 377                 clock_set_target_val(USDHC3_CLK_ROOT, CLK_ROOT_ON |
 378                                      CLK_ROOT_SOURCE_SEL(1));
 379                 clock_enable(CCGR_USDHC3, 1);
 380                 return;
 381         default:
 382                 printf("Invalid usdhc index\n");
 383                 return;
 384         }
 385 }
 386
 387 void init_clk_ecspi(u32 index)
 388 {
 389         switch (index) {
 390         case 0:
 391                 clock_enable(CCGR_ECSPI1, 0);
 392                 clock_set_target_val(ECSPI1_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0));
 393                 clock_enable(CCGR_ECSPI1, 1);
 394                 return;
 395         case 1:
 396                 clock_enable(CCGR_ECSPI2, 0);
 397                 clock_set_target_val(ECSPI2_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0));
 398                 clock_enable(CCGR_ECSPI2, 1);
 399                 return;
 400         case 2:
 401                 clock_enable(CCGR_ECSPI3, 0);
 402                 clock_set_target_val(ECSPI3_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0));
 403                 clock_enable(CCGR_ECSPI3, 1);
 404                 return;
 405         default:
 406                 printf("Invalid ecspi index\n");
 407                 return;
 408         }
 409 }
 410
 411 void init_nand_clk(void)
 412 {
 413         /*
 414          * set rawnand root
 415          * sys pll1 400M
 416          */
 417         clock_enable(CCGR_RAWNAND, 0);
 418         clock_set_target_val(NAND_CLK_ROOT, CLK_ROOT_ON |
 419                 CLK_ROOT_SOURCE_SEL(3) | CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4)); /* 100M */
 420         clock_enable(CCGR_RAWNAND, 1);
 421 }
 422
 423 int clock_init(void)
 424 {
 425         u32 val_cfg0;
 426
 427         /*
 428          * The gate is not exported to clk tree, so configure them here.
 429          * According to ANAMIX SPEC
 430          * sys pll1 fixed at 800MHz
 431          * sys pll2 fixed at 1GHz
 432          * Here we only enable the outputs.
 433          */
 434         val_cfg0 = readl(&ana_pll->sys_pll1_gnrl_ctl);
 435         val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK |
 436                 INTPLL_DIV3_CLKE_MASK | INTPLL_DIV4_CLKE_MASK |
 437                 INTPLL_DIV5_CLKE_MASK | INTPLL_DIV6_CLKE_MASK |
 438                 INTPLL_DIV8_CLKE_MASK | INTPLL_DIV10_CLKE_MASK |
 439                 INTPLL_DIV20_CLKE_MASK;
 440         writel(val_cfg0, &ana_pll->sys_pll1_gnrl_ctl);
 441
 442         val_cfg0 = readl(&ana_pll->sys_pll2_gnrl_ctl);
 443         val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK |
 444                 INTPLL_DIV3_CLKE_MASK | INTPLL_DIV4_CLKE_MASK |
 445                 INTPLL_DIV5_CLKE_MASK | INTPLL_DIV6_CLKE_MASK |
 446                 INTPLL_DIV8_CLKE_MASK | INTPLL_DIV10_CLKE_MASK |
 447                 INTPLL_DIV20_CLKE_MASK;
 448         writel(val_cfg0, &ana_pll->sys_pll2_gnrl_ctl);
 449
 450         /* Configure ARM at 1.2GHz */
 451         clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
 452                              CLK_ROOT_SOURCE_SEL(2));
 453
 454         intpll_configure(ANATOP_ARM_PLL, MHZ(1200));
 455
 456         /* Bypass CCM A53 ROOT, Switch to ARM PLL -> MUX-> CPU */
 457         clock_set_target_val(CORE_SEL_CFG, CLK_ROOT_SOURCE_SEL(1));
 458
 459         if (is_imx8mn() || is_imx8mp())
 460                 intpll_configure(ANATOP_SYSTEM_PLL3, MHZ(600));
 461         else
 462                 intpll_configure(ANATOP_SYSTEM_PLL3, MHZ(750));
 463
 464 #ifdef CONFIG_IMX8MP
 465         /* 8MP ROM already set NOC to 800Mhz, only need to configure NOC_IO clk to 600Mhz */
 466         /* 8MP ROM already set GIC to 400Mhz, system_pll1_800m with div = 2 */
 467         clock_set_target_val(NOC_IO_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(2));
 468 #else
 469         clock_set_target_val(NOC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(2));
 470
 471         /* config GIC to sys_pll2_100m */
 472         clock_enable(CCGR_GIC, 0);
 473         clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON |
 474                              CLK_ROOT_SOURCE_SEL(3));
 475         clock_enable(CCGR_GIC, 1);
 476 #endif
 477
 478         clock_set_target_val(NAND_USDHC_BUS_CLK_ROOT, CLK_ROOT_ON |
 479                              CLK_ROOT_SOURCE_SEL(1));
 480
 481         clock_enable(CCGR_DDR1, 0);
 482         clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON |
 483                              CLK_ROOT_SOURCE_SEL(1));
 484         clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
 485                              CLK_ROOT_SOURCE_SEL(1));
 486         clock_enable(CCGR_DDR1, 1);
 487
 488         init_wdog_clk();
 489
 490         clock_enable(CCGR_TEMP_SENSOR, 1);
 491
 492         clock_enable(CCGR_SEC_DEBUG, 1);
 493
 494         return 0;
 495 };
 496
 497 u32 imx_get_uartclk(void)
 498 {
 499         return 24000000U;
 500 }
 501
 502 static u32 decode_intpll(enum clk_root_src intpll)
 503 {
 504         u32 pll_gnrl_ctl, pll_div_ctl, pll_clke_mask;
 505         u32 main_div, pre_div, post_div, div;
 506         u64 freq;
 507
 508         switch (intpll) {
 509         case ARM_PLL_CLK:
 510                 pll_gnrl_ctl = readl(&ana_pll->arm_pll_gnrl_ctl);
 511                 pll_div_ctl = readl(&ana_pll->arm_pll_div_ctl);
 512                 break;
 513         case GPU_PLL_CLK:
 514                 pll_gnrl_ctl = readl(&ana_pll->gpu_pll_gnrl_ctl);
 515                 pll_div_ctl = readl(&ana_pll->gpu_pll_div_ctl);
 516                 break;
 517         case VPU_PLL_CLK:
 518                 pll_gnrl_ctl = readl(&ana_pll->vpu_pll_gnrl_ctl);
 519                 pll_div_ctl = readl(&ana_pll->vpu_pll_div_ctl);
 520                 break;
 521         case SYSTEM_PLL1_800M_CLK:
 522         case SYSTEM_PLL1_400M_CLK:
 523         case SYSTEM_PLL1_266M_CLK:
 524         case SYSTEM_PLL1_200M_CLK:
 525         case SYSTEM_PLL1_160M_CLK:
 526         case SYSTEM_PLL1_133M_CLK:
 527         case SYSTEM_PLL1_100M_CLK:
 528         case SYSTEM_PLL1_80M_CLK:
 529         case SYSTEM_PLL1_40M_CLK:
 530                 pll_gnrl_ctl = readl(&ana_pll->sys_pll1_gnrl_ctl);
 531                 pll_div_ctl = readl(&ana_pll->sys_pll1_div_ctl);
 532                 break;
 533         case SYSTEM_PLL2_1000M_CLK:
 534         case SYSTEM_PLL2_500M_CLK:
 535         case SYSTEM_PLL2_333M_CLK:
 536         case SYSTEM_PLL2_250M_CLK:
 537         case SYSTEM_PLL2_200M_CLK:
 538         case SYSTEM_PLL2_166M_CLK:
 539         case SYSTEM_PLL2_125M_CLK:
 540         case SYSTEM_PLL2_100M_CLK:
 541         case SYSTEM_PLL2_50M_CLK:
 542                 pll_gnrl_ctl = readl(&ana_pll->sys_pll2_gnrl_ctl);
 543                 pll_div_ctl = readl(&ana_pll->sys_pll2_div_ctl);
 544                 break;
 545         case SYSTEM_PLL3_CLK:
 546                 pll_gnrl_ctl = readl(&ana_pll->sys_pll3_gnrl_ctl);
 547                 pll_div_ctl = readl(&ana_pll->sys_pll3_div_ctl);
 548                 break;
 549         default:
 550                 return -EINVAL;
 551         }
 552
 553         /* Only support SYS_XTAL 24M, PAD_CLK not take into consideration */
 554         if ((pll_gnrl_ctl & INTPLL_REF_CLK_SEL_MASK) != 0)
 555                 return 0;
 556
 557         if ((pll_gnrl_ctl & INTPLL_RST_MASK) == 0)
 558                 return 0;
 559
 560         /*
 561          * When BYPASS is equal to 1, PLL enters the bypass mode
 562          * regardless of the values of RESETB
 563          */
 564         if (pll_gnrl_ctl & INTPLL_BYPASS_MASK)
 565                 return 24000000u;
 566
 567         if (!(pll_gnrl_ctl & INTPLL_LOCK_MASK)) {
 568                 puts("pll not locked\n");
 569                 return 0;
 570         }
 571
 572         switch (intpll) {
 573         case ARM_PLL_CLK:
 574         case GPU_PLL_CLK:
 575         case VPU_PLL_CLK:
 576         case SYSTEM_PLL3_CLK:
 577         case SYSTEM_PLL1_800M_CLK:
 578         case SYSTEM_PLL2_1000M_CLK:
 579                 pll_clke_mask = INTPLL_CLKE_MASK;
 580                 div = 1;
 581                 break;
 582
 583         case SYSTEM_PLL1_400M_CLK:
 584         case SYSTEM_PLL2_500M_CLK:
 585                 pll_clke_mask = INTPLL_DIV2_CLKE_MASK;
 586                 div = 2;
 587                 break;
 588
 589         case SYSTEM_PLL1_266M_CLK:
 590         case SYSTEM_PLL2_333M_CLK:
 591                 pll_clke_mask = INTPLL_DIV3_CLKE_MASK;
 592                 div = 3;
 593                 break;
 594
 595         case SYSTEM_PLL1_200M_CLK:
 596         case SYSTEM_PLL2_250M_CLK:
 597                 pll_clke_mask = INTPLL_DIV4_CLKE_MASK;
 598                 div = 4;
 599                 break;
 600
 601         case SYSTEM_PLL1_160M_CLK:
 602         case SYSTEM_PLL2_200M_CLK:
 603                 pll_clke_mask = INTPLL_DIV5_CLKE_MASK;
 604                 div = 5;
 605                 break;
 606
 607         case SYSTEM_PLL1_133M_CLK:
 608         case SYSTEM_PLL2_166M_CLK:
 609                 pll_clke_mask = INTPLL_DIV6_CLKE_MASK;
 610                 div = 6;
 611                 break;
 612
 613         case SYSTEM_PLL1_100M_CLK:
 614         case SYSTEM_PLL2_125M_CLK:
 615                 pll_clke_mask = INTPLL_DIV8_CLKE_MASK;
 616                 div = 8;
 617                 break;
 618
 619         case SYSTEM_PLL1_80M_CLK:
 620         case SYSTEM_PLL2_100M_CLK:
 621                 pll_clke_mask = INTPLL_DIV10_CLKE_MASK;
 622                 div = 10;
 623                 break;
 624
 625         case SYSTEM_PLL1_40M_CLK:
 626         case SYSTEM_PLL2_50M_CLK:
 627                 pll_clke_mask = INTPLL_DIV20_CLKE_MASK;
 628                 div = 20;
 629                 break;
 630         default:
 631                 return -EINVAL;
 632         }
 633
 634         if ((pll_gnrl_ctl & pll_clke_mask) == 0)
 635                 return 0;
 636
 637         main_div = (pll_div_ctl & INTPLL_MAIN_DIV_MASK) >>
 638                 INTPLL_MAIN_DIV_SHIFT;
 639         pre_div = (pll_div_ctl & INTPLL_PRE_DIV_MASK) >>
 640                 INTPLL_PRE_DIV_SHIFT;
 641         post_div = (pll_div_ctl & INTPLL_POST_DIV_MASK) >>
 642                 INTPLL_POST_DIV_SHIFT;
 643
 644         /* FFVCO = (m * FFIN) / p, FFOUT = (m * FFIN) / (p * 2^s) */
 645         freq = 24000000ULL * main_div;
 646         return lldiv(freq, pre_div * (1 << post_div) * div);
 647 }
 648
 649 static u32 decode_fracpll(enum clk_root_src frac_pll)
 650 {
 651         u32 pll_gnrl_ctl, pll_fdiv_ctl0, pll_fdiv_ctl1;
 652         u32 main_div, pre_div, post_div, k;
 653
 654         switch (frac_pll) {
 655         case DRAM_PLL1_CLK:
 656                 pll_gnrl_ctl = readl(&ana_pll->dram_pll_gnrl_ctl);
 657                 pll_fdiv_ctl0 = readl(&ana_pll->dram_pll_fdiv_ctl0);
 658                 pll_fdiv_ctl1 = readl(&ana_pll->dram_pll_fdiv_ctl1);
 659                 break;
 660         case AUDIO_PLL1_CLK:
 661                 pll_gnrl_ctl = readl(&ana_pll->audio_pll1_gnrl_ctl);
 662                 pll_fdiv_ctl0 = readl(&ana_pll->audio_pll1_fdiv_ctl0);
 663                 pll_fdiv_ctl1 = readl(&ana_pll->audio_pll1_fdiv_ctl1);
 664                 break;
 665         case AUDIO_PLL2_CLK:
 666                 pll_gnrl_ctl = readl(&ana_pll->audio_pll2_gnrl_ctl);
 667                 pll_fdiv_ctl0 = readl(&ana_pll->audio_pll2_fdiv_ctl0);
 668                 pll_fdiv_ctl1 = readl(&ana_pll->audio_pll2_fdiv_ctl1);
 669                 break;
 670         case VIDEO_PLL_CLK:
 671                 pll_gnrl_ctl = readl(&ana_pll->video_pll1_gnrl_ctl);
 672                 pll_fdiv_ctl0 = readl(&ana_pll->video_pll1_fdiv_ctl0);
 673                 pll_fdiv_ctl1 = readl(&ana_pll->video_pll1_fdiv_ctl1);
 674                 break;
 675         default:
 676                 printf("Unsupported clk_root_src %d\n", frac_pll);
 677                 return 0;
 678         }
 679
 680         /* Only support SYS_XTAL 24M, PAD_CLK not take into consideration */
 681         if ((pll_gnrl_ctl & GENMASK(1, 0)) != 0)
 682                 return 0;
 683
 684         if ((pll_gnrl_ctl & RST_MASK) == 0)
 685                 return 0;
 686         /*
 687          * When BYPASS is equal to 1, PLL enters the bypass mode
 688          * regardless of the values of RESETB
 689          */
 690         if (pll_gnrl_ctl & BYPASS_MASK)
 691                 return 24000000u;
 692
 693         if (!(pll_gnrl_ctl & LOCK_STATUS)) {
 694                 puts("pll not locked\n");
 695                 return 0;
 696         }
 697
 698         if (!(pll_gnrl_ctl & CLKE_MASK))
 699                 return 0;
 700
 701         main_div = (pll_fdiv_ctl0 & MDIV_MASK) >>
 702                 MDIV_SHIFT;
 703         pre_div = (pll_fdiv_ctl0 & PDIV_MASK) >>
 704                 PDIV_SHIFT;
 705         post_div = (pll_fdiv_ctl0 & SDIV_MASK) >>
 706                 SDIV_SHIFT;
 707
 708         k = pll_fdiv_ctl1 & KDIV_MASK;
 709
 710         return lldiv((main_div * 65536 + k) * 24000000ULL,
 711                      65536 * pre_div * (1 << post_div));
 712 }
 713
 714 static u32 get_root_src_clk(enum clk_root_src root_src)
 715 {
 716         switch (root_src) {
 717         case OSC_24M_CLK:
 718                 return 24000000u;
 719         case OSC_HDMI_CLK:
 720                 return 26000000u;
 721         case OSC_32K_CLK:
 722                 return 32000u;
 723         case ARM_PLL_CLK:
 724         case GPU_PLL_CLK:
 725         case VPU_PLL_CLK:
 726         case SYSTEM_PLL1_800M_CLK:
 727         case SYSTEM_PLL1_400M_CLK:
 728         case SYSTEM_PLL1_266M_CLK:
 729         case SYSTEM_PLL1_200M_CLK:
 730         case SYSTEM_PLL1_160M_CLK:
 731         case SYSTEM_PLL1_133M_CLK:
 732         case SYSTEM_PLL1_100M_CLK:
 733         case SYSTEM_PLL1_80M_CLK:
 734         case SYSTEM_PLL1_40M_CLK:
 735         case SYSTEM_PLL2_1000M_CLK:
 736         case SYSTEM_PLL2_500M_CLK:
 737         case SYSTEM_PLL2_333M_CLK:
 738         case SYSTEM_PLL2_250M_CLK:
 739         case SYSTEM_PLL2_200M_CLK:
 740         case SYSTEM_PLL2_166M_CLK:
 741         case SYSTEM_PLL2_125M_CLK:
 742         case SYSTEM_PLL2_100M_CLK:
 743         case SYSTEM_PLL2_50M_CLK:
 744         case SYSTEM_PLL3_CLK:
 745                 return decode_intpll(root_src);
 746         case DRAM_PLL1_CLK:
 747         case AUDIO_PLL1_CLK:
 748         case AUDIO_PLL2_CLK:
 749         case VIDEO_PLL_CLK:
 750                 return decode_fracpll(root_src);
 751         case ARM_A53_ALT_CLK:
 752                 return get_root_clk(ARM_A53_CLK_ROOT);
 753         default:
 754                 return 0;
 755         }
 756
 757         return 0;
 758 }
 759
 760 static u32 get_root_clk(enum clk_root_index clock_id)
 761 {
 762         enum clk_root_src root_src;
 763         u32 post_podf, pre_podf, root_src_clk;
 764
 765         if (clock_root_enabled(clock_id) <= 0)
 766                 return 0;
 767
 768         if (clock_get_prediv(clock_id, &pre_podf) < 0)
 769                 return 0;
 770
 771         if (clock_get_postdiv(clock_id, &post_podf) < 0)
 772                 return 0;
 773
 774         if (clock_get_src(clock_id, &root_src) < 0)
 775                 return 0;
 776
 777         root_src_clk = get_root_src_clk(root_src);
 778
 779         return root_src_clk / (post_podf + 1) / (pre_podf + 1);
 780 }
 781
 782 u32 get_arm_core_clk(void)
 783 {
 784         enum clk_root_src root_src;
 785         u32 root_src_clk;
 786
 787         if (clock_get_src(CORE_SEL_CFG, &root_src) < 0)
 788                 return 0;
 789
 790         root_src_clk = get_root_src_clk(root_src);
 791
 792         return root_src_clk;
 793 }
 794
 795 u32 mxc_get_clock(enum mxc_clock clk)
 796 {
 797         u32 val;
 798
 799         switch (clk) {
 800         case MXC_ARM_CLK:
 801                 return get_arm_core_clk();
 802         case MXC_IPG_CLK:
 803                 clock_get_target_val(IPG_CLK_ROOT, &val);
 804                 val = val & 0x3;
 805                 return get_root_clk(AHB_CLK_ROOT) / 2 / (val + 1);
 806         case MXC_CSPI_CLK:
 807                 return get_root_clk(ECSPI1_CLK_ROOT);
 808         case MXC_ESDHC_CLK:
 809                 return get_root_clk(USDHC1_CLK_ROOT);
 810         case MXC_ESDHC2_CLK:
 811                 return get_root_clk(USDHC2_CLK_ROOT);
 812         case MXC_ESDHC3_CLK:
 813                 return get_root_clk(USDHC3_CLK_ROOT);
 814         case MXC_I2C_CLK:
 815                 return get_root_clk(I2C1_CLK_ROOT);
 816         case MXC_UART_CLK:
 817                 return get_root_clk(UART1_CLK_ROOT);
 818         case MXC_QSPI_CLK:
 819                 return get_root_clk(QSPI_CLK_ROOT);
 820         default:
 821                 printf("Unsupported mxc_clock %d\n", clk);
 822                 break;
 823         }
 824
 825         return 0;
 826 }
 827
 828 #if defined(CONFIG_IMX8MP) && defined(CONFIG_DWC_ETH_QOS)
 829 static int imx8mp_eqos_interface_init(struct udevice *dev,
 830                                       phy_interface_t interface_type)
 831 {
 832         struct iomuxc_gpr_base_regs *gpr =
 833                 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
 834
 835         clrbits_le32(&gpr->gpr[1],
 836                      IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK |
 837                      IOMUXC_GPR_GPR1_GPR_ENET_QOS_RGMII_EN |
 838                      IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_TX_CLK_SEL |
 839                      IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN);
 840
 841         switch (interface_type) {
 842         case PHY_INTERFACE_MODE_MII:
 843                 setbits_le32(&gpr->gpr[1],
 844                              IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN |
 845                              IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MII);
 846                 break;
 847         case PHY_INTERFACE_MODE_RMII:
 848                 setbits_le32(&gpr->gpr[1],
 849                              IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_TX_CLK_SEL |
 850                              IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN |
 851                              IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_RMII);
 852                 break;
 853         case PHY_INTERFACE_MODE_RGMII:
 854         case PHY_INTERFACE_MODE_RGMII_ID:
 855         case PHY_INTERFACE_MODE_RGMII_RXID:
 856         case PHY_INTERFACE_MODE_RGMII_TXID:
 857                 setbits_le32(&gpr->gpr[1],
 858                              IOMUXC_GPR_GPR1_GPR_ENET_QOS_RGMII_EN |
 859                              IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN |
 860                              IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_RGMII);
 861                 break;
 862         default:
 863                 return -EINVAL;
 864         }
 865
 866         return 0;
 867 }
 868 #else
 869 static int imx8mp_eqos_interface_init(struct udevice *dev,
 870                                       phy_interface_t interface_type)
 871 {
 872         return 0;
 873 }
 874 #endif
 875
 876 #ifdef CONFIG_FEC_MXC
 877 static int imx8mp_fec_interface_init(struct udevice *dev,
 878                                      phy_interface_t interface_type,
 879                                      bool mx8mp)
 880 {
 881         /* i.MX8MP has extra RGMII_EN bit in IOMUXC GPR1 register */
 882         const u32 rgmii_en = mx8mp ? IOMUXC_GPR_GPR1_GPR_ENET1_RGMII_EN : 0;
 883         struct iomuxc_gpr_base_regs *gpr =
 884                 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
 885
 886         clrbits_le32(&gpr->gpr[1],
 887                      rgmii_en |
 888                      IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL);
 889
 890         switch (interface_type) {
 891         case PHY_INTERFACE_MODE_MII:
 892         case PHY_INTERFACE_MODE_RMII:
 893                 setbits_le32(&gpr->gpr[1], IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL);
 894                 break;
 895         case PHY_INTERFACE_MODE_RGMII:
 896         case PHY_INTERFACE_MODE_RGMII_ID:
 897         case PHY_INTERFACE_MODE_RGMII_RXID:
 898         case PHY_INTERFACE_MODE_RGMII_TXID:
 899                 setbits_le32(&gpr->gpr[1], rgmii_en);
 900                 break;
 901         default:
 902                 return -EINVAL;
 903         }
 904
 905         return 0;
 906 }
 907 #else
 908 static int imx8mp_fec_interface_init(struct udevice *dev,
 909                                      phy_interface_t interface_type,
 910                                      bool mx8mp)
 911 {
 912         return 0;
 913 }
 914 #endif
 915
 916 int board_interface_eth_init(struct udevice *dev, phy_interface_t interface_type)
 917 {
 918         if (IS_ENABLED(CONFIG_IMX8MM) &&
 919             IS_ENABLED(CONFIG_FEC_MXC) &&
 920             device_is_compatible(dev, "fsl,imx8mm-fec"))
 921                 return imx8mp_fec_interface_init(dev, interface_type, false);
 922
 923         if (IS_ENABLED(CONFIG_IMX8MN) &&
 924             IS_ENABLED(CONFIG_FEC_MXC) &&
 925             device_is_compatible(dev, "fsl,imx8mn-fec"))
 926                 return imx8mp_fec_interface_init(dev, interface_type, false);
 927
 928         if (IS_ENABLED(CONFIG_IMX8MP) &&
 929             IS_ENABLED(CONFIG_FEC_MXC) &&
 930             device_is_compatible(dev, "fsl,imx8mp-fec"))
 931                 return imx8mp_fec_interface_init(dev, interface_type, true);
 932
 933         if (IS_ENABLED(CONFIG_IMX8MP) &&
 934             IS_ENABLED(CONFIG_DWC_ETH_QOS) &&
 935             device_is_compatible(dev, "nxp,imx8mp-dwmac-eqos"))
 936                 return imx8mp_eqos_interface_init(dev, interface_type);
 937
 938         return -EINVAL;
 939 }