drivers/mmc/socfpga_dw_mmc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2013 Altera Corporation <www.altera.com>
   4  */
   5
   6 #include <common.h>
   7 #include <asm/arch/clock_manager.h>
   8 #include <asm/arch/system_manager.h>
   9 #include <clk.h>
  10 #include <dm.h>
  11 #include <dwmmc.h>
  12 #include <errno.h>
  13 #include <fdtdec.h>
  14 #include <linux/libfdt.h>
  15 #include <linux/err.h>
  16 #include <malloc.h>
  17 #include <reset.h>
  18
  19 DECLARE_GLOBAL_DATA_PTR;
  20
  21 struct socfpga_dwmci_plat {
  22         struct mmc_config cfg;
  23         struct mmc mmc;
  24 };
  25
  26 /* socfpga implmentation specific driver private data */
  27 struct dwmci_socfpga_priv_data {
  28         struct dwmci_host       host;
  29         unsigned int            drvsel;
  30         unsigned int            smplsel;
  31 };
  32
  33 static void socfpga_dwmci_reset(struct udevice *dev)
  34 {
  35         struct reset_ctl_bulk reset_bulk;
  36         int ret;
  37
  38         ret = reset_get_bulk(dev, &reset_bulk);
  39         if (ret) {
  40                 dev_warn(dev, "Can't get reset: %d\n", ret);
  41                 return;
  42         }
  43
  44         reset_deassert_bulk(&reset_bulk);
  45 }
  46
  47 static void socfpga_dwmci_clksel(struct dwmci_host *host)
  48 {
  49         struct dwmci_socfpga_priv_data *priv = host->priv;
  50         u32 sdmmc_mask = ((priv->smplsel & 0x7) << SYSMGR_SDMMC_SMPLSEL_SHIFT) |
  51                          ((priv->drvsel & 0x7) << SYSMGR_SDMMC_DRVSEL_SHIFT);
  52
  53         /* Disable SDMMC clock. */
  54         clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
  55                      CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
  56
  57         debug("%s: drvsel %d smplsel %d\n", __func__,
  58               priv->drvsel, priv->smplsel);
  59         writel(sdmmc_mask, socfpga_get_sysmgr_addr() + SYSMGR_SDMMC);
  60
  61         debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
  62                 readl(socfpga_get_sysmgr_addr() + SYSMGR_SDMMC));
  63
  64         /* Enable SDMMC clock */
  65         setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
  66                      CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
  67 }
  68
  69 static int socfpga_dwmmc_get_clk_rate(struct udevice *dev)
  70 {
  71         struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
  72         struct dwmci_host *host = &priv->host;
  73 #if CONFIG_IS_ENABLED(CLK)
  74         struct clk clk;
  75         int ret;
  76
  77         ret = clk_get_by_index(dev, 1, &clk);
  78         if (ret)
  79                 return ret;
  80
  81         host->bus_hz = clk_get_rate(&clk);
  82
  83         clk_free(&clk);
  84 #else
  85         /* Fixed clock divide by 4 which due to the SDMMC wrapper */
  86         host->bus_hz = cm_get_mmc_controller_clk_hz();
  87 #endif
  88         if (host->bus_hz == 0) {
  89                 printf("DWMMC: MMC clock is zero!");
  90                 return -EINVAL;
  91         }
  92
  93         return 0;
  94 }
  95
  96 static int socfpga_dwmmc_ofdata_to_platdata(struct udevice *dev)
  97 {
  98         struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
  99         struct dwmci_host *host = &priv->host;
 100         int fifo_depth;
 101
 102         fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
 103                                     "fifo-depth", 0);
 104         if (fifo_depth < 0) {
 105                 printf("DWMMC: Can't get FIFO depth\n");
 106                 return -EINVAL;
 107         }
 108
 109         host->name = dev->name;
 110         host->ioaddr = (void *)devfdt_get_addr(dev);
 111         host->buswidth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
 112                                         "bus-width", 4);
 113         host->clksel = socfpga_dwmci_clksel;
 114
 115         /*
 116          * TODO([email protected]): Remove the need for this hack.
 117          * We only have one dwmmc block on gen5 SoCFPGA.
 118          */
 119         host->dev_index = 0;
 120         host->fifoth_val = MSIZE(0x2) |
 121                 RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2);
 122         priv->drvsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
 123                                        "drvsel", 3);
 124         priv->smplsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
 125                                         "smplsel", 0);
 126         host->priv = priv;
 127
 128         return 0;
 129 }
 130
 131 static int socfpga_dwmmc_probe(struct udevice *dev)
 132 {
 133 #ifdef CONFIG_BLK
 134         struct socfpga_dwmci_plat *plat = dev_get_platdata(dev);
 135 #endif
 136         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 137         struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
 138         struct dwmci_host *host = &priv->host;
 139         int ret;
 140
 141         ret = socfpga_dwmmc_get_clk_rate(dev);
 142         if (ret)
 143                 return ret;
 144
 145         socfpga_dwmci_reset(dev);
 146
 147 #ifdef CONFIG_BLK
 148         dwmci_setup_cfg(&plat->cfg, host, host->bus_hz, 400000);
 149         host->mmc = &plat->mmc;
 150 #else
 151
 152         ret = add_dwmci(host, host->bus_hz, 400000);
 153         if (ret)
 154                 return ret;
 155 #endif
 156         host->mmc->priv = &priv->host;
 157         upriv->mmc = host->mmc;
 158         host->mmc->dev = dev;
 159
 160         return dwmci_probe(dev);
 161 }
 162
 163 static int socfpga_dwmmc_bind(struct udevice *dev)
 164 {
 165 #ifdef CONFIG_BLK
 166         struct socfpga_dwmci_plat *plat = dev_get_platdata(dev);
 167         int ret;
 168
 169         ret = dwmci_bind(dev, &plat->mmc, &plat->cfg);
 170         if (ret)
 171                 return ret;
 172 #endif
 173
 174         return 0;
 175 }
 176
 177 static const struct udevice_id socfpga_dwmmc_ids[] = {
 178         { .compatible = "altr,socfpga-dw-mshc" },
 179         { }
 180 };
 181
 182 U_BOOT_DRIVER(socfpga_dwmmc_drv) = {
 183         .name           = "socfpga_dwmmc",
 184         .id             = UCLASS_MMC,
 185         .of_match       = socfpga_dwmmc_ids,
 186         .ofdata_to_platdata = socfpga_dwmmc_ofdata_to_platdata,
 187         .ops            = &dm_dwmci_ops,
 188         .bind           = socfpga_dwmmc_bind,
 189         .probe          = socfpga_dwmmc_probe,
 190         .priv_auto_alloc_size = sizeof(struct dwmci_socfpga_priv_data),
 191         .platdata_auto_alloc_size = sizeof(struct socfpga_dwmci_plat),
 192 };