drivers/net/phy/aquantia.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Aquantia PHY drivers
   4  *
   5  * Copyright 2014 Freescale Semiconductor, Inc.
   6  * Copyright 2018 NXP
   7  */
   8 #include <config.h>
   9 #include <common.h>
  10 #include <dm.h>
  11 #include <phy.h>
  12 #include <u-boot/crc.h>
  13 #include <malloc.h>
  14 #include <asm/byteorder.h>
  15 #include <fs.h>
  16
  17 #define AQUNTIA_10G_CTL         0x20
  18 #define AQUNTIA_VENDOR_P1       0xc400
  19
  20 #define AQUNTIA_SPEED_LSB_MASK  0x2000
  21 #define AQUNTIA_SPEED_MSB_MASK  0x40
  22
  23 #define AQUANTIA_SYSTEM_INTERFACE_SR     0xe812
  24 #define AQUANTIA_VENDOR_PROVISIONING_REG 0xC441
  25 #define AQUANTIA_FIRMWARE_ID             0x20
  26 #define AQUANTIA_RESERVED_STATUS         0xc885
  27 #define AQUANTIA_FIRMWARE_MAJOR_MASK     0xff00
  28 #define AQUANTIA_FIRMWARE_MINOR_MASK     0xff
  29 #define AQUANTIA_FIRMWARE_BUILD_MASK     0xf0
  30
  31 #define AQUANTIA_USX_AUTONEG_CONTROL_ENA 0x0008
  32 #define AQUANTIA_SI_IN_USE_MASK          0x0078
  33 #define AQUANTIA_SI_USXGMII              0x0018
  34
  35 /* registers in MDIO_MMD_VEND1 region */
  36 #define GLOBAL_FIRMWARE_ID 0x20
  37 #define GLOBAL_FAULT 0xc850
  38 #define GLOBAL_RSTATUS_1 0xc885
  39
  40 #define GLOBAL_STANDARD_CONTROL 0x0
  41 #define SOFT_RESET BIT(15)
  42 #define LOW_POWER BIT(11)
  43
  44 #define MAILBOX_CONTROL 0x0200
  45 #define MAILBOX_EXECUTE BIT(15)
  46 #define MAILBOX_WRITE BIT(14)
  47 #define MAILBOX_RESET_CRC BIT(12)
  48 #define MAILBOX_BUSY BIT(8)
  49
  50 #define MAILBOX_CRC 0x0201
  51
  52 #define MAILBOX_ADDR_MSW 0x0202
  53 #define MAILBOX_ADDR_LSW 0x0203
  54
  55 #define MAILBOX_DATA_MSW 0x0204
  56 #define MAILBOX_DATA_LSW 0x0205
  57
  58 #define UP_CONTROL 0xc001
  59 #define UP_RESET BIT(15)
  60 #define UP_RUN_STALL_OVERRIDE BIT(6)
  61 #define UP_RUN_STALL BIT(0)
  62
  63 /* addresses of memory segments in the phy */
  64 #define DRAM_BASE_ADDR 0x3FFE0000
  65 #define IRAM_BASE_ADDR 0x40000000
  66
  67 /* firmware image format constants */
  68 #define VERSION_STRING_SIZE 0x40
  69 #define VERSION_STRING_OFFSET 0x0200
  70 #define HEADER_OFFSET 0x300
  71
  72 #pragma pack(1)
  73 struct fw_header {
  74         u8 padding[4];
  75         u8 iram_offset[3];
  76         u8 iram_size[3];
  77         u8 dram_offset[3];
  78         u8 dram_size[3];
  79 };
  80
  81 #pragma pack()
  82
  83 #if defined(CONFIG_PHY_AQUANTIA_UPLOAD_FW)
  84 static int aquantia_read_fw(u8 **fw_addr, size_t *fw_length)
  85 {
  86         loff_t length, read;
  87         int ret;
  88         void *addr = NULL;
  89
  90         *fw_addr = NULL;
  91         *fw_length = 0;
  92         debug("Loading Acquantia microcode from %s %s\n",
  93               CONFIG_PHY_AQUANTIA_FW_PART, CONFIG_PHY_AQUANTIA_FW_NAME);
  94         ret = fs_set_blk_dev("mmc", CONFIG_PHY_AQUANTIA_FW_PART, FS_TYPE_ANY);
  95         if (ret < 0)
  96                 goto cleanup;
  97
  98         ret = fs_size(CONFIG_PHY_AQUANTIA_FW_NAME, &length);
  99         if (ret < 0)
 100                 goto cleanup;
 101
 102         addr = malloc(length);
 103         if (!addr) {
 104                 ret = -ENOMEM;
 105                 goto cleanup;
 106         }
 107
 108         ret = fs_set_blk_dev("mmc", CONFIG_PHY_AQUANTIA_FW_PART, FS_TYPE_ANY);
 109         if (ret < 0)
 110                 goto cleanup;
 111
 112         ret = fs_read(CONFIG_PHY_AQUANTIA_FW_NAME, (ulong)addr, 0, length,
 113                       &read);
 114         if (ret < 0)
 115                 goto cleanup;
 116
 117         *fw_addr = addr;
 118         *fw_length = length;
 119         debug("Found Acquantia microcode.\n");
 120
 121 cleanup:
 122         if (ret < 0) {
 123                 printf("loading firmware file %s %s failed with error %d\n",
 124                        CONFIG_PHY_AQUANTIA_FW_PART,
 125                        CONFIG_PHY_AQUANTIA_FW_NAME, ret);
 126                 free(addr);
 127         }
 128         return ret;
 129 }
 130
 131 /* load data into the phy's memory */
 132 static int aquantia_load_memory(struct phy_device *phydev, u32 addr,
 133                                 const u8 *data, size_t len)
 134 {
 135         size_t pos;
 136         u16 crc = 0, up_crc;
 137
 138         phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_CONTROL, MAILBOX_RESET_CRC);
 139         phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_ADDR_MSW, addr >> 16);
 140         phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_ADDR_LSW, addr & 0xfffc);
 141
 142         for (pos = 0; pos < len; pos += min(sizeof(u32), len - pos)) {
 143                 u32 word = 0;
 144
 145                 memcpy(&word, &data[pos], min(sizeof(u32), len - pos));
 146
 147                 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_DATA_MSW,
 148                           (word >> 16));
 149                 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_DATA_LSW,
 150                           word & 0xffff);
 151
 152                 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_CONTROL,
 153                           MAILBOX_EXECUTE | MAILBOX_WRITE);
 154
 155                 /* keep a big endian CRC to match the phy processor */
 156                 word = cpu_to_be32(word);
 157                 crc = crc16_ccitt(crc, (u8 *)&word, sizeof(word));
 158         }
 159
 160         up_crc = phy_read(phydev, MDIO_MMD_VEND1, MAILBOX_CRC);
 161         if (crc != up_crc) {
 162                 printf("%s crc mismatch: calculated 0x%04hx phy 0x%04hx\n",
 163                        phydev->dev->name, crc, up_crc);
 164                 return -EINVAL;
 165         }
 166         return 0;
 167 }
 168
 169 static u32 unpack_u24(const u8 *data)
 170 {
 171         return (data[2] << 16) + (data[1] << 8) + data[0];
 172 }
 173
 174 static int aquantia_upload_firmware(struct phy_device *phydev)
 175 {
 176         int ret;
 177         u8 *addr = NULL;
 178         size_t fw_length = 0;
 179         u16 calculated_crc, read_crc;
 180         char version[VERSION_STRING_SIZE];
 181         u32 primary_offset, iram_offset, iram_size, dram_offset, dram_size;
 182         const struct fw_header *header;
 183
 184         ret = aquantia_read_fw(&addr, &fw_length);
 185         if (ret != 0)
 186                 return ret;
 187
 188         read_crc = (addr[fw_length - 2] << 8)  | addr[fw_length - 1];
 189         calculated_crc = crc16_ccitt(0, addr, fw_length - 2);
 190         if (read_crc != calculated_crc) {
 191                 printf("%s bad firmware crc: file 0x%04x calculated 0x%04x\n",
 192                        phydev->dev->name, read_crc, calculated_crc);
 193                 ret = -EINVAL;
 194                 goto done;
 195         }
 196
 197         /* Find the DRAM and IRAM sections within the firmware file. */
 198         primary_offset = ((addr[9] & 0xf) << 8 | addr[8]) << 12;
 199
 200         header = (struct fw_header *)&addr[primary_offset + HEADER_OFFSET];
 201
 202         iram_offset = primary_offset + unpack_u24(header->iram_offset);
 203         iram_size = unpack_u24(header->iram_size);
 204
 205         dram_offset = primary_offset + unpack_u24(header->dram_offset);
 206         dram_size = unpack_u24(header->dram_size);
 207
 208         debug("primary %d iram offset=%d size=%d dram offset=%d size=%d\n",
 209               primary_offset, iram_offset, iram_size, dram_offset, dram_size);
 210
 211         strlcpy(version, (char *)&addr[dram_offset + VERSION_STRING_OFFSET],
 212                 VERSION_STRING_SIZE);
 213         printf("%s loading firmare version '%s'\n", phydev->dev->name, version);
 214
 215         /* stall the microcprocessor */
 216         phy_write(phydev, MDIO_MMD_VEND1, UP_CONTROL,
 217                   UP_RUN_STALL | UP_RUN_STALL_OVERRIDE);
 218
 219         debug("loading dram 0x%08x from offset=%d size=%d\n",
 220               DRAM_BASE_ADDR, dram_offset, dram_size);
 221         ret = aquantia_load_memory(phydev, DRAM_BASE_ADDR, &addr[dram_offset],
 222                                    dram_size);
 223         if (ret != 0)
 224                 goto done;
 225
 226         debug("loading iram 0x%08x from offset=%d size=%d\n",
 227               IRAM_BASE_ADDR, iram_offset, iram_size);
 228         ret = aquantia_load_memory(phydev, IRAM_BASE_ADDR, &addr[iram_offset],
 229                                    iram_size);
 230         if (ret != 0)
 231                 goto done;
 232
 233         /* make sure soft reset and low power mode are clear */
 234         phy_write(phydev, MDIO_MMD_VEND1, GLOBAL_STANDARD_CONTROL, 0);
 235
 236         /* Release the microprocessor. UP_RESET must be held for 100 usec. */
 237         phy_write(phydev, MDIO_MMD_VEND1, UP_CONTROL,
 238                   UP_RUN_STALL | UP_RUN_STALL_OVERRIDE | UP_RESET);
 239
 240         udelay(100);
 241
 242         phy_write(phydev, MDIO_MMD_VEND1, UP_CONTROL, UP_RUN_STALL_OVERRIDE);
 243
 244         printf("%s firmare loading done.\n", phydev->dev->name);
 245 done:
 246         free(addr);
 247         return ret;
 248 }
 249 #else
 250 static int aquantia_upload_firmware(struct phy_device *phydev)
 251 {
 252         printf("ERROR %s firmware loading disabled.\n", phydev->dev->name);
 253         return -1;
 254 }
 255 #endif
 256
 257 int aquantia_config(struct phy_device *phydev)
 258 {
 259         u32 val, id, rstatus, fault;
 260         u32 reg_val1 = 0;
 261
 262         id = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_FIRMWARE_ID);
 263         rstatus = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_RSTATUS_1);
 264         fault = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_FAULT);
 265
 266         if (id != 0)
 267                 printf("%s running firmware version %X.%X.%X\n",
 268                        phydev->dev->name, (id >> 8), id & 0xff,
 269                        (rstatus >> 4) & 0xf);
 270
 271         if (fault != 0)
 272                 printf("%s fault 0x%04x detected\n", phydev->dev->name, fault);
 273
 274         if (id == 0 || fault != 0) {
 275                 int ret;
 276
 277                 ret = aquantia_upload_firmware(phydev);
 278                 if (ret != 0)
 279                         return ret;
 280         }
 281
 282         val = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR);
 283
 284         if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
 285                 /* 1000BASE-T mode */
 286                 phydev->advertising = SUPPORTED_1000baseT_Full;
 287                 phydev->supported = phydev->advertising;
 288
 289                 val = (val & ~AQUNTIA_SPEED_LSB_MASK) | AQUNTIA_SPEED_MSB_MASK;
 290                 phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val);
 291         } else if (phydev->interface == PHY_INTERFACE_MODE_XGMII) {
 292                 /* 10GBASE-T mode */
 293                 phydev->advertising = SUPPORTED_10000baseT_Full;
 294                 phydev->supported = phydev->advertising;
 295
 296                 if (!(val & AQUNTIA_SPEED_LSB_MASK) ||
 297                     !(val & AQUNTIA_SPEED_MSB_MASK))
 298                         phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR,
 299                                   AQUNTIA_SPEED_LSB_MASK |
 300                                   AQUNTIA_SPEED_MSB_MASK);
 301
 302                 val = phy_read(phydev, MDIO_MMD_PHYXS,
 303                                AQUANTIA_SYSTEM_INTERFACE_SR);
 304                 /* If SI is USXGMII then start USXGMII autoneg */
 305                 if ((val & AQUANTIA_SI_IN_USE_MASK) == AQUANTIA_SI_USXGMII) {
 306                         reg_val1 =  phy_read(phydev, MDIO_MMD_PHYXS,
 307                                              AQUANTIA_VENDOR_PROVISIONING_REG);
 308
 309                         reg_val1 |= AQUANTIA_USX_AUTONEG_CONTROL_ENA;
 310
 311                         phy_write(phydev, MDIO_MMD_PHYXS,
 312                                   AQUANTIA_VENDOR_PROVISIONING_REG,
 313                                   reg_val1);
 314                         printf("%s: system interface USXGMII\n",
 315                                phydev->dev->name);
 316                 } else {
 317                         printf("%s: system interface XFI\n",
 318                                phydev->dev->name);
 319                 }
 320
 321         } else if (phydev->interface == PHY_INTERFACE_MODE_SGMII_2500) {
 322                 /* 2.5GBASE-T mode */
 323                 phydev->advertising = SUPPORTED_1000baseT_Full;
 324                 phydev->supported = phydev->advertising;
 325
 326                 phy_write(phydev, MDIO_MMD_AN, AQUNTIA_10G_CTL, 1);
 327                 phy_write(phydev, MDIO_MMD_AN, AQUNTIA_VENDOR_P1, 0x9440);
 328         } else if (phydev->interface == PHY_INTERFACE_MODE_MII) {
 329                 /* 100BASE-TX mode */
 330                 phydev->advertising = SUPPORTED_100baseT_Full;
 331                 phydev->supported = phydev->advertising;
 332
 333                 val = (val & ~AQUNTIA_SPEED_MSB_MASK) | AQUNTIA_SPEED_LSB_MASK;
 334                 phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val);
 335         }
 336
 337         val = phy_read(phydev, MDIO_MMD_VEND1, AQUANTIA_RESERVED_STATUS);
 338         reg_val1 = phy_read(phydev, MDIO_MMD_VEND1, AQUANTIA_FIRMWARE_ID);
 339
 340         printf("%s: %s Firmware Version %x.%x.%x\n", phydev->dev->name,
 341                phydev->drv->name,
 342                (reg_val1 & AQUANTIA_FIRMWARE_MAJOR_MASK) >> 8,
 343                reg_val1 & AQUANTIA_FIRMWARE_MINOR_MASK,
 344                (val & AQUANTIA_FIRMWARE_BUILD_MASK) >> 4);
 345
 346         return 0;
 347 }
 348
 349 int aquantia_startup(struct phy_device *phydev)
 350 {
 351         u32 reg, speed;
 352         int i = 0;
 353
 354         phydev->duplex = DUPLEX_FULL;
 355
 356         /* if the AN is still in progress, wait till timeout. */
 357         phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
 358         reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
 359         if (!(reg & MDIO_AN_STAT1_COMPLETE)) {
 360                 printf("%s Waiting for PHY auto negotiation to complete",
 361                        phydev->dev->name);
 362                 do {
 363                         udelay(1000);
 364                         reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
 365                         if ((i++ % 500) == 0)
 366                                 printf(".");
 367                 } while (!(reg & MDIO_AN_STAT1_COMPLETE) &&
 368                          i < (4 * PHY_ANEG_TIMEOUT));
 369
 370                 if (i > PHY_ANEG_TIMEOUT)
 371                         printf(" TIMEOUT !\n");
 372         }
 373
 374         /* Read twice because link state is latched and a
 375          * read moves the current state into the register */
 376         phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
 377         reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
 378         if (reg < 0 || !(reg & MDIO_STAT1_LSTATUS))
 379                 phydev->link = 0;
 380         else
 381                 phydev->link = 1;
 382
 383         speed = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR);
 384         if (speed & AQUNTIA_SPEED_MSB_MASK) {
 385                 if (speed & AQUNTIA_SPEED_LSB_MASK)
 386                         phydev->speed = SPEED_10000;
 387                 else
 388                         phydev->speed = SPEED_1000;
 389         } else {
 390                 if (speed & AQUNTIA_SPEED_LSB_MASK)
 391                         phydev->speed = SPEED_100;
 392                 else
 393                         phydev->speed = SPEED_10;
 394         }
 395
 396         return 0;
 397 }
 398
 399 struct phy_driver aq1202_driver = {
 400         .name = "Aquantia AQ1202",
 401         .uid = 0x3a1b445,
 402         .mask = 0xfffffff0,
 403         .features = PHY_10G_FEATURES,
 404         .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
 405                         MDIO_MMD_PHYXS | MDIO_MMD_AN |
 406                         MDIO_MMD_VEND1),
 407         .config = &aquantia_config,
 408         .startup = &aquantia_startup,
 409         .shutdown = &gen10g_shutdown,
 410 };
 411
 412 struct phy_driver aq2104_driver = {
 413         .name = "Aquantia AQ2104",
 414         .uid = 0x3a1b460,
 415         .mask = 0xfffffff0,
 416         .features = PHY_10G_FEATURES,
 417         .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
 418                         MDIO_MMD_PHYXS | MDIO_MMD_AN |
 419                         MDIO_MMD_VEND1),
 420         .config = &aquantia_config,
 421         .startup = &aquantia_startup,
 422         .shutdown = &gen10g_shutdown,
 423 };
 424
 425 struct phy_driver aqr105_driver = {
 426         .name = "Aquantia AQR105",
 427         .uid = 0x3a1b4a2,
 428         .mask = 0xfffffff0,
 429         .features = PHY_10G_FEATURES,
 430         .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
 431                         MDIO_MMD_PHYXS | MDIO_MMD_AN |
 432                         MDIO_MMD_VEND1),
 433         .config = &aquantia_config,
 434         .startup = &aquantia_startup,
 435         .shutdown = &gen10g_shutdown,
 436 };
 437
 438 struct phy_driver aqr106_driver = {
 439         .name = "Aquantia AQR106",
 440         .uid = 0x3a1b4d0,
 441         .mask = 0xfffffff0,
 442         .features = PHY_10G_FEATURES,
 443         .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
 444                         MDIO_MMD_PHYXS | MDIO_MMD_AN |
 445                         MDIO_MMD_VEND1),
 446         .config = &aquantia_config,
 447         .startup = &aquantia_startup,
 448         .shutdown = &gen10g_shutdown,
 449 };
 450
 451 struct phy_driver aqr107_driver = {
 452         .name = "Aquantia AQR107",
 453         .uid = 0x3a1b4e0,
 454         .mask = 0xfffffff0,
 455         .features = PHY_10G_FEATURES,
 456         .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
 457                         MDIO_MMD_PHYXS | MDIO_MMD_AN |
 458                         MDIO_MMD_VEND1),
 459         .config = &aquantia_config,
 460         .startup = &aquantia_startup,
 461         .shutdown = &gen10g_shutdown,
 462 };
 463
 464 struct phy_driver aqr112_driver = {
 465         .name = "Aquantia AQR112",
 466         .uid = 0x3a1b660,
 467         .mask = 0xfffffff0,
 468         .features = PHY_10G_FEATURES,
 469         .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS |
 470                  MDIO_MMD_PHYXS | MDIO_MMD_AN |
 471                  MDIO_MMD_VEND1),
 472         .config = &aquantia_config,
 473         .startup = &aquantia_startup,
 474         .shutdown = &gen10g_shutdown,
 475 };
 476
 477 struct phy_driver aqr405_driver = {
 478         .name = "Aquantia AQR405",
 479         .uid = 0x3a1b4b2,
 480         .mask = 0xfffffff0,
 481         .features = PHY_10G_FEATURES,
 482         .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
 483                  MDIO_MMD_PHYXS | MDIO_MMD_AN |
 484                  MDIO_MMD_VEND1),
 485         .config = &aquantia_config,
 486         .startup = &aquantia_startup,
 487         .shutdown = &gen10g_shutdown,
 488 };
 489
 490 struct phy_driver aqr412_driver = {
 491         .name = "Aquantia AQR412",
 492         .uid = 0x3a1b710,
 493         .mask = 0xfffffff0,
 494         .features = PHY_10G_FEATURES,
 495         .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS |
 496                  MDIO_MMD_PHYXS | MDIO_MMD_AN |
 497                  MDIO_MMD_VEND1),
 498         .config = &aquantia_config,
 499         .startup = &aquantia_startup,
 500         .shutdown = &gen10g_shutdown,
 501 };
 502
 503 int phy_aquantia_init(void)
 504 {
 505         phy_register(&aq1202_driver);
 506         phy_register(&aq2104_driver);
 507         phy_register(&aqr105_driver);
 508         phy_register(&aqr106_driver);
 509         phy_register(&aqr107_driver);
 510         phy_register(&aqr112_driver);
 511         phy_register(&aqr405_driver);
 512         phy_register(&aqr412_driver);
 513
 514         return 0;
 515 }