drivers/phy/phy-stm32-usbphyc.c

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
   4  */
   5
   6 #define LOG_CATEGORY UCLASS_PHY
   7
   8 #include <common.h>
   9 #include <clk.h>
  10 #include <clk-uclass.h>
  11 #include <div64.h>
  12 #include <dm.h>
  13 #include <fdtdec.h>
  14 #include <generic-phy.h>
  15 #include <log.h>
  16 #include <reset.h>
  17 #include <syscon.h>
  18 #include <usb.h>
  19 #include <asm/io.h>
  20 #include <dm/device_compat.h>
  21 #include <dm/lists.h>
  22 #include <dm/of_access.h>
  23 #include <linux/bitfield.h>
  24 #include <linux/bitops.h>
  25 #include <linux/delay.h>
  26 #include <linux/printk.h>
  27 #include <power/regulator.h>
  28
  29 /* USBPHYC registers */
  30 #define STM32_USBPHYC_PLL       0x0
  31 #define STM32_USBPHYC_MISC      0x8
  32 #define STM32_USBPHYC_TUNE(X)   (0x10C + ((X) * 0x100))
  33
  34 /* STM32_USBPHYC_PLL bit fields */
  35 #define PLLNDIV                 GENMASK(6, 0)
  36 #define PLLNDIV_SHIFT           0
  37 #define PLLFRACIN               GENMASK(25, 10)
  38 #define PLLFRACIN_SHIFT         10
  39 #define PLLEN                   BIT(26)
  40 #define PLLSTRB                 BIT(27)
  41 #define PLLSTRBYP               BIT(28)
  42 #define PLLFRACCTL              BIT(29)
  43 #define PLLDITHEN0              BIT(30)
  44 #define PLLDITHEN1              BIT(31)
  45
  46 /* STM32_USBPHYC_MISC bit fields */
  47 #define SWITHOST                BIT(0)
  48
  49 /* STM32_USBPHYC_TUNE bit fields */
  50 #define INCURREN                BIT(0)
  51 #define INCURRINT               BIT(1)
  52 #define LFSCAPEN                BIT(2)
  53 #define HSDRVSLEW               BIT(3)
  54 #define HSDRVDCCUR              BIT(4)
  55 #define HSDRVDCLEV              BIT(5)
  56 #define HSDRVCURINCR            BIT(6)
  57 #define FSDRVRFADJ              BIT(7)
  58 #define HSDRVRFRED              BIT(8)
  59 #define HSDRVCHKITRM            GENMASK(12, 9)
  60 #define HSDRVCHKZTRM            GENMASK(14, 13)
  61 #define OTPCOMP                 GENMASK(19, 15)
  62 #define SQLCHCTL                GENMASK(21, 20)
  63 #define HDRXGNEQEN              BIT(22)
  64 #define HSRXOFF                 GENMASK(24, 23)
  65 #define HSFALLPREEM             BIT(25)
  66 #define SHTCCTCTLPROT           BIT(26)
  67 #define STAGSEL                 BIT(27)
  68
  69 #define MAX_PHYS                2
  70
  71 /* max 100 us for PLL lock and 100 us for PHY init */
  72 #define PLL_INIT_TIME_US        200
  73 #define PLL_PWR_DOWN_TIME_US    5
  74 #define PLL_FVCO                2880     /* in MHz */
  75 #define PLL_INFF_MIN_RATE       19200000 /* in Hz */
  76 #define PLL_INFF_MAX_RATE       38400000 /* in Hz */
  77
  78 /* USBPHYC_CLK48 */
  79 #define USBPHYC_CLK48_FREQ      48000000 /* in Hz */
  80
  81 enum boosting_vals {
  82         BOOST_1000_UA = 1000,
  83         BOOST_2000_UA = 2000,
  84 };
  85
  86 enum dc_level_vals {
  87         DC_MINUS_5_TO_7_MV,
  88         DC_PLUS_5_TO_7_MV,
  89         DC_PLUS_10_TO_14_MV,
  90         DC_MAX,
  91 };
  92
  93 enum current_trim {
  94         CUR_NOMINAL,
  95         CUR_PLUS_1_56_PCT,
  96         CUR_PLUS_3_12_PCT,
  97         CUR_PLUS_4_68_PCT,
  98         CUR_PLUS_6_24_PCT,
  99         CUR_PLUS_7_8_PCT,
 100         CUR_PLUS_9_36_PCT,
 101         CUR_PLUS_10_92_PCT,
 102         CUR_PLUS_12_48_PCT,
 103         CUR_PLUS_14_04_PCT,
 104         CUR_PLUS_15_6_PCT,
 105         CUR_PLUS_17_16_PCT,
 106         CUR_PLUS_19_01_PCT,
 107         CUR_PLUS_20_58_PCT,
 108         CUR_PLUS_22_16_PCT,
 109         CUR_PLUS_23_73_PCT,
 110         CUR_MAX,
 111 };
 112
 113 enum impedance_trim {
 114         IMP_NOMINAL,
 115         IMP_MINUS_2_OHMS,
 116         IMP_MINUS_4_OMHS,
 117         IMP_MINUS_6_OHMS,
 118         IMP_MAX,
 119 };
 120
 121 enum squelch_level {
 122         SQLCH_NOMINAL,
 123         SQLCH_PLUS_7_MV,
 124         SQLCH_MINUS_5_MV,
 125         SQLCH_PLUS_14_MV,
 126         SQLCH_MAX,
 127 };
 128
 129 enum rx_offset {
 130         NO_RX_OFFSET,
 131         RX_OFFSET_PLUS_5_MV,
 132         RX_OFFSET_PLUS_10_MV,
 133         RX_OFFSET_MINUS_5_MV,
 134         RX_OFFSET_MAX,
 135 };
 136
 137 struct pll_params {
 138         u8 ndiv;
 139         u16 frac;
 140 };
 141
 142 struct stm32_usbphyc {
 143         fdt_addr_t base;
 144         struct clk clk;
 145         struct udevice *vdda1v1;
 146         struct udevice *vdda1v8;
 147         struct stm32_usbphyc_phy {
 148                 struct udevice *vdd;
 149                 struct udevice *vbus;
 150                 bool init;
 151                 bool powered;
 152         } phys[MAX_PHYS];
 153         int n_pll_cons;
 154 };
 155
 156 static void stm32_usbphyc_get_pll_params(u32 clk_rate,
 157                                          struct pll_params *pll_params)
 158 {
 159         unsigned long long fvco, ndiv, frac;
 160
 161         /*
 162          *    | FVCO = INFF*2*(NDIV + FRACT/2^16 ) when DITHER_DISABLE[1] = 1
 163          *    | FVCO = 2880MHz
 164          *    | NDIV = integer part of input bits to set the LDF
 165          *    | FRACT = fractional part of input bits to set the LDF
 166          *  =>  PLLNDIV = integer part of (FVCO / (INFF*2))
 167          *  =>  PLLFRACIN = fractional part of(FVCO / INFF*2) * 2^16
 168          * <=>  PLLFRACIN = ((FVCO / (INFF*2)) - PLLNDIV) * 2^16
 169          */
 170         fvco = (unsigned long long)PLL_FVCO * 1000000; /* In Hz */
 171
 172         ndiv = fvco;
 173         do_div(ndiv, (clk_rate * 2));
 174         pll_params->ndiv = (u8)ndiv;
 175
 176         frac = fvco * (1 << 16);
 177         do_div(frac, (clk_rate * 2));
 178         frac = frac - (ndiv * (1 << 16));
 179         pll_params->frac = (u16)frac;
 180 }
 181
 182 static int stm32_usbphyc_pll_init(struct stm32_usbphyc *usbphyc)
 183 {
 184         struct pll_params pll_params;
 185         u32 clk_rate = clk_get_rate(&usbphyc->clk);
 186         u32 usbphyc_pll;
 187
 188         if ((clk_rate < PLL_INFF_MIN_RATE) || (clk_rate > PLL_INFF_MAX_RATE)) {
 189                 log_debug("input clk freq (%dHz) out of range\n",
 190                           clk_rate);
 191                 return -EINVAL;
 192         }
 193
 194         stm32_usbphyc_get_pll_params(clk_rate, &pll_params);
 195
 196         usbphyc_pll = PLLDITHEN1 | PLLDITHEN0 | PLLSTRBYP;
 197         usbphyc_pll |= ((pll_params.ndiv << PLLNDIV_SHIFT) & PLLNDIV);
 198
 199         if (pll_params.frac) {
 200                 usbphyc_pll |= PLLFRACCTL;
 201                 usbphyc_pll |= ((pll_params.frac << PLLFRACIN_SHIFT)
 202                                  & PLLFRACIN);
 203         }
 204
 205         writel(usbphyc_pll, usbphyc->base + STM32_USBPHYC_PLL);
 206
 207         log_debug("input clk freq=%dHz, ndiv=%d, frac=%d\n",
 208                   clk_rate, pll_params.ndiv, pll_params.frac);
 209
 210         return 0;
 211 }
 212
 213 static bool stm32_usbphyc_is_powered(struct stm32_usbphyc *usbphyc)
 214 {
 215         int i;
 216
 217         for (i = 0; i < MAX_PHYS; i++) {
 218                 if (usbphyc->phys[i].powered)
 219                         return true;
 220         }
 221
 222         return false;
 223 }
 224
 225 static int stm32_usbphyc_pll_enable(struct stm32_usbphyc *usbphyc)
 226 {
 227         bool pllen = readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN ?
 228                      true : false;
 229         int ret;
 230
 231         /* Check if one consumer has already configured the pll */
 232         if (pllen && usbphyc->n_pll_cons) {
 233                 usbphyc->n_pll_cons++;
 234                 return 0;
 235         }
 236
 237         if (usbphyc->vdda1v1) {
 238                 ret = regulator_set_enable(usbphyc->vdda1v1, true);
 239                 if (ret)
 240                         return ret;
 241         }
 242
 243         if (usbphyc->vdda1v8) {
 244                 ret = regulator_set_enable(usbphyc->vdda1v8, true);
 245                 if (ret)
 246                         return ret;
 247         }
 248
 249         if (pllen) {
 250                 clrbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
 251                 udelay(PLL_PWR_DOWN_TIME_US);
 252         }
 253
 254         ret = stm32_usbphyc_pll_init(usbphyc);
 255         if (ret)
 256                 return ret;
 257
 258         setbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
 259
 260         /* We must wait PLL_INIT_TIME_US before using PHY */
 261         udelay(PLL_INIT_TIME_US);
 262
 263         if (!(readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN))
 264                 return -EIO;
 265
 266         usbphyc->n_pll_cons++;
 267
 268         return 0;
 269 }
 270
 271 static int stm32_usbphyc_pll_disable(struct stm32_usbphyc *usbphyc)
 272 {
 273         int ret;
 274
 275         usbphyc->n_pll_cons--;
 276
 277         /* Check if other consumer requires pllen */
 278         if (usbphyc->n_pll_cons)
 279                 return 0;
 280
 281         clrbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
 282
 283         /*
 284          * We must wait PLL_PWR_DOWN_TIME_US before checking that PLLEN
 285          * bit is still clear
 286          */
 287         udelay(PLL_PWR_DOWN_TIME_US);
 288
 289         if (readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN)
 290                 return -EIO;
 291
 292         if (usbphyc->vdda1v1) {
 293                 ret = regulator_set_enable(usbphyc->vdda1v1, false);
 294                 if (ret)
 295                         return ret;
 296         }
 297
 298         if (usbphyc->vdda1v8) {
 299                 ret = regulator_set_enable(usbphyc->vdda1v8, false);
 300                 if (ret)
 301                         return ret;
 302         }
 303
 304         return 0;
 305 }
 306
 307 static int stm32_usbphyc_phy_init(struct phy *phy)
 308 {
 309         struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
 310         struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
 311         int ret;
 312
 313         dev_dbg(phy->dev, "phy ID = %lu\n", phy->id);
 314         if (usbphyc_phy->init)
 315                 return 0;
 316
 317         ret = stm32_usbphyc_pll_enable(usbphyc);
 318         if (ret)
 319                 return log_ret(ret);
 320
 321         usbphyc_phy->init = true;
 322
 323         return 0;
 324 }
 325
 326 static int stm32_usbphyc_phy_exit(struct phy *phy)
 327 {
 328         struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
 329         struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
 330         int ret;
 331
 332         dev_dbg(phy->dev, "phy ID = %lu\n", phy->id);
 333         if (!usbphyc_phy->init)
 334                 return 0;
 335
 336         ret = stm32_usbphyc_pll_disable(usbphyc);
 337
 338         usbphyc_phy->init = false;
 339
 340         return log_ret(ret);
 341 }
 342
 343 static int stm32_usbphyc_phy_power_on(struct phy *phy)
 344 {
 345         struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
 346         struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
 347         int ret;
 348
 349         dev_dbg(phy->dev, "phy ID = %lu\n", phy->id);
 350         if (usbphyc_phy->vdd) {
 351                 ret = regulator_set_enable(usbphyc_phy->vdd, true);
 352                 if (ret)
 353                         return ret;
 354         }
 355         if (usbphyc_phy->vbus) {
 356                 ret = regulator_set_enable(usbphyc_phy->vbus, true);
 357                 if (ret)
 358                         return ret;
 359         }
 360
 361         usbphyc_phy->powered = true;
 362
 363         return 0;
 364 }
 365
 366 static int stm32_usbphyc_phy_power_off(struct phy *phy)
 367 {
 368         struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
 369         struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
 370         int ret;
 371
 372         dev_dbg(phy->dev, "phy ID = %lu\n", phy->id);
 373         usbphyc_phy->powered = false;
 374
 375         if (stm32_usbphyc_is_powered(usbphyc))
 376                 return 0;
 377
 378         if (usbphyc_phy->vbus) {
 379                 ret = regulator_set_enable_if_allowed(usbphyc_phy->vbus, false);
 380                 if (ret)
 381                         return ret;
 382         }
 383         if (usbphyc_phy->vdd) {
 384                 ret = regulator_set_enable_if_allowed(usbphyc_phy->vdd, false);
 385                 if (ret)
 386                         return ret;
 387         }
 388
 389         return 0;
 390 }
 391
 392 static int stm32_usbphyc_get_regulator(ofnode node,
 393                                        char *supply_name,
 394                                        struct udevice **regulator)
 395 {
 396         struct ofnode_phandle_args regulator_phandle;
 397         int ret;
 398
 399         ret = ofnode_parse_phandle_with_args(node, supply_name,
 400                                              NULL, 0, 0,
 401                                              &regulator_phandle);
 402         if (ret)
 403                 return ret;
 404
 405         ret = uclass_get_device_by_ofnode(UCLASS_REGULATOR,
 406                                           regulator_phandle.node,
 407                                           regulator);
 408         if (ret)
 409                 return ret;
 410
 411         return 0;
 412 }
 413
 414 static int stm32_usbphyc_of_xlate(struct phy *phy,
 415                                   struct ofnode_phandle_args *args)
 416 {
 417         if (args->args_count < 1)
 418                 return -ENODEV;
 419
 420         if (args->args[0] >= MAX_PHYS)
 421                 return -ENODEV;
 422
 423         phy->id = args->args[0];
 424
 425         if ((phy->id == 0 && args->args_count != 1) ||
 426             (phy->id == 1 && args->args_count != 2)) {
 427                 dev_err(phy->dev, "invalid number of cells for phy port%ld\n",
 428                         phy->id);
 429                 return -EINVAL;
 430         }
 431
 432         return 0;
 433 }
 434
 435 static void stm32_usbphyc_tuning(struct udevice *dev, ofnode node, u32 index)
 436 {
 437         struct stm32_usbphyc *usbphyc = dev_get_priv(dev);
 438         u32 reg = STM32_USBPHYC_TUNE(index);
 439         u32 otpcomp, val, tune = 0;
 440         int ret;
 441
 442         /* Backup OTP compensation code */
 443         otpcomp = FIELD_GET(OTPCOMP, readl(usbphyc->base + reg));
 444
 445         ret = ofnode_read_u32(node, "st,current-boost-microamp", &val);
 446         if (!ret && (val == BOOST_1000_UA || val == BOOST_2000_UA)) {
 447                 val = (val == BOOST_2000_UA) ? 1 : 0;
 448                 tune |= INCURREN | FIELD_PREP(INCURRINT, val);
 449         } else if (ret != -EINVAL) {
 450                 dev_warn(dev, "phy%d: invalid st,current-boost-microamp value\n", index);
 451         }
 452
 453         if (!ofnode_read_bool(node, "st,no-lsfs-fb-cap"))
 454                 tune |= LFSCAPEN;
 455
 456         if (ofnode_read_bool(node, "st,decrease-hs-slew-rate"))
 457                 tune |= HSDRVSLEW;
 458
 459         ret = ofnode_read_u32(node, "st,tune-hs-dc-level", &val);
 460         if (!ret && val < DC_MAX) {
 461                 if (val == DC_MINUS_5_TO_7_MV) {
 462                         tune |= HSDRVDCCUR;
 463                 } else {
 464                         val = (val == DC_PLUS_10_TO_14_MV) ? 1 : 0;
 465                         tune |= HSDRVCURINCR | FIELD_PREP(HSDRVDCLEV, val);
 466                 }
 467         } else if (ret != -EINVAL) {
 468                 dev_warn(dev, "phy%d: invalid st,tune-hs-dc-level value\n", index);
 469         }
 470
 471         if (ofnode_read_bool(node, "st,enable-fs-rftime-tuning"))
 472                 tune |= FSDRVRFADJ;
 473
 474         if (ofnode_read_bool(node, "st,enable-hs-rftime-reduction"))
 475                 tune |= HSDRVRFRED;
 476
 477         ret = ofnode_read_u32(node, "st,trim-hs-current", &val);
 478         if (!ret && val < CUR_MAX)
 479                 tune |= FIELD_PREP(HSDRVCHKITRM, val);
 480         else if (ret != -EINVAL)
 481                 dev_warn(dev, "phy%d: invalid st,trim-hs-current value\n", index);
 482
 483         ret = ofnode_read_u32(node, "st,trim-hs-impedance", &val);
 484         if (!ret && val < IMP_MAX)
 485                 tune |= FIELD_PREP(HSDRVCHKZTRM, val);
 486         else if (ret != -EINVAL)
 487                 dev_warn(dev, "phy%d: invalid trim-hs-impedance value\n", index);
 488
 489         ret = ofnode_read_u32(node, "st,tune-squelch-level", &val);
 490         if (!ret && val < SQLCH_MAX)
 491                 tune |= FIELD_PREP(SQLCHCTL, val);
 492         else if (ret != -EINVAL)
 493                 dev_warn(dev, "phy%d: invalid st,tune-squelch-level value\n", index);
 494
 495         if (ofnode_read_bool(node, "st,enable-hs-rx-gain-eq"))
 496                 tune |= HDRXGNEQEN;
 497
 498         ret = ofnode_read_u32(node, "st,tune-hs-rx-offset", &val);
 499         if (!ret && val < RX_OFFSET_MAX)
 500                 tune |= FIELD_PREP(HSRXOFF, val);
 501         else if (ret != -EINVAL)
 502                 dev_warn(dev, "phy%d: invalid st,tune-hs-rx-offset value\n", index);
 503
 504         if (ofnode_read_bool(node, "st,no-hs-ftime-ctrl"))
 505                 tune |= HSFALLPREEM;
 506
 507         if (!ofnode_read_bool(node, "st,no-lsfs-sc"))
 508                 tune |= SHTCCTCTLPROT;
 509
 510         if (ofnode_read_bool(node, "st,enable-hs-tx-staggering"))
 511                 tune |= STAGSEL;
 512
 513         /* Restore OTP compensation code */
 514         tune |= FIELD_PREP(OTPCOMP, otpcomp);
 515
 516         writel(tune, usbphyc->base + reg);
 517 }
 518
 519 static const struct phy_ops stm32_usbphyc_phy_ops = {
 520         .init = stm32_usbphyc_phy_init,
 521         .exit = stm32_usbphyc_phy_exit,
 522         .power_on = stm32_usbphyc_phy_power_on,
 523         .power_off = stm32_usbphyc_phy_power_off,
 524         .of_xlate = stm32_usbphyc_of_xlate,
 525 };
 526
 527 static int stm32_usbphyc_bind(struct udevice *dev)
 528 {
 529         int ret;
 530
 531         ret = device_bind_driver_to_node(dev, "stm32-usbphyc-clk", "ck_usbo_48m",
 532                                          dev_ofnode(dev), NULL);
 533
 534         return log_ret(ret);
 535 }
 536
 537 static int stm32_usbphyc_probe(struct udevice *dev)
 538 {
 539         struct stm32_usbphyc *usbphyc = dev_get_priv(dev);
 540         struct reset_ctl reset;
 541         ofnode node, connector;
 542         int ret;
 543
 544         usbphyc->base = dev_read_addr(dev);
 545         if (usbphyc->base == FDT_ADDR_T_NONE)
 546                 return -EINVAL;
 547
 548         /* Enable clock */
 549         ret = clk_get_by_index(dev, 0, &usbphyc->clk);
 550         if (ret)
 551                 return ret;
 552
 553         ret = clk_enable(&usbphyc->clk);
 554         if (ret)
 555                 return ret;
 556
 557         /* Reset */
 558         ret = reset_get_by_index(dev, 0, &reset);
 559         if (!ret) {
 560                 reset_assert(&reset);
 561                 udelay(2);
 562                 reset_deassert(&reset);
 563         }
 564
 565         /* get usbphyc regulator */
 566         ret = device_get_supply_regulator(dev, "vdda1v1-supply",
 567                                           &usbphyc->vdda1v1);
 568         if (ret) {
 569                 dev_err(dev, "Can't get vdda1v1-supply regulator\n");
 570                 return ret;
 571         }
 572
 573         ret = device_get_supply_regulator(dev, "vdda1v8-supply",
 574                                           &usbphyc->vdda1v8);
 575         if (ret) {
 576                 dev_err(dev, "Can't get vdda1v8-supply regulator\n");
 577                 return ret;
 578         }
 579
 580         /* parse all PHY subnodes to populate regulator associated to each PHY port */
 581         dev_for_each_subnode(node, dev) {
 582                 fdt_addr_t phy_id;
 583                 struct stm32_usbphyc_phy *usbphyc_phy;
 584
 585                 phy_id = ofnode_read_u32_default(node, "reg", FDT_ADDR_T_NONE);
 586                 if (phy_id >= MAX_PHYS) {
 587                         dev_err(dev, "invalid reg value %llx for %s\n",
 588                                 (fdt64_t)phy_id, ofnode_get_name(node));
 589                         return -ENOENT;
 590                 }
 591
 592                 /* Configure phy tuning */
 593                 stm32_usbphyc_tuning(dev, node, phy_id);
 594
 595                 usbphyc_phy = usbphyc->phys + phy_id;
 596                 usbphyc_phy->init = false;
 597                 usbphyc_phy->powered = false;
 598                 ret = stm32_usbphyc_get_regulator(node, "phy-supply",
 599                                                   &usbphyc_phy->vdd);
 600                 if (ret) {
 601                         dev_err(dev, "Can't get phy-supply regulator\n");
 602                         return ret;
 603                 }
 604
 605                 usbphyc_phy->vbus = NULL;
 606                 connector = ofnode_find_subnode(node, "connector");
 607                 if (ofnode_valid(connector)) {
 608                         ret = stm32_usbphyc_get_regulator(connector, "vbus-supply",
 609                                                           &usbphyc_phy->vbus);
 610                 }
 611         }
 612
 613         /* Check if second port has to be used for host controller */
 614         if (dev_read_bool(dev, "st,port2-switch-to-host"))
 615                 setbits_le32(usbphyc->base + STM32_USBPHYC_MISC, SWITHOST);
 616
 617         return 0;
 618 }
 619
 620 static const struct udevice_id stm32_usbphyc_of_match[] = {
 621         { .compatible = "st,stm32mp1-usbphyc", },
 622         { },
 623 };
 624
 625 U_BOOT_DRIVER(stm32_usb_phyc) = {
 626         .name = "stm32-usbphyc",
 627         .id = UCLASS_PHY,
 628         .of_match = stm32_usbphyc_of_match,
 629         .ops = &stm32_usbphyc_phy_ops,
 630         .bind = stm32_usbphyc_bind,
 631         .probe = stm32_usbphyc_probe,
 632         .priv_auto      = sizeof(struct stm32_usbphyc),
 633 };
 634
 635 struct stm32_usbphyc_clk {
 636         bool enable;
 637 };
 638
 639 static ulong stm32_usbphyc_clk48_get_rate(struct clk *clk)
 640 {
 641         return USBPHYC_CLK48_FREQ;
 642 }
 643
 644 static int stm32_usbphyc_clk48_enable(struct clk *clk)
 645 {
 646         struct stm32_usbphyc_clk *usbphyc_clk = dev_get_priv(clk->dev);
 647         struct stm32_usbphyc *usbphyc;
 648         int ret;
 649
 650         if (usbphyc_clk->enable)
 651                 return 0;
 652
 653         usbphyc = dev_get_priv(clk->dev->parent);
 654
 655         /* ck_usbo_48m is generated by usbphyc PLL */
 656         ret = stm32_usbphyc_pll_enable(usbphyc);
 657         if (ret)
 658                 return ret;
 659
 660         usbphyc_clk->enable = true;
 661
 662         return 0;
 663 }
 664
 665 static int stm32_usbphyc_clk48_disable(struct clk *clk)
 666 {
 667         struct stm32_usbphyc_clk *usbphyc_clk = dev_get_priv(clk->dev);
 668         struct stm32_usbphyc *usbphyc;
 669         int ret;
 670
 671         if (!usbphyc_clk->enable)
 672                 return 0;
 673
 674         usbphyc = dev_get_priv(clk->dev->parent);
 675
 676         ret = stm32_usbphyc_pll_disable(usbphyc);
 677         if (ret)
 678                 return ret;
 679
 680         usbphyc_clk->enable = false;
 681
 682         return 0;
 683 }
 684
 685 const struct clk_ops usbphyc_clk48_ops = {
 686         .get_rate = stm32_usbphyc_clk48_get_rate,
 687         .enable = stm32_usbphyc_clk48_enable,
 688         .disable = stm32_usbphyc_clk48_disable,
 689 };
 690
 691 U_BOOT_DRIVER(stm32_usb_phyc_clk) = {
 692         .name = "stm32-usbphyc-clk",
 693         .id = UCLASS_CLK,
 694         .ops = &usbphyc_clk48_ops,
 695         .priv_auto = sizeof(struct stm32_usbphyc_clk),
 696 };