arch/arm/mach-meson/board-g12a.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2016 Beniamino Galvani <[email protected]>
   4  * (C) Copyright 2018 Neil Armstrong <[email protected]>
   5  */
   6
   7 #include <common.h>
   8 #include <asm/arch/boot.h>
   9 #include <asm/arch/eth.h>
  10 #include <asm/arch/g12a.h>
  11 #include <asm/arch/mem.h>
  12 #include <asm/io.h>
  13 #include <asm/armv8/mmu.h>
  14 #include <linux/sizes.h>
  15 #include <phy.h>
  16
  17 DECLARE_GLOBAL_DATA_PTR;
  18
  19 int meson_get_boot_device(void)
  20 {
  21         return readl(G12A_AO_SEC_GP_CFG0) & G12A_AO_BOOT_DEVICE;
  22 }
  23
  24 /* Configure the reserved memory zones exported by the secure registers
  25  * into EFI and DTB reserved memory entries.
  26  */
  27 void meson_init_reserved_memory(void *fdt)
  28 {
  29         u64 bl31_size, bl31_start;
  30         u64 bl32_size, bl32_start;
  31         u32 reg;
  32
  33         /*
  34          * Get ARM Trusted Firmware reserved memory zones in :
  35          * - AO_SEC_GP_CFG3: bl32 & bl31 size in KiB, can be 0
  36          * - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL
  37          * - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL
  38          */
  39         reg = readl(G12A_AO_SEC_GP_CFG3);
  40
  41         bl31_size = ((reg & G12A_AO_BL31_RSVMEM_SIZE_MASK)
  42                         >> G12A_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K;
  43         bl32_size = (reg & G12A_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K;
  44
  45         bl31_start = readl(G12A_AO_SEC_GP_CFG5);
  46         bl32_start = readl(G12A_AO_SEC_GP_CFG4);
  47
  48         /* Add BL31 reserved zone */
  49         if (bl31_start && bl31_size)
  50                 meson_board_add_reserved_memory(fdt, bl31_start, bl31_size);
  51
  52         /* Add BL32 reserved zone */
  53         if (bl32_start && bl32_size)
  54                 meson_board_add_reserved_memory(fdt, bl32_start, bl32_size);
  55 }
  56
  57 phys_size_t get_effective_memsize(void)
  58 {
  59         /* Size is reported in MiB, convert it in bytes */
  60         return ((readl(G12A_AO_SEC_GP_CFG0) & G12A_AO_MEM_SIZE_MASK)
  61                         >> G12A_AO_MEM_SIZE_SHIFT) * SZ_1M;
  62 }
  63
  64 static struct mm_region g12a_mem_map[] = {
  65         {
  66                 .virt = 0x0UL,
  67                 .phys = 0x0UL,
  68                 .size = 0x80000000UL,
  69                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  70                          PTE_BLOCK_INNER_SHARE
  71         }, {
  72                 .virt = 0xf0000000UL,
  73                 .phys = 0xf0000000UL,
  74                 .size = 0x10000000UL,
  75                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  76                          PTE_BLOCK_NON_SHARE |
  77                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  78         }, {
  79                 /* List terminator */
  80                 0,
  81         }
  82 };
  83
  84 struct mm_region *mem_map = g12a_mem_map;
  85
  86 static void g12a_enable_external_mdio(void)
  87 {
  88         writel(0x0, ETH_PHY_CNTL2);
  89 }
  90
  91 static void g12a_enable_internal_mdio(void)
  92 {
  93         /* Fire up the PHY PLL */
  94         writel(0x29c0040a, ETH_PLL_CNTL0);
  95         writel(0x927e0000, ETH_PLL_CNTL1);
  96         writel(0xac5f49e5, ETH_PLL_CNTL2);
  97         writel(0x00000000, ETH_PLL_CNTL3);
  98         writel(0x00000000, ETH_PLL_CNTL4);
  99         writel(0x20200000, ETH_PLL_CNTL5);
 100         writel(0x0000c002, ETH_PLL_CNTL6);
 101         writel(0x00000023, ETH_PLL_CNTL7);
 102         writel(0x39c0040a, ETH_PLL_CNTL0);
 103         writel(0x19c0040a, ETH_PLL_CNTL0);
 104
 105         /* Select the internal MDIO */
 106         writel(0x33000180, ETH_PHY_CNTL0);
 107         writel(0x00074043, ETH_PHY_CNTL1);
 108         writel(0x00000260, ETH_PHY_CNTL2);
 109 }
 110
 111 /* Configure the Ethernet MAC with the requested interface mode
 112  * with some optional flags.
 113  */
 114 void meson_eth_init(phy_interface_t mode, unsigned int flags)
 115 {
 116         switch (mode) {
 117         case PHY_INTERFACE_MODE_RGMII:
 118         case PHY_INTERFACE_MODE_RGMII_ID:
 119         case PHY_INTERFACE_MODE_RGMII_RXID:
 120         case PHY_INTERFACE_MODE_RGMII_TXID:
 121                 /* Set RGMII mode */
 122                 setbits_le32(G12A_ETH_REG_0, G12A_ETH_REG_0_PHY_INTF_RGMII |
 123                              G12A_ETH_REG_0_TX_PHASE(1) |
 124                              G12A_ETH_REG_0_TX_RATIO(4) |
 125                              G12A_ETH_REG_0_PHY_CLK_EN |
 126                              G12A_ETH_REG_0_CLK_EN);
 127                 break;
 128
 129         case PHY_INTERFACE_MODE_RMII:
 130                 /* Set RMII mode */
 131                 out_le32(G12A_ETH_REG_0, G12A_ETH_REG_0_PHY_INTF_RMII |
 132                                         G12A_ETH_REG_0_INVERT_RMII_CLK |
 133                                         G12A_ETH_REG_0_CLK_EN);
 134
 135                 /* Use G12A RMII Internal PHY */
 136                 if (flags & MESON_USE_INTERNAL_RMII_PHY)
 137                         g12a_enable_internal_mdio();
 138                 else
 139                         g12a_enable_external_mdio();
 140
 141                 break;
 142
 143         default:
 144                 printf("Invalid Ethernet interface mode\n");
 145                 return;
 146         }
 147
 148         /* Enable power gate */
 149         clrbits_le32(G12A_MEM_PD_REG_0, G12A_MEM_PD_REG_0_ETH_MASK);
 150 }