2 * Configuation settings for the Renesas Solutions ECOVEC board
4 * Copyright (C) 2009 - 2011 Renesas Solutions Corp.
8 * SPDX-License-Identifier: GPL-2.0+
15 * Address Interface BusWidth
16 *-----------------------------------------
17 * 0x0000_0000 U-Boot 16bit
18 * 0x0004_0000 Linux romImage 16bit
19 * 0x0014_0000 MTD for Linux 16bit
20 * 0x0400_0000 Internal I/O 16/32bit
21 * 0x0800_0000 DRAM 32bit
22 * 0x1800_0000 MFI 16bit
29 #define CONFIG_CPU_SH7724 1
30 #define CONFIG_BOARD_LATE_INIT 1
31 #define CONFIG_ECOVEC 1
33 #define CONFIG_ECOVEC_ROMIMAGE_ADDR 0xA0040000
34 #define CONFIG_SYS_TEXT_BASE 0x8FFC0000
36 #define CONFIG_CMD_FLASH
37 #define CONFIG_CMD_MEMORY
38 #define CONFIG_CMD_NET
39 #define CONFIG_CMD_PING
40 #define CONFIG_CMD_MII
41 #define CONFIG_CMD_NFS
42 #define CONFIG_CMD_SDRAM
43 #define CONFIG_CMD_ENV
44 #define CONFIG_CMD_USB
45 #define CONFIG_CMD_FAT
46 #define CONFIG_CMD_EXT2
47 #define CONFIG_CMD_SAVEENV
49 #define CONFIG_USB_STORAGE
50 #define CONFIG_DOS_PARTITION
52 #define CONFIG_BAUDRATE 115200
53 #define CONFIG_BOOTDELAY 3
54 #define CONFIG_BOOTARGS "console=ttySC0,115200"
56 #define CONFIG_VERSION_VARIABLE
57 #undef CONFIG_SHOW_BOOT_PROGRESS
60 #define CONFIG_CMD_I2C
61 #define CONFIG_SH_I2C 1
62 #define CONFIG_HARD_I2C 1
63 #define CONFIG_I2C_MULTI_BUS 1
64 #define CONFIG_SYS_MAX_I2C_BUS 2
65 #define CONFIG_SYS_I2C_MODULE 1
66 #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
67 #define CONFIG_SYS_I2C_SLAVE 0x7F
68 #define CONFIG_SH_I2C_DATA_HIGH 4
69 #define CONFIG_SH_I2C_DATA_LOW 5
70 #define CONFIG_SH_I2C_CLOCK 41666666
71 #define CONFIG_SH_I2C_BASE0 0xA4470000
72 #define CONFIG_SH_I2C_BASE1 0xA4750000
75 #define CONFIG_SH_ETHER 1
76 #define CONFIG_SH_ETHER_USE_PORT (0)
77 #define CONFIG_SH_ETHER_PHY_ADDR (0x1f)
78 #define CONFIG_PHY_SMSC 1
80 #define CONFIG_BITBANGMII
81 #define CONFIG_BITBANGMII_MULTI
82 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
85 #define CONFIG_USB_R8A66597_HCD
86 #define CONFIG_R8A66597_BASE_ADDR 0xA4D80000
87 #define CONFIG_R8A66597_XTAL 0x0000 /* 12MHz */
88 #define CONFIG_R8A66597_LDRV 0x8000 /* 3.3V */
89 #define CONFIG_R8A66597_ENDIAN 0x0000 /* little */
90 #define CONFIG_SUPERH_ON_CHIP_R8A66597
92 /* undef to save memory */
93 #define CONFIG_SYS_LONGHELP
94 /* Monitor Command Prompt */
95 #define CONFIG_SYS_PROMPT "=> "
96 /* Buffer size for input from the Console */
97 #define CONFIG_SYS_CBSIZE 256
98 /* Buffer size for Console output */
99 #define CONFIG_SYS_PBSIZE 256
100 /* max args accepted for monitor commands */
101 #define CONFIG_SYS_MAXARGS 16
102 /* Buffer size for Boot Arguments passed to kernel */
103 #define CONFIG_SYS_BARGSIZE 512
104 /* List of legal baudrate settings for this board */
105 #define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
108 #define CONFIG_SCIF_CONSOLE 1
109 #define CONFIG_SCIF 1
110 #define CONFIG_CONS_SCIF0 1
112 /* Suppress display of console information at boot */
113 #undef CONFIG_SYS_CONSOLE_INFO_QUIET
114 #undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
115 #undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
118 #define CONFIG_SYS_SDRAM_BASE (0x88000000)
119 #define CONFIG_SYS_SDRAM_SIZE (256 * 1024 * 1024)
120 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
122 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
123 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 200 * 1024 * 1024)
124 /* Enable alternate, more extensive, memory test */
125 #undef CONFIG_SYS_ALT_MEMTEST
126 /* Scratch address used by the alternate memory test */
127 #undef CONFIG_SYS_MEMTEST_SCRATCH
129 /* Enable temporary baudrate change while serial download */
130 #undef CONFIG_SYS_LOADS_BAUD_CHANGE
133 #define CONFIG_FLASH_CFI_DRIVER 1
134 #define CONFIG_SYS_FLASH_CFI
135 #undef CONFIG_SYS_FLASH_QUIET_TEST
136 #define CONFIG_SYS_FLASH_EMPTY_INFO
137 #define CONFIG_SYS_FLASH_BASE (0xA0000000)
138 #define CONFIG_SYS_MAX_FLASH_SECT 512
140 /* if you use all NOR Flash , you change dip-switch. Please see Manual. */
141 #define CONFIG_SYS_MAX_FLASH_BANKS 1
142 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
144 /* Timeout for Flash erase operations (in ms) */
145 #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
146 /* Timeout for Flash write operations (in ms) */
147 #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
148 /* Timeout for Flash set sector lock bit operations (in ms) */
149 #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
150 /* Timeout for Flash clear lock bit operations (in ms) */
151 #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
154 * Use hardware flash sectors protection instead
155 * of U-Boot software protection
157 #undef CONFIG_SYS_FLASH_PROTECTION
158 #undef CONFIG_SYS_DIRECT_FLASH_TFTP
160 /* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
161 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
163 #define CONFIG_SYS_MONITOR_LEN (256 * 1024)
164 /* Size of DRAM reserved for malloc() use */
165 #define CONFIG_SYS_MALLOC_LEN (256 * 1024)
166 /* size in bytes reserved for initial data */
167 #define CONFIG_SYS_GBL_DATA_SIZE (256)
168 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
171 #define CONFIG_ENV_IS_IN_FLASH
172 #define CONFIG_ENV_OVERWRITE 1
173 #define CONFIG_ENV_SECT_SIZE (128 * 1024)
174 #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
175 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
176 /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
177 #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
178 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
181 #define CONFIG_SYS_CLK_FREQ 41666666
182 #define CONFIG_SYS_TMU_CLK_DIV 4
183 #define CONFIG_SYS_HZ 1000
185 #endif /* __ECOVEC_H */