drivers/ata/sata_sil.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2011 Freescale Semiconductor, Inc.
   4  * Copyright 2019 NXP
   5  * Author: Tang Yuantian <[email protected]>
   6  */
   7
   8 #include <common.h>
   9 #include <cpu_func.h>
  10 #include <pci.h>
  11 #include <command.h>
  12 #include <asm/byteorder.h>
  13 #include <malloc.h>
  14 #include <asm/io.h>
  15 #include <fis.h>
  16 #include <sata.h>
  17 #include <libata.h>
  18 #include <sata.h>
  19
  20 #if CONFIG_IS_ENABLED(BLK)
  21 #include <dm.h>
  22 #include <blk.h>
  23 #include <dm/device-internal.h>
  24 #endif
  25
  26 #include "sata_sil.h"
  27
  28 #define virt_to_bus(devno, v)   pci_virt_to_mem(devno, (void *) (v))
  29
  30 /* just compatible ahci_ops */
  31 struct sil_ops {
  32         int *rev0;
  33         int *rev1;
  34         int (*scan)(struct udevice *dev);
  35 };
  36
  37 static struct sata_info sata_info;
  38
  39 static struct pci_device_id supported[] = {
  40         { PCI_DEVICE(PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3131) },
  41         { PCI_DEVICE(PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3132) },
  42         { PCI_DEVICE(PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3124) },
  43         {}
  44 };
  45
  46 static void sil_sata_dump_fis(struct sata_fis_d2h *s)
  47 {
  48         printf("Status FIS dump:\n");
  49         printf("fis_type:               %02x\n", s->fis_type);
  50         printf("pm_port_i:              %02x\n", s->pm_port_i);
  51         printf("status:                 %02x\n", s->status);
  52         printf("error:                  %02x\n", s->error);
  53         printf("lba_low:                %02x\n", s->lba_low);
  54         printf("lba_mid:                %02x\n", s->lba_mid);
  55         printf("lba_high:               %02x\n", s->lba_high);
  56         printf("device:                 %02x\n", s->device);
  57         printf("lba_low_exp:            %02x\n", s->lba_low_exp);
  58         printf("lba_mid_exp:            %02x\n", s->lba_mid_exp);
  59         printf("lba_high_exp:           %02x\n", s->lba_high_exp);
  60         printf("res1:                   %02x\n", s->res1);
  61         printf("sector_count:           %02x\n", s->sector_count);
  62         printf("sector_count_exp:       %02x\n", s->sector_count_exp);
  63 }
  64
  65 static const char *sata_spd_string(unsigned int speed)
  66 {
  67         static const char * const spd_str[] = {
  68                 "1.5 Gbps",
  69                 "3.0 Gbps",
  70                 "6.0 Gbps",
  71         };
  72
  73         if ((speed - 1) > 2)
  74                 return "<unknown>";
  75
  76         return spd_str[speed - 1];
  77 }
  78
  79 static u32 ata_wait_register(void *reg, u32 mask,
  80                          u32 val, int timeout_msec)
  81 {
  82         u32 tmp;
  83
  84         tmp = readl(reg);
  85         while ((tmp & mask) == val && timeout_msec > 0) {
  86                 mdelay(1);
  87                 timeout_msec--;
  88                 tmp = readl(reg);
  89         }
  90
  91         return tmp;
  92 }
  93
  94 static void sil_config_port(void *port)
  95 {
  96         /* configure IRQ WoC */
  97         writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
  98
  99         /* zero error counters. */
 100         writew(0x8000, port + PORT_DECODE_ERR_THRESH);
 101         writew(0x8000, port + PORT_CRC_ERR_THRESH);
 102         writew(0x8000, port + PORT_HSHK_ERR_THRESH);
 103         writew(0x0000, port + PORT_DECODE_ERR_CNT);
 104         writew(0x0000, port + PORT_CRC_ERR_CNT);
 105         writew(0x0000, port + PORT_HSHK_ERR_CNT);
 106
 107         /* always use 64bit activation */
 108         writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);
 109
 110         /* clear port multiplier enable and resume bits */
 111         writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR);
 112 }
 113
 114 static int sil_init_port(void *port)
 115 {
 116         u32 tmp;
 117
 118         writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
 119         ata_wait_register(port + PORT_CTRL_STAT,
 120                           PORT_CS_INIT, PORT_CS_INIT, 100);
 121         tmp = ata_wait_register(port + PORT_CTRL_STAT,
 122                                 PORT_CS_RDY, 0, 100);
 123
 124         if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY)
 125                 return 1;
 126
 127         return 0;
 128 }
 129
 130 static void sil_read_fis(struct sil_sata *sata, int tag,
 131                          struct sata_fis_d2h *fis)
 132 {
 133         void *port = sata->port;
 134         struct sil_prb *prb;
 135         int i;
 136         u32 *src, *dst;
 137
 138         prb = port + PORT_LRAM + tag * PORT_LRAM_SLOT_SZ;
 139         src = (u32 *)&prb->fis;
 140         dst = (u32 *)fis;
 141         for (i = 0; i < sizeof(struct sata_fis_h2d); i += 4)
 142                 *dst++ = readl(src++);
 143 }
 144
 145 static int sil_exec_cmd(struct sil_sata *sata, struct sil_cmd_block *pcmd,
 146                         int tag)
 147 {
 148         void *port = sata->port;
 149         u64 paddr = virt_to_bus(sata->devno, pcmd);
 150         u32 irq_mask, irq_stat;
 151         int rc;
 152
 153         writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR, port + PORT_IRQ_ENABLE_CLR);
 154
 155         /* better to add momery barrior here */
 156         writel((u32)paddr, port + PORT_CMD_ACTIVATE + tag * 8);
 157         writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + tag * 8 + 4);
 158
 159         irq_mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT;
 160         irq_stat = ata_wait_register(port + PORT_IRQ_STAT, irq_mask,
 161                         0, 10000);
 162
 163         /* clear IRQs */
 164         writel(irq_mask, port + PORT_IRQ_STAT);
 165         irq_stat >>= PORT_IRQ_RAW_SHIFT;
 166
 167         if (irq_stat & PORT_IRQ_COMPLETE)
 168                 rc = 0;
 169         else {
 170                 /* force port into known state */
 171                 sil_init_port(port);
 172                 if (irq_stat & PORT_IRQ_ERROR)
 173                         rc = 1; /* error */
 174                 else
 175                         rc = 2; /* busy */
 176         }
 177
 178         return rc;
 179 }
 180
 181 static int sil_cmd_set_feature(struct sil_sata *sata)
 182 {
 183         struct sil_cmd_block cmdb, *pcmd = &cmdb;
 184         struct sata_fis_d2h fis;
 185         u8 udma_cap;
 186         int ret;
 187
 188         memset((void *)&cmdb, 0, sizeof(struct sil_cmd_block));
 189         pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
 190         pcmd->prb.fis.pm_port_c = (1 << 7);
 191         pcmd->prb.fis.command = ATA_CMD_SET_FEATURES;
 192         pcmd->prb.fis.features = SETFEATURES_XFER;
 193
 194         /* First check the device capablity */
 195         udma_cap = (u8)(sata->udma & 0xff);
 196         debug("udma_cap %02x\n", udma_cap);
 197
 198         if (udma_cap == ATA_UDMA6)
 199                 pcmd->prb.fis.sector_count = XFER_UDMA_6;
 200         if (udma_cap == ATA_UDMA5)
 201                 pcmd->prb.fis.sector_count = XFER_UDMA_5;
 202         if (udma_cap == ATA_UDMA4)
 203                 pcmd->prb.fis.sector_count = XFER_UDMA_4;
 204         if (udma_cap == ATA_UDMA3)
 205                 pcmd->prb.fis.sector_count = XFER_UDMA_3;
 206
 207         ret = sil_exec_cmd(sata, pcmd, 0);
 208         if (ret) {
 209                 sil_read_fis(sata, 0, &fis);
 210                 printf("Err: exe cmd(0x%x).\n",
 211                                 readl(sata->port + PORT_SERROR));
 212                 sil_sata_dump_fis(&fis);
 213                 return 1;
 214         }
 215
 216         return 0;
 217 }
 218
 219 static void sil_sata_init_wcache(struct sil_sata *sata, u16 *id)
 220 {
 221         if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id))
 222                 sata->wcache = 1;
 223         if (ata_id_has_flush(id))
 224                 sata->flush = 1;
 225         if (ata_id_has_flush_ext(id))
 226                 sata->flush_ext = 1;
 227 }
 228
 229 static void sil_sata_set_feature_by_id(struct sil_sata *sata, u16 *id)
 230 {
 231 #ifdef CONFIG_LBA48
 232         /* Check if support LBA48 */
 233         if (ata_id_has_lba48(id)) {
 234                 sata->lba48 = 1;
 235                 debug("Device supports LBA48\n");
 236         } else {
 237                 debug("Device supports LBA28\n");
 238         }
 239 #endif
 240
 241         sil_sata_init_wcache(sata, id);
 242         sil_cmd_set_feature(sata);
 243 }
 244
 245 static int sil_cmd_identify_device(struct sil_sata *sata, u16 *id)
 246 {
 247         struct sil_cmd_block cmdb, *pcmd = &cmdb;
 248         struct sata_fis_d2h fis;
 249         int ret;
 250
 251         memset((void *)&cmdb, 0, sizeof(struct sil_cmd_block));
 252         pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_PROTOCOL);
 253         pcmd->prb.prot = cpu_to_le16(PRB_PROT_READ);
 254         pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
 255         pcmd->prb.fis.pm_port_c = (1 << 7);
 256         pcmd->prb.fis.command = ATA_CMD_ID_ATA;
 257         pcmd->sge.addr = cpu_to_le64(virt_to_bus(sata->devno, id));
 258         pcmd->sge.cnt = cpu_to_le32(sizeof(id[0]) * ATA_ID_WORDS);
 259         pcmd->sge.flags = cpu_to_le32(SGE_TRM);
 260
 261         ret = sil_exec_cmd(sata, pcmd, 0);
 262         if (ret) {
 263                 sil_read_fis(sata, 0, &fis);
 264                 printf("Err: id cmd(0x%x).\n", readl(sata->port + PORT_SERROR));
 265                 sil_sata_dump_fis(&fis);
 266                 return 1;
 267         }
 268         ata_swap_buf_le16(id, ATA_ID_WORDS);
 269
 270         return 0;
 271 }
 272
 273 static int sil_cmd_soft_reset(struct sil_sata *sata)
 274 {
 275         struct sil_cmd_block cmdb, *pcmd = &cmdb;
 276         struct sata_fis_d2h fis;
 277         void *port = sata->port;
 278         int ret;
 279
 280         /* put the port into known state */
 281         if (sil_init_port(port)) {
 282                 printf("SRST: port %d not ready\n", sata->id);
 283                 return 1;
 284         }
 285
 286         memset((void *)&cmdb, 0, sizeof(struct sil_cmd_block));
 287
 288         pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_SRST);
 289         pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
 290         pcmd->prb.fis.pm_port_c = 0xf;
 291
 292         ret = sil_exec_cmd(sata, &cmdb, 0);
 293         if (ret) {
 294                 sil_read_fis(sata, 0, &fis);
 295                 printf("SRST cmd error.\n");
 296                 sil_sata_dump_fis(&fis);
 297                 return 1;
 298         }
 299
 300         return 0;
 301 }
 302
 303 static ulong sil_sata_rw_cmd(struct sil_sata *sata, ulong start, ulong blkcnt,
 304                              u8 *buffer, int is_write)
 305 {
 306         struct sil_cmd_block cmdb, *pcmd = &cmdb;
 307         struct sata_fis_d2h fis;
 308         u64 block;
 309         int ret;
 310
 311         block = (u64)start;
 312         memset(pcmd, 0, sizeof(struct sil_cmd_block));
 313         pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_PROTOCOL);
 314         pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
 315         pcmd->prb.fis.pm_port_c = (1 << 7);
 316         if (is_write) {
 317                 pcmd->prb.fis.command = ATA_CMD_WRITE;
 318                 pcmd->prb.prot = cpu_to_le16(PRB_PROT_WRITE);
 319         } else {
 320                 pcmd->prb.fis.command = ATA_CMD_READ;
 321                 pcmd->prb.prot = cpu_to_le16(PRB_PROT_READ);
 322         }
 323
 324         pcmd->prb.fis.device = ATA_LBA;
 325         pcmd->prb.fis.device |= (block >> 24) & 0xf;
 326         pcmd->prb.fis.lba_high = (block >> 16) & 0xff;
 327         pcmd->prb.fis.lba_mid = (block >> 8) & 0xff;
 328         pcmd->prb.fis.lba_low = block & 0xff;
 329         pcmd->prb.fis.sector_count = (u8)blkcnt & 0xff;
 330
 331         pcmd->sge.addr = cpu_to_le64(virt_to_bus(sata->devno, buffer));
 332         pcmd->sge.cnt = cpu_to_le32(blkcnt * ATA_SECT_SIZE);
 333         pcmd->sge.flags = cpu_to_le32(SGE_TRM);
 334
 335         ret = sil_exec_cmd(sata, pcmd, 0);
 336         if (ret) {
 337                 sil_read_fis(sata, 0, &fis);
 338                 printf("Err: rw cmd(0x%08x).\n",
 339                                 readl(sata->port + PORT_SERROR));
 340                 sil_sata_dump_fis(&fis);
 341                 return 1;
 342         }
 343
 344         return blkcnt;
 345 }
 346
 347 static ulong sil_sata_rw_cmd_ext(struct sil_sata *sata, ulong start,
 348                                  ulong blkcnt, u8 *buffer, int is_write)
 349 {
 350         struct sil_cmd_block cmdb, *pcmd = &cmdb;
 351         struct sata_fis_d2h fis;
 352         u64 block;
 353         int ret;
 354
 355         block = (u64)start;
 356         memset(pcmd, 0, sizeof(struct sil_cmd_block));
 357         pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_PROTOCOL);
 358         pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
 359         pcmd->prb.fis.pm_port_c = (1 << 7);
 360         if (is_write) {
 361                 pcmd->prb.fis.command = ATA_CMD_WRITE_EXT;
 362                 pcmd->prb.prot = cpu_to_le16(PRB_PROT_WRITE);
 363         } else {
 364                 pcmd->prb.fis.command = ATA_CMD_READ_EXT;
 365                 pcmd->prb.prot = cpu_to_le16(PRB_PROT_READ);
 366         }
 367
 368         pcmd->prb.fis.lba_high_exp = (block >> 40) & 0xff;
 369         pcmd->prb.fis.lba_mid_exp = (block >> 32) & 0xff;
 370         pcmd->prb.fis.lba_low_exp = (block >> 24) & 0xff;
 371         pcmd->prb.fis.lba_high = (block >> 16) & 0xff;
 372         pcmd->prb.fis.lba_mid = (block >> 8) & 0xff;
 373         pcmd->prb.fis.lba_low = block & 0xff;
 374         pcmd->prb.fis.device = ATA_LBA;
 375         pcmd->prb.fis.sector_count_exp = (blkcnt >> 8) & 0xff;
 376         pcmd->prb.fis.sector_count = blkcnt & 0xff;
 377
 378         pcmd->sge.addr = cpu_to_le64(virt_to_bus(sata->devno, buffer));
 379         pcmd->sge.cnt = cpu_to_le32(blkcnt * ATA_SECT_SIZE);
 380         pcmd->sge.flags = cpu_to_le32(SGE_TRM);
 381
 382         ret = sil_exec_cmd(sata, pcmd, 0);
 383         if (ret) {
 384                 sil_read_fis(sata, 0, &fis);
 385                 printf("Err: rw ext cmd(0x%08x).\n",
 386                                 readl(sata->port + PORT_SERROR));
 387                 sil_sata_dump_fis(&fis);
 388                 return 1;
 389         }
 390
 391         return blkcnt;
 392 }
 393
 394 static ulong sil_sata_rw_lba28(struct sil_sata *sata, ulong blknr,
 395                                lbaint_t blkcnt, const void *buffer,
 396                                int is_write)
 397 {
 398         ulong start, blks, max_blks;
 399         u8 *addr;
 400
 401         start = blknr;
 402         blks = blkcnt;
 403         addr = (u8 *)buffer;
 404
 405         max_blks = ATA_MAX_SECTORS;
 406         do {
 407                 if (blks > max_blks) {
 408                         sil_sata_rw_cmd(sata, start, max_blks, addr, is_write);
 409                         start += max_blks;
 410                         blks -= max_blks;
 411                         addr += ATA_SECT_SIZE * max_blks;
 412                 } else {
 413                         sil_sata_rw_cmd(sata, start, blks, addr, is_write);
 414                         start += blks;
 415                         blks = 0;
 416                         addr += ATA_SECT_SIZE * blks;
 417                 }
 418         } while (blks != 0);
 419
 420         return blkcnt;
 421 }
 422
 423 static ulong sil_sata_rw_lba48(struct sil_sata *sata, ulong blknr,
 424                                lbaint_t blkcnt, const void *buffer,
 425                                int is_write)
 426 {
 427         ulong start, blks, max_blks;
 428         u8 *addr;
 429
 430         start = blknr;
 431         blks = blkcnt;
 432         addr = (u8 *)buffer;
 433
 434         max_blks = ATA_MAX_SECTORS_LBA48;
 435         do {
 436                 if (blks > max_blks) {
 437                         sil_sata_rw_cmd_ext(sata, start, max_blks,
 438                                             addr, is_write);
 439                         start += max_blks;
 440                         blks -= max_blks;
 441                         addr += ATA_SECT_SIZE * max_blks;
 442                 } else {
 443                         sil_sata_rw_cmd_ext(sata, start, blks,
 444                                             addr, is_write);
 445                         start += blks;
 446                         blks = 0;
 447                         addr += ATA_SECT_SIZE * blks;
 448                 }
 449         } while (blks != 0);
 450
 451         return blkcnt;
 452 }
 453
 454 static void sil_sata_cmd_flush_cache(struct sil_sata *sata)
 455 {
 456         struct sil_cmd_block cmdb, *pcmd = &cmdb;
 457
 458         memset((void *)pcmd, 0, sizeof(struct sil_cmd_block));
 459         pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
 460         pcmd->prb.fis.pm_port_c = (1 << 7);
 461         pcmd->prb.fis.command = ATA_CMD_FLUSH;
 462
 463         sil_exec_cmd(sata, pcmd, 0);
 464 }
 465
 466 static void sil_sata_cmd_flush_cache_ext(struct sil_sata *sata)
 467 {
 468         struct sil_cmd_block cmdb, *pcmd = &cmdb;
 469
 470         memset((void *)pcmd, 0, sizeof(struct sil_cmd_block));
 471         pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
 472         pcmd->prb.fis.pm_port_c = (1 << 7);
 473         pcmd->prb.fis.command = ATA_CMD_FLUSH_EXT;
 474
 475         sil_exec_cmd(sata, pcmd, 0);
 476 }
 477
 478 /*
 479  * SATA interface between low level driver and command layer
 480  */
 481 #if !CONFIG_IS_ENABLED(BLK)
 482 ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
 483 {
 484         struct sil_sata *sata = (struct sil_sata *)sata_dev_desc[dev].priv;
 485 #else
 486 static ulong sata_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
 487                        void *buffer)
 488 {
 489         struct sil_sata_priv *priv = dev_get_platdata(dev);
 490         int port_number = priv->port_num;
 491         struct sil_sata *sata = priv->sil_sata_desc[port_number];
 492 #endif
 493         ulong rc;
 494
 495         if (sata->lba48)
 496                 rc = sil_sata_rw_lba48(sata, blknr, blkcnt, buffer, READ_CMD);
 497         else
 498                 rc = sil_sata_rw_lba28(sata, blknr, blkcnt, buffer, READ_CMD);
 499
 500         return rc;
 501 }
 502
 503 /*
 504  * SATA interface between low level driver and command layer
 505  */
 506 #if !CONFIG_IS_ENABLED(BLK)
 507 ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
 508 {
 509         struct sil_sata *sata = (struct sil_sata *)sata_dev_desc[dev].priv;
 510 #else
 511 ulong sata_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
 512                  const void *buffer)
 513 {
 514         struct sil_sata_priv *priv = dev_get_platdata(dev);
 515         int port_number = priv->port_num;
 516         struct sil_sata *sata = priv->sil_sata_desc[port_number];
 517 #endif
 518         ulong rc;
 519
 520         if (sata->lba48) {
 521                 rc = sil_sata_rw_lba48(sata, blknr, blkcnt, buffer, WRITE_CMD);
 522                 if (sata->wcache && sata->flush_ext)
 523                         sil_sata_cmd_flush_cache_ext(sata);
 524         } else {
 525                 rc = sil_sata_rw_lba28(sata, blknr, blkcnt, buffer, WRITE_CMD);
 526                 if (sata->wcache && sata->flush)
 527                         sil_sata_cmd_flush_cache(sata);
 528         }
 529
 530         return rc;
 531 }
 532
 533 #if !CONFIG_IS_ENABLED(BLK)
 534 static int sil_init_sata(int dev)
 535 {
 536 #else
 537 static int sil_init_sata(struct udevice *uc_dev, int dev)
 538 {
 539         struct sil_sata_priv *priv = dev_get_platdata(uc_dev);
 540 #endif
 541         struct sil_sata *sata;
 542         void *port;
 543         u32 tmp;
 544         int cnt;
 545
 546         printf("SATA#%d:\n", dev);
 547
 548         port = (void *)sata_info.iobase[1] +
 549                 PORT_REGS_SIZE * (dev - sata_info.portbase);
 550
 551         /* Initial PHY setting */
 552         writel(0x20c, port + PORT_PHY_CFG);
 553
 554         /* clear port RST */
 555         tmp = readl(port + PORT_CTRL_STAT);
 556         if (tmp & PORT_CS_PORT_RST) {
 557                 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
 558                 tmp = ata_wait_register(port + PORT_CTRL_STAT,
 559                                 PORT_CS_PORT_RST, PORT_CS_PORT_RST, 100);
 560                 if (tmp & PORT_CS_PORT_RST)
 561                         printf("Err: Failed to clear port RST\n");
 562         }
 563
 564         /* Check if device is present */
 565         for (cnt = 0; cnt < 100; cnt++) {
 566                 tmp = readl(port + PORT_SSTATUS);
 567                 if ((tmp & 0xF) == 0x3)
 568                         break;
 569                 mdelay(1);
 570         }
 571
 572         tmp = readl(port + PORT_SSTATUS);
 573         if ((tmp & 0xf) != 0x3) {
 574                 printf("        (No RDY)\n");
 575                 return 1;
 576         }
 577
 578         /* Wait for port ready */
 579         tmp = ata_wait_register(port + PORT_CTRL_STAT,
 580                                 PORT_CS_RDY, PORT_CS_RDY, 100);
 581         if ((tmp & PORT_CS_RDY) != PORT_CS_RDY) {
 582                 printf("%d port not ready.\n", dev);
 583                 return 1;
 584         }
 585
 586         /* configure port */
 587         sil_config_port(port);
 588
 589         /* Reset port */
 590         writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
 591         readl(port + PORT_CTRL_STAT);
 592         tmp = ata_wait_register(port + PORT_CTRL_STAT, PORT_CS_DEV_RST,
 593                                 PORT_CS_DEV_RST, 100);
 594         if (tmp & PORT_CS_DEV_RST) {
 595                 printf("%d port reset failed.\n", dev);
 596                 return 1;
 597         }
 598
 599         sata = (struct sil_sata *)malloc(sizeof(struct sil_sata));
 600         if (!sata) {
 601                 printf("%d no memory.\n", dev);
 602                 return 1;
 603         }
 604         memset((void *)sata, 0, sizeof(struct sil_sata));
 605
 606         /* Save the private struct to block device struct */
 607 #if !CONFIG_IS_ENABLED(BLK)
 608         sata_dev_desc[dev].priv = (void *)sata;
 609 #else
 610         priv->sil_sata_desc[dev] = sata;
 611         priv->port_num = dev;
 612 #endif
 613         sata->id = dev;
 614         sata->port = port;
 615         sata->devno = sata_info.devno;
 616         sprintf(sata->name, "SATA#%d", dev);
 617         sil_cmd_soft_reset(sata);
 618         tmp = readl(port + PORT_SSTATUS);
 619         tmp = (tmp >> 4) & 0xf;
 620         printf("        (%s)\n", sata_spd_string(tmp));
 621
 622         return 0;
 623 }
 624
 625 #if !CONFIG_IS_ENABLED(BLK)
 626 /*
 627  * SATA interface between low level driver and command layer
 628  */
 629 int init_sata(int dev)
 630 {
 631         static int init_done, idx;
 632         pci_dev_t devno;
 633         u16 word;
 634
 635         if (init_done == 1 && dev < sata_info.maxport)
 636                 goto init_start;
 637
 638         init_done = 1;
 639
 640         /* Find PCI device(s) */
 641         devno = pci_find_devices(supported, idx++);
 642         if (devno == -1)
 643                 return 1;
 644
 645         pci_read_config_word(devno, PCI_DEVICE_ID, &word);
 646
 647         /* get the port count */
 648         word &= 0xf;
 649
 650         sata_info.portbase = 0;
 651         sata_info.maxport = sata_info.portbase + word;
 652         sata_info.devno = devno;
 653
 654         /* Read out all BARs */
 655         sata_info.iobase[0] = (ulong)pci_map_bar(devno,
 656                         PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
 657         sata_info.iobase[1] = (ulong)pci_map_bar(devno,
 658                         PCI_BASE_ADDRESS_2, PCI_REGION_MEM);
 659
 660         /* mask out the unused bits */
 661         sata_info.iobase[0] &= 0xffffff80;
 662         sata_info.iobase[1] &= 0xfffffc00;
 663
 664         /* Enable Bus Mastering and memory region */
 665         pci_write_config_word(devno, PCI_COMMAND,
 666                               PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 667
 668         /* Check if mem accesses and Bus Mastering are enabled. */
 669         pci_read_config_word(devno, PCI_COMMAND, &word);
 670         if (!(word & PCI_COMMAND_MEMORY) ||
 671             (!(word & PCI_COMMAND_MASTER))) {
 672                 printf("Error: Can not enable MEM access or Bus Mastering.\n");
 673                 debug("PCI command: %04x\n", word);
 674                 return 1;
 675         }
 676
 677         /* GPIO off */
 678         writel(0, (void *)(sata_info.iobase[0] + HOST_FLASH_CMD));
 679         /* clear global reset & mask interrupts during initialization */
 680         writel(0, (void *)(sata_info.iobase[0] + HOST_CTRL));
 681
 682 init_start:
 683         return sil_init_sata(dev);
 684 }
 685
 686 int reset_sata(int dev)
 687 {
 688         return 0;
 689 }
 690
 691 /*
 692  * SATA interface between low level driver and command layer
 693  */
 694 int scan_sata(int dev)
 695 {
 696         struct sil_sata *sata = (struct sil_sata *)sata_dev_desc[dev].priv;
 697 #else
 698 static int scan_sata(struct udevice *blk_dev, int dev)
 699 {
 700         struct blk_desc *desc = dev_get_uclass_platdata(blk_dev);
 701         struct sil_sata_priv *priv = dev_get_platdata(blk_dev);
 702         struct sil_sata *sata = priv->sil_sata_desc[dev];
 703 #endif
 704         unsigned char serial[ATA_ID_SERNO_LEN + 1];
 705         unsigned char firmware[ATA_ID_FW_REV_LEN + 1];
 706         unsigned char product[ATA_ID_PROD_LEN + 1];
 707         u16 *id;
 708
 709         id = (u16 *)malloc(ATA_ID_WORDS * 2);
 710         if (!id) {
 711                 printf("Id malloc failed\n");
 712                 return 1;
 713         }
 714         sil_cmd_identify_device(sata, id);
 715
 716         sil_sata_set_feature_by_id(sata, id);
 717
 718         /* Serial number */
 719         ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
 720
 721         /* Firmware version */
 722         ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
 723
 724         /* Product model */
 725         ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
 726
 727 #if !CONFIG_IS_ENABLED(BLK)
 728         memcpy(sata_dev_desc[dev].product, serial, sizeof(serial));
 729         memcpy(sata_dev_desc[dev].revision, firmware, sizeof(firmware));
 730         memcpy(sata_dev_desc[dev].vendor, product, sizeof(product));
 731         /* Totoal sectors */
 732         sata_dev_desc[dev].lba = ata_id_n_sectors(id);
 733 #ifdef CONFIG_LBA48
 734         sata_dev_desc[dev].lba48 = sata->lba48;
 735 #endif
 736 #else
 737         memcpy(desc->product, serial, sizeof(serial));
 738         memcpy(desc->revision, firmware, sizeof(firmware));
 739         memcpy(desc->vendor, product, sizeof(product));
 740         desc->lba = ata_id_n_sectors(id);
 741 #ifdef CONFIG_LBA48
 742         desc->lba48 = sata->lba48;
 743 #endif
 744 #endif
 745
 746 #ifdef DEBUG
 747         ata_dump_id(id);
 748 #endif
 749         free((void *)id);
 750
 751         return 0;
 752 }
 753
 754 #if CONFIG_IS_ENABLED(BLK)
 755 static const struct blk_ops sata_sil_blk_ops = {
 756         .read   = sata_read,
 757         .write  = sata_write,
 758 };
 759
 760 U_BOOT_DRIVER(sata_sil_driver) = {
 761         .name = "sata_sil_blk",
 762         .id = UCLASS_BLK,
 763         .ops = &sata_sil_blk_ops,
 764         .platdata_auto_alloc_size = sizeof(struct sil_sata_priv),
 765 };
 766
 767 static int sil_unbind_device(struct udevice *dev)
 768 {
 769         int ret;
 770
 771         ret = device_remove(dev, DM_REMOVE_NORMAL);
 772         if (ret)
 773                 return ret;
 774
 775         ret = device_unbind(dev);
 776         if (ret)
 777                 return ret;
 778
 779         return 0;
 780 }
 781
 782 static int sil_pci_probe(struct udevice *dev)
 783 {
 784         struct udevice *blk;
 785         int failed_number;
 786         char sata_name[10];
 787         pci_dev_t devno;
 788         u16 word;
 789         int ret;
 790         int i;
 791
 792         failed_number = 0;
 793
 794         /* Get PCI device number */
 795         devno = dm_pci_get_bdf(dev);
 796         if (devno == -1)
 797                 return 1;
 798
 799         dm_pci_read_config16(dev, PCI_DEVICE_ID, &word);
 800
 801         /* get the port count */
 802         word &= 0xf;
 803
 804         sata_info.portbase = 0;
 805         sata_info.maxport = sata_info.portbase + word;
 806         sata_info.devno = devno;
 807
 808         /* Read out all BARs */
 809         sata_info.iobase[0] = (ulong)dm_pci_map_bar(dev,
 810                         PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
 811         sata_info.iobase[1] = (ulong)dm_pci_map_bar(dev,
 812                         PCI_BASE_ADDRESS_2, PCI_REGION_MEM);
 813
 814         /* mask out the unused bits */
 815         sata_info.iobase[0] &= 0xffffff80;
 816         sata_info.iobase[1] &= 0xfffffc00;
 817
 818         /* Enable Bus Mastering and memory region */
 819         dm_pci_write_config16(dev, PCI_COMMAND,
 820                               PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 821
 822         /* Check if mem accesses and Bus Mastering are enabled. */
 823         dm_pci_read_config16(dev, PCI_COMMAND, &word);
 824         if (!(word & PCI_COMMAND_MEMORY) ||
 825             (!(word & PCI_COMMAND_MASTER))) {
 826                 printf("Error: Can not enable MEM access or Bus Mastering.\n");
 827                 debug("PCI command: %04x\n", word);
 828                 return 1;
 829         }
 830
 831         /* GPIO off */
 832         writel(0, (void *)(sata_info.iobase[0] + HOST_FLASH_CMD));
 833         /* clear global reset & mask interrupts during initialization */
 834         writel(0, (void *)(sata_info.iobase[0] + HOST_CTRL));
 835
 836         for (i = sata_info.portbase; i < sata_info.maxport; i++) {
 837                 snprintf(sata_name, sizeof(sata_name), "sil_sata%d", i);
 838                 ret = blk_create_devicef(dev, "sata_sil_blk", sata_name,
 839                                          IF_TYPE_SATA, -1, 512, 0, &blk);
 840                 if (ret) {
 841                         debug("Can't create device\n");
 842                         return ret;
 843                 }
 844
 845                 ret = sil_init_sata(blk, i);
 846                 if (ret) {
 847                         ret = sil_unbind_device(blk);
 848                         if (ret)
 849                                 return ret;
 850
 851                         failed_number++;
 852                         continue;
 853                 }
 854
 855                 ret = scan_sata(blk, i);
 856                 if (ret) {
 857                         ret = sil_unbind_device(blk);
 858                         if (ret)
 859                                 return ret;
 860
 861                         failed_number++;
 862                         continue;
 863                 }
 864         }
 865
 866         if (failed_number == sata_info.maxport)
 867                 return -ENODEV;
 868         else
 869                 return 0;
 870 }
 871
 872 static int sil_pci_remove(struct udevice *dev)
 873 {
 874         int i;
 875         struct sil_sata *sata;
 876         struct sil_sata_priv *priv;
 877
 878         priv = dev_get_priv(dev);
 879
 880         for (i = sata_info.portbase; i < sata_info.maxport; i++) {
 881                 sata = priv->sil_sata_desc[i];
 882                 if (sata)
 883                         free(sata);
 884         }
 885
 886         return 0;
 887 }
 888
 889 static int sata_sil_scan(struct udevice *dev)
 890 {
 891         /* Nothing to do here */
 892
 893         return 0;
 894 }
 895
 896 struct sil_ops sata_sil_ops = {
 897         .scan = sata_sil_scan,
 898 };
 899
 900 static const struct udevice_id sil_pci_ids[] = {
 901         { .compatible = "sil-pci-sample" },
 902         { }
 903 };
 904
 905 U_BOOT_DRIVER(sil_ahci_pci) = {
 906         .name   = "sil_ahci_pci",
 907         .id     = UCLASS_AHCI,
 908         .of_match = sil_pci_ids,
 909         .ops = &sata_sil_ops,
 910         .probe = sil_pci_probe,
 911         .remove = sil_pci_remove,
 912         .priv_auto_alloc_size = sizeof(struct sil_sata_priv),
 913 };
 914
 915 U_BOOT_PCI_DEVICE(sil_ahci_pci, supported);
 916 #endif