arch/arm/mach-rockchip/rk3308/rk3308.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  *Copyright (c) 2018 Rockchip Electronics Co., Ltd
   4  */
   5 #include <common.h>
   6 #include <asm/io.h>
   7 #include <asm/arch/grf_rk3308.h>
   8 #include <asm/arch-rockchip/hardware.h>
   9 #include <asm/gpio.h>
  10 #include <debug_uart.h>
  11
  12 DECLARE_GLOBAL_DATA_PTR;
  13
  14 #include <asm/armv8/mmu.h>
  15 static struct mm_region rk3308_mem_map[] = {
  16         {
  17                 .virt = 0x0UL,
  18                 .phys = 0x0UL,
  19                 .size = 0xff000000UL,
  20                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  21                          PTE_BLOCK_INNER_SHARE
  22         }, {
  23                 .virt = 0xff000000UL,
  24                 .phys = 0xff000000UL,
  25                 .size = 0x01000000UL,
  26                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  27                          PTE_BLOCK_NON_SHARE |
  28                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  29         }, {
  30                 /* List terminator */
  31                 0,
  32         }
  33 };
  34
  35 struct mm_region *mem_map = rk3308_mem_map;
  36
  37 #define GRF_BASE        0xff000000
  38 #define SGRF_BASE       0xff2b0000
  39
  40 enum {
  41         GPIO1C7_SHIFT           = 8,
  42         GPIO1C7_MASK            = GENMASK(11, 8),
  43         GPIO1C7_GPIO            = 0,
  44         GPIO1C7_UART1_RTSN,
  45         GPIO1C7_UART2_TX_M0,
  46         GPIO1C7_SPI2_MOSI,
  47         GPIO1C7_JTAG_TMS,
  48
  49         GPIO1C6_SHIFT           = 4,
  50         GPIO1C6_MASK            = GENMASK(7, 4),
  51         GPIO1C6_GPIO            = 0,
  52         GPIO1C6_UART1_CTSN,
  53         GPIO1C6_UART2_RX_M0,
  54         GPIO1C6_SPI2_MISO,
  55         GPIO1C6_JTAG_TCLK,
  56
  57         GPIO4D3_SHIFT           = 6,
  58         GPIO4D3_MASK            = GENMASK(7, 6),
  59         GPIO4D3_GPIO            = 0,
  60         GPIO4D3_SDMMC_D3,
  61         GPIO4D3_UART2_TX_M1,
  62
  63         GPIO4D2_SHIFT           = 4,
  64         GPIO4D2_MASK            = GENMASK(5, 4),
  65         GPIO4D2_GPIO            = 0,
  66         GPIO4D2_SDMMC_D2,
  67         GPIO4D2_UART2_RX_M1,
  68
  69         UART2_IO_SEL_SHIFT      = 2,
  70         UART2_IO_SEL_MASK       = GENMASK(3, 2),
  71         UART2_IO_SEL_M0         = 0,
  72         UART2_IO_SEL_M1,
  73         UART2_IO_SEL_USB,
  74
  75         GPIO2C0_SEL_SRC_CTRL_SHIFT      = 11,
  76         GPIO2C0_SEL_SRC_CTRL_MASK       = BIT(11),
  77         GPIO2C0_SEL_SRC_CTRL_IOMUX      = 0,
  78         GPIO2C0_SEL_SRC_CTRL_SEL_PLUS,
  79
  80         GPIO3B3_SEL_SRC_CTRL_SHIFT      = 7,
  81         GPIO3B3_SEL_SRC_CTRL_MASK       = BIT(7),
  82         GPIO3B3_SEL_SRC_CTRL_IOMUX      = 0,
  83         GPIO3B3_SEL_SRC_CTRL_SEL_PLUS,
  84
  85         GPIO3B3_SEL_PLUS_SHIFT          = 4,
  86         GPIO3B3_SEL_PLUS_MASK           = GENMASK(6, 4),
  87         GPIO3B3_SEL_PLUS_GPIO3_B3       = 0,
  88         GPIO3B3_SEL_PLUS_FLASH_ALE,
  89         GPIO3B3_SEL_PLUS_EMMC_PWREN,
  90         GPIO3B3_SEL_PLUS_SPI1_CLK,
  91         GPIO3B3_SEL_PLUS_LCDC_D23_M1,
  92
  93         GPIO3B2_SEL_SRC_CTRL_SHIFT      = 3,
  94         GPIO3B2_SEL_SRC_CTRL_MASK       = BIT(3),
  95         GPIO3B2_SEL_SRC_CTRL_IOMUX      = 0,
  96         GPIO3B2_SEL_SRC_CTRL_SEL_PLUS,
  97
  98         GPIO3B2_SEL_PLUS_SHIFT          = 0,
  99         GPIO3B2_SEL_PLUS_MASK           = GENMASK(2, 0),
 100         GPIO3B2_SEL_PLUS_GPIO3_B2       = 0,
 101         GPIO3B2_SEL_PLUS_FLASH_RDN,
 102         GPIO3B2_SEL_PLUS_EMMC_RSTN,
 103         GPIO3B2_SEL_PLUS_SPI1_MISO,
 104         GPIO3B2_SEL_PLUS_LCDC_D22_M1,
 105
 106         I2C3_IOFUNC_SRC_CTRL_SHIFT      = 10,
 107         I2C3_IOFUNC_SRC_CTRL_MASK       = BIT(10),
 108         I2C3_IOFUNC_SRC_CTRL_SEL_PLUS   = 1,
 109
 110         GPIO2A3_SEL_SRC_CTRL_SHIFT      = 7,
 111         GPIO2A3_SEL_SRC_CTRL_MASK       = BIT(7),
 112         GPIO2A3_SEL_SRC_CTRL_SEL_PLUS   = 1,
 113
 114         GPIO2A2_SEL_SRC_CTRL_SHIFT      = 3,
 115         GPIO2A2_SEL_SRC_CTRL_MASK       = BIT(3),
 116         GPIO2A2_SEL_SRC_CTRL_SEL_PLUS   = 1,
 117 };
 118
 119 enum {
 120         IOVSEL3_CTRL_SHIFT      = 8,
 121         IOVSEL3_CTRL_MASK       = BIT(8),
 122         VCCIO3_SEL_BY_GPIO      = 0,
 123         VCCIO3_SEL_BY_IOVSEL3,
 124
 125         IOVSEL3_SHIFT           = 3,
 126         IOVSEL3_MASK            = BIT(3),
 127         VCCIO3_3V3              = 0,
 128         VCCIO3_1V8,
 129 };
 130
 131 /*
 132  * The voltage of VCCIO3(which is the voltage domain of emmc/flash/sfc
 133  * interface) can indicated by GPIO0_A4 or io_vsel3. The SOC defaults
 134  * use GPIO0_A4 to indicate power supply voltage for VCCIO3 by hardware,
 135  * then we can switch to io_vsel3 after system power on, and release GPIO0_A4
 136  * for other usage.
 137  */
 138
 139 #define GPIO0_A4        4
 140
 141 int rk_board_init(void)
 142 {
 143         static struct rk3308_grf * const grf = (void *)GRF_BASE;
 144         u32 val;
 145         int ret;
 146
 147         ret = gpio_request(GPIO0_A4, "gpio0_a4");
 148         if (ret < 0) {
 149                 printf("request for gpio0_a4 failed:%d\n", ret);
 150                 return 0;
 151         }
 152
 153         gpio_direction_input(GPIO0_A4);
 154
 155         if (gpio_get_value(GPIO0_A4))
 156                 val = VCCIO3_SEL_BY_IOVSEL3 << IOVSEL3_CTRL_SHIFT |
 157                       VCCIO3_1V8 << IOVSEL3_SHIFT;
 158         else
 159                 val = VCCIO3_SEL_BY_IOVSEL3 << IOVSEL3_CTRL_SHIFT |
 160                       VCCIO3_3V3 << IOVSEL3_SHIFT;
 161         rk_clrsetreg(&grf->soc_con0, IOVSEL3_CTRL_MASK | IOVSEL3_MASK, val);
 162
 163         gpio_free(GPIO0_A4);
 164         return 0;
 165 }
 166
 167 #if defined(CONFIG_DEBUG_UART)
 168 __weak void board_debug_uart_init(void)
 169 {
 170         static struct rk3308_grf * const grf = (void *)GRF_BASE;
 171
 172         /* Enable early UART2 channel m1 on the rk3308 */
 173         rk_clrsetreg(&grf->soc_con5, UART2_IO_SEL_MASK,
 174                      UART2_IO_SEL_M1 << UART2_IO_SEL_SHIFT);
 175         rk_clrsetreg(&grf->gpio4d_iomux,
 176                      GPIO4D3_MASK | GPIO4D2_MASK,
 177                      GPIO4D2_UART2_RX_M1 << GPIO4D2_SHIFT |
 178                      GPIO4D3_UART2_TX_M1 << GPIO4D3_SHIFT);
 179 }
 180 #endif
 181
 182 #if defined(CONFIG_SPL_BUILD)
 183 int arch_cpu_init(void)
 184 {
 185         static struct rk3308_sgrf * const sgrf = (void *)SGRF_BASE;
 186         static struct rk3308_grf * const grf = (void *)GRF_BASE;
 187
 188         /* Set CRYPTO SDMMC EMMC NAND SFC USB master bus to be secure access */
 189         rk_clrreg(&sgrf->con_secure0, 0x2b83);
 190
 191         /*
 192          * Enable plus options to use more pinctrl functions, including
 193          * GPIO2A2_PLUS, GPIO2A3_PLUS and I2C3_MULTI_SRC_PLUS.
 194          */
 195         rk_clrsetreg(&grf->soc_con13,
 196                      I2C3_IOFUNC_SRC_CTRL_MASK | GPIO2A3_SEL_SRC_CTRL_MASK |
 197                      GPIO2A2_SEL_SRC_CTRL_MASK,
 198                      I2C3_IOFUNC_SRC_CTRL_SEL_PLUS << I2C3_IOFUNC_SRC_CTRL_SHIFT |
 199                      GPIO2A3_SEL_SRC_CTRL_SEL_PLUS << GPIO2A3_SEL_SRC_CTRL_SHIFT |
 200                      GPIO2A2_SEL_SRC_CTRL_SEL_PLUS << GPIO2A2_SEL_SRC_CTRL_SHIFT);
 201
 202         /* Plus options about GPIO3B2_PLUS, GPIO3B3_PLUS and GPIO2C0_PLUS. */
 203         rk_clrsetreg(&grf->soc_con15,
 204                      GPIO2C0_SEL_SRC_CTRL_MASK | GPIO3B3_SEL_SRC_CTRL_MASK |
 205                      GPIO3B2_SEL_SRC_CTRL_MASK,
 206                      GPIO2C0_SEL_SRC_CTRL_SEL_PLUS << GPIO2C0_SEL_SRC_CTRL_SHIFT |
 207                      GPIO3B3_SEL_SRC_CTRL_SEL_PLUS << GPIO3B3_SEL_SRC_CTRL_SHIFT |
 208                      GPIO3B2_SEL_SRC_CTRL_SEL_PLUS << GPIO3B2_SEL_SRC_CTRL_SHIFT);
 209
 210         return 0;
 211 }
 212 #endif