drivers/mmc/zynq_sdhci.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2013 - 2015 Xilinx, Inc.
   4  *
   5  * Xilinx Zynq SD Host Controller Interface
   6  */
   7
   8 #include <clk.h>
   9 #include <common.h>
  10 #include <dm.h>
  11 #include <fdtdec.h>
  12 #include <linux/delay.h>
  13 #include "mmc_private.h"
  14 #include <log.h>
  15 #include <dm/device_compat.h>
  16 #include <linux/err.h>
  17 #include <linux/libfdt.h>
  18 #include <asm/cache.h>
  19 #include <malloc.h>
  20 #include <sdhci.h>
  21 #include <zynqmp_firmware.h>
  22
  23 #define SDHCI_ARASAN_ITAPDLY_REGISTER   0xF0F8
  24 #define SDHCI_ARASAN_ITAPDLY_SEL_MASK   GENMASK(7, 0)
  25 #define SDHCI_ARASAN_OTAPDLY_REGISTER   0xF0FC
  26 #define SDHCI_ARASAN_OTAPDLY_SEL_MASK   GENMASK(5, 0)
  27 #define SDHCI_ITAPDLY_CHGWIN            BIT(9)
  28 #define SDHCI_ITAPDLY_ENABLE            BIT(8)
  29 #define SDHCI_OTAPDLY_ENABLE            BIT(6)
  30
  31 #define SDHCI_TUNING_LOOP_COUNT         40
  32 #define MMC_BANK2                       0x2
  33
  34 #define SD_DLL_CTRL                     0xFF180358
  35 #define SD_ITAP_DLY                     0xFF180314
  36 #define SD_OTAP_DLY                     0xFF180318
  37 #define SD0_DLL_RST                     BIT(2)
  38 #define SD1_DLL_RST                     BIT(18)
  39 #define SD0_ITAPCHGWIN                  BIT(9)
  40 #define SD1_ITAPCHGWIN                  BIT(25)
  41 #define SD0_ITAPDLYENA                  BIT(8)
  42 #define SD1_ITAPDLYENA                  BIT(24)
  43 #define SD0_ITAPDLYSEL_MASK             GENMASK(7, 0)
  44 #define SD1_ITAPDLYSEL_MASK             GENMASK(23, 16)
  45 #define SD0_OTAPDLYSEL_MASK             GENMASK(5, 0)
  46 #define SD1_OTAPDLYSEL_MASK             GENMASK(21, 16)
  47
  48 struct arasan_sdhci_clk_data {
  49         int clk_phase_in[MMC_TIMING_MMC_HS400 + 1];
  50         int clk_phase_out[MMC_TIMING_MMC_HS400 + 1];
  51 };
  52
  53 struct arasan_sdhci_plat {
  54         struct mmc_config cfg;
  55         struct mmc mmc;
  56 };
  57
  58 struct arasan_sdhci_priv {
  59         struct sdhci_host *host;
  60         struct arasan_sdhci_clk_data clk_data;
  61         u8 deviceid;
  62         u8 bank;
  63         u8 no_1p8;
  64 };
  65
  66 /* For Versal platforms zynqmp_mmio_write() won't be available */
  67 __weak int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value)
  68 {
  69         return 0;
  70 }
  71
  72 __weak int xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
  73                              u32 arg3, u32 *ret_payload)
  74 {
  75         return 0;
  76 }
  77
  78 #if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL)
  79 /* Default settings for ZynqMP Clock Phases */
  80 static const u32 zynqmp_iclk_phases[] = {0, 63, 63, 0, 63,  0,
  81                                          0, 183, 54,  0, 0};
  82 static const u32 zynqmp_oclk_phases[] = {0, 72, 60, 0, 60, 72,
  83                                          135, 48, 72, 135, 0};
  84
  85 /* Default settings for Versal Clock Phases */
  86 static const u32 versal_iclk_phases[] = {0, 132, 132, 0, 132,
  87                                          0, 0, 162, 90, 0, 0};
  88 static const u32 versal_oclk_phases[] = {0,  60, 48, 0, 48, 72,
  89                                          90, 36, 60, 90, 0};
  90
  91 static const u8 mode2timing[] = {
  92         [MMC_LEGACY] = MMC_TIMING_LEGACY,
  93         [MMC_HS] = MMC_TIMING_MMC_HS,
  94         [SD_HS] = MMC_TIMING_SD_HS,
  95         [MMC_HS_52] = MMC_TIMING_UHS_SDR50,
  96         [MMC_DDR_52] = MMC_TIMING_UHS_DDR50,
  97         [UHS_SDR12] = MMC_TIMING_UHS_SDR12,
  98         [UHS_SDR25] = MMC_TIMING_UHS_SDR25,
  99         [UHS_SDR50] = MMC_TIMING_UHS_SDR50,
 100         [UHS_DDR50] = MMC_TIMING_UHS_DDR50,
 101         [UHS_SDR104] = MMC_TIMING_UHS_SDR104,
 102         [MMC_HS_200] = MMC_TIMING_MMC_HS200,
 103 };
 104
 105 static inline int arasan_zynqmp_set_in_tapdelay(u8 node_id, u32 itap_delay)
 106 {
 107         int ret;
 108
 109         if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
 110                 if (node_id == NODE_SD_0) {
 111                         ret = zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN,
 112                                                 SD0_ITAPCHGWIN);
 113                         if (ret)
 114                                 return ret;
 115
 116                         ret = zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYENA,
 117                                                 SD0_ITAPDLYENA);
 118                         if (ret)
 119                                 return ret;
 120
 121                         ret = zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYSEL_MASK,
 122                                                 itap_delay);
 123                         if (ret)
 124                                 return ret;
 125
 126                         ret = zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN, 0);
 127                         if (ret)
 128                                 return ret;
 129                 }
 130                 ret = zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN,
 131                                         SD1_ITAPCHGWIN);
 132                 if (ret)
 133                         return ret;
 134
 135                 ret = zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYENA,
 136                                         SD1_ITAPDLYENA);
 137                 if (ret)
 138                         return ret;
 139
 140                 ret = zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYSEL_MASK,
 141                                         (itap_delay << 16));
 142                 if (ret)
 143                         return ret;
 144
 145                 ret = zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN, 0);
 146                 if (ret)
 147                         return ret;
 148         } else {
 149                 return xilinx_pm_request(PM_IOCTL, (u32)node_id,
 150                                          IOCTL_SET_SD_TAPDELAY,
 151                                          PM_TAPDELAY_INPUT, itap_delay, NULL);
 152         }
 153
 154         return 0;
 155 }
 156
 157 static inline int arasan_zynqmp_set_out_tapdelay(u8 node_id, u32 otap_delay)
 158 {
 159         if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
 160                 if (node_id == NODE_SD_0)
 161                         return zynqmp_mmio_write(SD_OTAP_DLY,
 162                                                  SD0_OTAPDLYSEL_MASK,
 163                                                  otap_delay);
 164
 165                 return zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
 166                                          (otap_delay << 16));
 167         } else {
 168                 return xilinx_pm_request(PM_IOCTL, (u32)node_id,
 169                                          IOCTL_SET_SD_TAPDELAY,
 170                                          PM_TAPDELAY_OUTPUT, otap_delay, NULL);
 171         }
 172 }
 173
 174 static inline int zynqmp_dll_reset(u8 node_id, u32 type)
 175 {
 176         if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
 177                 if (node_id == NODE_SD_0)
 178                         return zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST,
 179                                                  type == PM_DLL_RESET_ASSERT ?
 180                                                  SD0_DLL_RST : 0);
 181
 182                 return zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST,
 183                                          type == PM_DLL_RESET_ASSERT ?
 184                                          SD1_DLL_RST : 0);
 185         } else {
 186                 return xilinx_pm_request(PM_IOCTL, (u32)node_id,
 187                                          IOCTL_SD_DLL_RESET, type, 0, NULL);
 188         }
 189 }
 190
 191 static int arasan_zynqmp_dll_reset(struct sdhci_host *host, u8 node_id)
 192 {
 193         struct mmc *mmc = (struct mmc *)host->mmc;
 194         struct udevice *dev = mmc->dev;
 195         unsigned long timeout;
 196         int ret;
 197         u16 clk;
 198
 199         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
 200         clk &= ~(SDHCI_CLOCK_CARD_EN);
 201         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 202
 203         /* Issue DLL Reset */
 204         ret = zynqmp_dll_reset(node_id, PM_DLL_RESET_ASSERT);
 205         if (ret) {
 206                 dev_err(dev, "dll_reset assert failed with err: %d\n", ret);
 207                 return ret;
 208         }
 209
 210         /* Allow atleast 1ms delay for proper DLL reset */
 211         mdelay(1);
 212         ret = zynqmp_dll_reset(node_id, PM_DLL_RESET_RELEASE);
 213         if (ret) {
 214                 dev_err(dev, "dll_reset release failed with err: %d\n", ret);
 215                 return ret;
 216         }
 217
 218         /* Wait max 20 ms */
 219         timeout = 100;
 220         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
 221                                 & SDHCI_CLOCK_INT_STABLE)) {
 222                 if (timeout == 0) {
 223                         dev_err(dev, ": Internal clock never stabilised.\n");
 224                         return -EBUSY;
 225                 }
 226                 timeout--;
 227                 udelay(1000);
 228         }
 229
 230         clk |= SDHCI_CLOCK_CARD_EN;
 231         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 232
 233         return 0;
 234 }
 235
 236 static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
 237 {
 238         struct mmc_cmd cmd;
 239         struct mmc_data data;
 240         u32 ctrl;
 241         struct sdhci_host *host;
 242         struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev);
 243         char tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT;
 244         u8 node_id = priv->deviceid ? NODE_SD_1 : NODE_SD_0;
 245
 246         debug("%s\n", __func__);
 247
 248         host = priv->host;
 249
 250         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 251         ctrl |= SDHCI_CTRL_EXEC_TUNING;
 252         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
 253
 254         mdelay(1);
 255
 256         arasan_zynqmp_dll_reset(host, node_id);
 257
 258         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
 259         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
 260
 261         do {
 262                 cmd.cmdidx = opcode;
 263                 cmd.resp_type = MMC_RSP_R1;
 264                 cmd.cmdarg = 0;
 265
 266                 data.blocksize = 64;
 267                 data.blocks = 1;
 268                 data.flags = MMC_DATA_READ;
 269
 270                 if (tuning_loop_counter-- == 0)
 271                         break;
 272
 273                 if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200 &&
 274                     mmc->bus_width == 8)
 275                         data.blocksize = 128;
 276
 277                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
 278                                                     data.blocksize),
 279                              SDHCI_BLOCK_SIZE);
 280                 sdhci_writew(host, data.blocks, SDHCI_BLOCK_COUNT);
 281                 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
 282
 283                 mmc_send_cmd(mmc, &cmd, NULL);
 284                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 285
 286                 if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK)
 287                         udelay(1);
 288
 289         } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
 290
 291         if (tuning_loop_counter < 0) {
 292                 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
 293                 sdhci_writel(host, ctrl, SDHCI_HOST_CONTROL2);
 294         }
 295
 296         if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
 297                 printf("%s:Tuning failed\n", __func__);
 298                 return -1;
 299         }
 300
 301         udelay(1);
 302         arasan_zynqmp_dll_reset(host, node_id);
 303
 304         /* Enable only interrupts served by the SD controller */
 305         sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
 306                      SDHCI_INT_ENABLE);
 307         /* Mask all sdhci interrupt sources */
 308         sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
 309
 310         return 0;
 311 }
 312
 313 /**
 314  * sdhci_zynqmp_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
 315  *
 316  * @host:               Pointer to the sdhci_host structure.
 317  * @degrees:            The clock phase shift between 0 - 359.
 318  * Return: 0
 319  *
 320  * Set the SD Output Clock Tap Delays for Output path
 321  */
 322 static int sdhci_zynqmp_sdcardclk_set_phase(struct sdhci_host *host,
 323                                             int degrees)
 324 {
 325         struct mmc *mmc = (struct mmc *)host->mmc;
 326         struct udevice *dev = mmc->dev;
 327         struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev);
 328         u8 node_id = priv->deviceid ? NODE_SD_1 : NODE_SD_0;
 329         u8 tap_delay, tap_max = 0;
 330         int timing = mode2timing[mmc->selected_mode];
 331         int ret;
 332
 333         /*
 334          * This is applicable for SDHCI_SPEC_300 and above
 335          * ZynqMP does not set phase for <=25MHz clock.
 336          * If degrees is zero, no need to do anything.
 337          */
 338         if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300)
 339                 return 0;
 340
 341         switch (timing) {
 342         case MMC_TIMING_MMC_HS:
 343         case MMC_TIMING_SD_HS:
 344         case MMC_TIMING_UHS_SDR25:
 345         case MMC_TIMING_UHS_DDR50:
 346         case MMC_TIMING_MMC_DDR52:
 347                 /* For 50MHz clock, 30 Taps are available */
 348                 tap_max = 30;
 349                 break;
 350         case MMC_TIMING_UHS_SDR50:
 351                 /* For 100MHz clock, 15 Taps are available */
 352                 tap_max = 15;
 353                 break;
 354         case MMC_TIMING_UHS_SDR104:
 355         case MMC_TIMING_MMC_HS200:
 356                 /* For 200MHz clock, 8 Taps are available */
 357                 tap_max = 8;
 358         default:
 359                 break;
 360         }
 361
 362         tap_delay = (degrees * tap_max) / 360;
 363
 364         /* Limit output tap_delay value to 6 bits */
 365         tap_delay &= SDHCI_ARASAN_OTAPDLY_SEL_MASK;
 366
 367         /* Set the Clock Phase */
 368         ret = arasan_zynqmp_set_out_tapdelay(node_id, tap_delay);
 369         if (ret) {
 370                 dev_err(dev, "Error setting output Tap Delay\n");
 371                 return ret;
 372         }
 373
 374         /* Release DLL Reset */
 375         ret = zynqmp_dll_reset(node_id, PM_DLL_RESET_RELEASE);
 376         if (ret) {
 377                 dev_err(dev, "dll_reset release failed with err: %d\n", ret);
 378                 return ret;
 379         }
 380
 381         return 0;
 382 }
 383
 384 /**
 385  * sdhci_zynqmp_sampleclk_set_phase - Set the SD Input Clock Tap Delays
 386  *
 387  * @host:               Pointer to the sdhci_host structure.
 388  * @degrees:            The clock phase shift between 0 - 359.
 389  * Return: 0
 390  *
 391  * Set the SD Input Clock Tap Delays for Input path
 392  */
 393 static int sdhci_zynqmp_sampleclk_set_phase(struct sdhci_host *host,
 394                                             int degrees)
 395 {
 396         struct mmc *mmc = (struct mmc *)host->mmc;
 397         struct udevice *dev = mmc->dev;
 398         struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev);
 399         u8 node_id = priv->deviceid ? NODE_SD_1 : NODE_SD_0;
 400         u8 tap_delay, tap_max = 0;
 401         int timing = mode2timing[mmc->selected_mode];
 402         int ret;
 403
 404         /*
 405          * This is applicable for SDHCI_SPEC_300 and above
 406          * ZynqMP does not set phase for <=25MHz clock.
 407          * If degrees is zero, no need to do anything.
 408          */
 409         if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300)
 410                 return 0;
 411
 412         /* Assert DLL Reset */
 413         ret = zynqmp_dll_reset(node_id, PM_DLL_RESET_ASSERT);
 414         if (ret) {
 415                 dev_err(dev, "dll_reset assert failed with err: %d\n", ret);
 416                 return ret;
 417         }
 418
 419         switch (timing) {
 420         case MMC_TIMING_MMC_HS:
 421         case MMC_TIMING_SD_HS:
 422         case MMC_TIMING_UHS_SDR25:
 423         case MMC_TIMING_UHS_DDR50:
 424         case MMC_TIMING_MMC_DDR52:
 425                 /* For 50MHz clock, 120 Taps are available */
 426                 tap_max = 120;
 427                 break;
 428         case MMC_TIMING_UHS_SDR50:
 429                 /* For 100MHz clock, 60 Taps are available */
 430                 tap_max = 60;
 431                 break;
 432         case MMC_TIMING_UHS_SDR104:
 433         case MMC_TIMING_MMC_HS200:
 434                 /* For 200MHz clock, 30 Taps are available */
 435                 tap_max = 30;
 436         default:
 437                 break;
 438         }
 439
 440         tap_delay = (degrees * tap_max) / 360;
 441
 442         /* Limit input tap_delay value to 8 bits */
 443         tap_delay &= SDHCI_ARASAN_ITAPDLY_SEL_MASK;
 444
 445         ret = arasan_zynqmp_set_in_tapdelay(node_id, tap_delay);
 446         if (ret) {
 447                 dev_err(dev, "Error setting Input Tap Delay\n");
 448                 return ret;
 449         }
 450
 451         return 0;
 452 }
 453
 454 /**
 455  * sdhci_versal_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
 456  *
 457  * @host:               Pointer to the sdhci_host structure.
 458  * @degrees:            The clock phase shift between 0 - 359.
 459  * Return: 0
 460  *
 461  * Set the SD Output Clock Tap Delays for Output path
 462  */
 463 static int sdhci_versal_sdcardclk_set_phase(struct sdhci_host *host,
 464                                             int degrees)
 465 {
 466         struct mmc *mmc = (struct mmc *)host->mmc;
 467         u8 tap_delay, tap_max = 0;
 468         int timing = mode2timing[mmc->selected_mode];
 469         u32 regval;
 470
 471         /*
 472          * This is applicable for SDHCI_SPEC_300 and above
 473          * Versal does not set phase for <=25MHz clock.
 474          * If degrees is zero, no need to do anything.
 475          */
 476         if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300)
 477                 return 0;
 478
 479         switch (timing) {
 480         case MMC_TIMING_MMC_HS:
 481         case MMC_TIMING_SD_HS:
 482         case MMC_TIMING_UHS_SDR25:
 483         case MMC_TIMING_UHS_DDR50:
 484         case MMC_TIMING_MMC_DDR52:
 485                 /* For 50MHz clock, 30 Taps are available */
 486                 tap_max = 30;
 487                 break;
 488         case MMC_TIMING_UHS_SDR50:
 489                 /* For 100MHz clock, 15 Taps are available */
 490                 tap_max = 15;
 491                 break;
 492         case MMC_TIMING_UHS_SDR104:
 493         case MMC_TIMING_MMC_HS200:
 494                 /* For 200MHz clock, 8 Taps are available */
 495                 tap_max = 8;
 496         default:
 497                 break;
 498         }
 499
 500         tap_delay = (degrees * tap_max) / 360;
 501
 502         /* Limit output tap_delay value to 6 bits */
 503         tap_delay &= SDHCI_ARASAN_OTAPDLY_SEL_MASK;
 504
 505         /* Set the Clock Phase */
 506         regval = sdhci_readl(host, SDHCI_ARASAN_OTAPDLY_REGISTER);
 507         regval |= SDHCI_OTAPDLY_ENABLE;
 508         sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
 509         regval &= ~SDHCI_ARASAN_OTAPDLY_SEL_MASK;
 510         regval |= tap_delay;
 511         sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
 512
 513         return 0;
 514 }
 515
 516 /**
 517  * sdhci_versal_sampleclk_set_phase - Set the SD Input Clock Tap Delays
 518  *
 519  * @host:               Pointer to the sdhci_host structure.
 520  * @degrees:            The clock phase shift between 0 - 359.
 521  * Return: 0
 522  *
 523  * Set the SD Input Clock Tap Delays for Input path
 524  */
 525 static int sdhci_versal_sampleclk_set_phase(struct sdhci_host *host,
 526                                             int degrees)
 527 {
 528         struct mmc *mmc = (struct mmc *)host->mmc;
 529         u8 tap_delay, tap_max = 0;
 530         int timing = mode2timing[mmc->selected_mode];
 531         u32 regval;
 532
 533         /*
 534          * This is applicable for SDHCI_SPEC_300 and above
 535          * Versal does not set phase for <=25MHz clock.
 536          * If degrees is zero, no need to do anything.
 537          */
 538         if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300)
 539                 return 0;
 540
 541         switch (timing) {
 542         case MMC_TIMING_MMC_HS:
 543         case MMC_TIMING_SD_HS:
 544         case MMC_TIMING_UHS_SDR25:
 545         case MMC_TIMING_UHS_DDR50:
 546         case MMC_TIMING_MMC_DDR52:
 547                 /* For 50MHz clock, 120 Taps are available */
 548                 tap_max = 120;
 549                 break;
 550         case MMC_TIMING_UHS_SDR50:
 551                 /* For 100MHz clock, 60 Taps are available */
 552                 tap_max = 60;
 553                 break;
 554         case MMC_TIMING_UHS_SDR104:
 555         case MMC_TIMING_MMC_HS200:
 556                 /* For 200MHz clock, 30 Taps are available */
 557                 tap_max = 30;
 558         default:
 559                 break;
 560         }
 561
 562         tap_delay = (degrees * tap_max) / 360;
 563
 564         /* Limit input tap_delay value to 8 bits */
 565         tap_delay &= SDHCI_ARASAN_ITAPDLY_SEL_MASK;
 566
 567         /* Set the Clock Phase */
 568         regval = sdhci_readl(host, SDHCI_ARASAN_ITAPDLY_REGISTER);
 569         regval |= SDHCI_ITAPDLY_CHGWIN;
 570         sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
 571         regval |= SDHCI_ITAPDLY_ENABLE;
 572         sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
 573         regval &= ~SDHCI_ARASAN_ITAPDLY_SEL_MASK;
 574         regval |= tap_delay;
 575         sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
 576         regval &= ~SDHCI_ITAPDLY_CHGWIN;
 577         sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
 578
 579         return 0;
 580 }
 581
 582 static int arasan_sdhci_set_tapdelay(struct sdhci_host *host)
 583 {
 584         struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev);
 585         struct arasan_sdhci_clk_data *clk_data = &priv->clk_data;
 586         struct mmc *mmc = (struct mmc *)host->mmc;
 587         struct udevice *dev = mmc->dev;
 588         u8 timing = mode2timing[mmc->selected_mode];
 589         u32 iclk_phase = clk_data->clk_phase_in[timing];
 590         u32 oclk_phase = clk_data->clk_phase_out[timing];
 591         int ret;
 592
 593         dev_dbg(dev, "%s, host:%s, mode:%d\n", __func__, host->name, timing);
 594
 595         if (IS_ENABLED(CONFIG_ARCH_ZYNQMP) &&
 596             device_is_compatible(dev, "xlnx,zynqmp-8.9a")) {
 597                 ret = sdhci_zynqmp_sampleclk_set_phase(host, iclk_phase);
 598                 if (ret)
 599                         return ret;
 600
 601                 ret = sdhci_zynqmp_sdcardclk_set_phase(host, oclk_phase);
 602                 if (ret)
 603                         return ret;
 604         } else if (IS_ENABLED(CONFIG_ARCH_VERSAL) &&
 605                    device_is_compatible(dev, "xlnx,versal-8.9a")) {
 606                 ret = sdhci_versal_sampleclk_set_phase(host, iclk_phase);
 607                 if (ret)
 608                         return ret;
 609
 610                 ret = sdhci_versal_sdcardclk_set_phase(host, oclk_phase);
 611                 if (ret)
 612                         return ret;
 613         }
 614
 615         return 0;
 616 }
 617
 618 static void arasan_dt_read_clk_phase(struct udevice *dev, unsigned char timing,
 619                                      const char *prop)
 620 {
 621         struct arasan_sdhci_priv *priv = dev_get_priv(dev);
 622         struct arasan_sdhci_clk_data *clk_data = &priv->clk_data;
 623         u32 clk_phase[2] = {0};
 624
 625         /*
 626          * Read Tap Delay values from DT, if the DT does not contain the
 627          * Tap Values then use the pre-defined values
 628          */
 629         if (dev_read_u32_array(dev, prop, &clk_phase[0], 2)) {
 630                 dev_dbg(dev, "Using predefined clock phase for %s = %d %d\n",
 631                         prop, clk_data->clk_phase_in[timing],
 632                         clk_data->clk_phase_out[timing]);
 633                 return;
 634         }
 635
 636         /* The values read are Input and Output Clock Delays in order */
 637         clk_data->clk_phase_in[timing] = clk_phase[0];
 638         clk_data->clk_phase_out[timing] = clk_phase[1];
 639 }
 640
 641 /**
 642  * arasan_dt_parse_clk_phases - Read Tap Delay values from DT
 643  *
 644  * @dev:                Pointer to our struct udevice.
 645  *
 646  * Called at initialization to parse the values of Tap Delays.
 647  */
 648 static void arasan_dt_parse_clk_phases(struct udevice *dev)
 649 {
 650         struct arasan_sdhci_priv *priv = dev_get_priv(dev);
 651         struct arasan_sdhci_clk_data *clk_data = &priv->clk_data;
 652         int i;
 653
 654         if (IS_ENABLED(CONFIG_ARCH_ZYNQMP) &&
 655             device_is_compatible(dev, "xlnx,zynqmp-8.9a")) {
 656                 for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
 657                         clk_data->clk_phase_in[i] = zynqmp_iclk_phases[i];
 658                         clk_data->clk_phase_out[i] = zynqmp_oclk_phases[i];
 659                 }
 660
 661                 if (priv->bank == MMC_BANK2) {
 662                         clk_data->clk_phase_out[MMC_TIMING_UHS_SDR104] = 90;
 663                         clk_data->clk_phase_out[MMC_TIMING_MMC_HS200] = 90;
 664                 }
 665         }
 666
 667         if (IS_ENABLED(CONFIG_ARCH_VERSAL) &&
 668             device_is_compatible(dev, "xlnx,versal-8.9a")) {
 669                 for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
 670                         clk_data->clk_phase_in[i] = versal_iclk_phases[i];
 671                         clk_data->clk_phase_out[i] = versal_oclk_phases[i];
 672                 }
 673         }
 674
 675         arasan_dt_read_clk_phase(dev, MMC_TIMING_LEGACY,
 676                                  "clk-phase-legacy");
 677         arasan_dt_read_clk_phase(dev, MMC_TIMING_MMC_HS,
 678                                  "clk-phase-mmc-hs");
 679         arasan_dt_read_clk_phase(dev, MMC_TIMING_SD_HS,
 680                                  "clk-phase-sd-hs");
 681         arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR12,
 682                                  "clk-phase-uhs-sdr12");
 683         arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR25,
 684                                  "clk-phase-uhs-sdr25");
 685         arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR50,
 686                                  "clk-phase-uhs-sdr50");
 687         arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR104,
 688                                  "clk-phase-uhs-sdr104");
 689         arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_DDR50,
 690                                  "clk-phase-uhs-ddr50");
 691         arasan_dt_read_clk_phase(dev, MMC_TIMING_MMC_DDR52,
 692                                  "clk-phase-mmc-ddr52");
 693         arasan_dt_read_clk_phase(dev, MMC_TIMING_MMC_HS200,
 694                                  "clk-phase-mmc-hs200");
 695         arasan_dt_read_clk_phase(dev, MMC_TIMING_MMC_HS400,
 696                                  "clk-phase-mmc-hs400");
 697 }
 698
 699 static const struct sdhci_ops arasan_ops = {
 700         .platform_execute_tuning        = &arasan_sdhci_execute_tuning,
 701         .set_delay = &arasan_sdhci_set_tapdelay,
 702         .set_control_reg = &sdhci_set_control_reg,
 703 };
 704 #endif
 705
 706 static int arasan_sdhci_probe(struct udevice *dev)
 707 {
 708         struct arasan_sdhci_plat *plat = dev_get_plat(dev);
 709         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 710         struct arasan_sdhci_priv *priv = dev_get_priv(dev);
 711         struct sdhci_host *host;
 712         struct clk clk;
 713         unsigned long clock;
 714         int ret;
 715
 716         host = priv->host;
 717
 718         ret = clk_get_by_index(dev, 0, &clk);
 719         if (ret < 0) {
 720                 dev_err(dev, "failed to get clock\n");
 721                 return ret;
 722         }
 723
 724         clock = clk_get_rate(&clk);
 725         if (IS_ERR_VALUE(clock)) {
 726                 dev_err(dev, "failed to get rate\n");
 727                 return clock;
 728         }
 729
 730         debug("%s: CLK %ld\n", __func__, clock);
 731
 732         ret = clk_enable(&clk);
 733         if (ret) {
 734                 dev_err(dev, "failed to enable clock\n");
 735                 return ret;
 736         }
 737
 738         host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
 739                        SDHCI_QUIRK_BROKEN_R1B;
 740
 741 #ifdef CONFIG_ZYNQ_HISPD_BROKEN
 742         host->quirks |= SDHCI_QUIRK_BROKEN_HISPD_MODE;
 743 #endif
 744
 745         if (priv->no_1p8)
 746                 host->quirks |= SDHCI_QUIRK_NO_1_8_V;
 747
 748         plat->cfg.f_max = CONFIG_ZYNQ_SDHCI_MAX_FREQ;
 749
 750         ret = mmc_of_parse(dev, &plat->cfg);
 751         if (ret)
 752                 return ret;
 753
 754         host->max_clk = clock;
 755
 756         host->mmc = &plat->mmc;
 757         host->mmc->dev = dev;
 758         host->mmc->priv = host;
 759
 760         ret = sdhci_setup_cfg(&plat->cfg, host, plat->cfg.f_max,
 761                               CONFIG_ZYNQ_SDHCI_MIN_FREQ);
 762         if (ret)
 763                 return ret;
 764         upriv->mmc = host->mmc;
 765
 766         /*
 767          * WORKAROUND: Versal platforms have an issue with card detect state.
 768          * Due to this, host controller is switching off voltage to sd card
 769          * causing sd card timeout error. Workaround this by adding a wait for
 770          * 1000msec till the card detect state gets stable.
 771          */
 772         if (IS_ENABLED(CONFIG_ARCH_VERSAL)) {
 773                 u32 timeout = 1000;
 774
 775                 while (((sdhci_readl(host, SDHCI_PRESENT_STATE) &
 776                          SDHCI_CARD_STATE_STABLE) == 0) && timeout--) {
 777                         mdelay(1);
 778                 }
 779                 if (!timeout) {
 780                         dev_err(dev, "Sdhci card detect state not stable\n");
 781                         return -ETIMEDOUT;
 782                 }
 783         }
 784
 785         return sdhci_probe(dev);
 786 }
 787
 788 static int arasan_sdhci_of_to_plat(struct udevice *dev)
 789 {
 790         struct arasan_sdhci_priv *priv = dev_get_priv(dev);
 791
 792         priv->host = calloc(1, sizeof(struct sdhci_host));
 793         if (!priv->host)
 794                 return -1;
 795
 796         priv->host->name = dev->name;
 797
 798 #if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL)
 799         priv->host->ops = &arasan_ops;
 800         arasan_dt_parse_clk_phases(dev);
 801 #endif
 802
 803         priv->host->ioaddr = (void *)dev_read_addr(dev);
 804         if (IS_ERR(priv->host->ioaddr))
 805                 return PTR_ERR(priv->host->ioaddr);
 806
 807         priv->deviceid = dev_read_u32_default(dev, "xlnx,device_id", -1);
 808         priv->bank = dev_read_u32_default(dev, "xlnx,mio-bank", 0);
 809         priv->no_1p8 = dev_read_bool(dev, "no-1-8-v");
 810
 811         return 0;
 812 }
 813
 814 static int arasan_sdhci_bind(struct udevice *dev)
 815 {
 816         struct arasan_sdhci_plat *plat = dev_get_plat(dev);
 817
 818         return sdhci_bind(dev, &plat->mmc, &plat->cfg);
 819 }
 820
 821 static const struct udevice_id arasan_sdhci_ids[] = {
 822         { .compatible = "arasan,sdhci-8.9a" },
 823         { }
 824 };
 825
 826 U_BOOT_DRIVER(arasan_sdhci_drv) = {
 827         .name           = "arasan_sdhci",
 828         .id             = UCLASS_MMC,
 829         .of_match       = arasan_sdhci_ids,
 830         .of_to_plat = arasan_sdhci_of_to_plat,
 831         .ops            = &sdhci_ops,
 832         .bind           = arasan_sdhci_bind,
 833         .probe          = arasan_sdhci_probe,
 834         .priv_auto      = sizeof(struct arasan_sdhci_priv),
 835         .plat_auto      = sizeof(struct arasan_sdhci_plat),
 836 };