drivers/mmc/tegra_mmc.c

   1 /*
   2  * (C) Copyright 2009 SAMSUNG Electronics
   3  * Minkyu Kang <[email protected]>
   4  * Jaehoon Chung <[email protected]>
   5  * Portions Copyright 2011-2013 NVIDIA Corporation
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <bouncebuf.h>
  11 #include <common.h>
  12 #include <asm/gpio.h>
  13 #include <asm/io.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/arch-tegra/clk_rst.h>
  16 #include <asm/arch-tegra/tegra_mmc.h>
  17 #include <mmc.h>
  18
  19 DECLARE_GLOBAL_DATA_PTR;
  20
  21 struct mmc mmc_dev[MAX_HOSTS];
  22 struct mmc_host mmc_host[MAX_HOSTS];
  23
  24 #ifndef CONFIG_OF_CONTROL
  25 #error "Please enable device tree support to use this driver"
  26 #endif
  27
  28 static void mmc_set_power(struct mmc_host *host, unsigned short power)
  29 {
  30         u8 pwr = 0;
  31         debug("%s: power = %x\n", __func__, power);
  32
  33         if (power != (unsigned short)-1) {
  34                 switch (1 << power) {
  35                 case MMC_VDD_165_195:
  36                         pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V1_8;
  37                         break;
  38                 case MMC_VDD_29_30:
  39                 case MMC_VDD_30_31:
  40                         pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_0;
  41                         break;
  42                 case MMC_VDD_32_33:
  43                 case MMC_VDD_33_34:
  44                         pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_3;
  45                         break;
  46                 }
  47         }
  48         debug("%s: pwr = %X\n", __func__, pwr);
  49
  50         /* Set the bus voltage first (if any) */
  51         writeb(pwr, &host->reg->pwrcon);
  52         if (pwr == 0)
  53                 return;
  54
  55         /* Now enable bus power */
  56         pwr |= TEGRA_MMC_PWRCTL_SD_BUS_POWER;
  57         writeb(pwr, &host->reg->pwrcon);
  58 }
  59
  60 static void mmc_prepare_data(struct mmc_host *host, struct mmc_data *data,
  61                                 struct bounce_buffer *bbstate)
  62 {
  63         unsigned char ctrl;
  64
  65
  66         debug("buf: %p (%p), data->blocks: %u, data->blocksize: %u\n",
  67                 bbstate->bounce_buffer, bbstate->user_buffer, data->blocks,
  68                 data->blocksize);
  69
  70         writel((u32)bbstate->bounce_buffer, &host->reg->sysad);
  71         /*
  72          * DMASEL[4:3]
  73          * 00 = Selects SDMA
  74          * 01 = Reserved
  75          * 10 = Selects 32-bit Address ADMA2
  76          * 11 = Selects 64-bit Address ADMA2
  77          */
  78         ctrl = readb(&host->reg->hostctl);
  79         ctrl &= ~TEGRA_MMC_HOSTCTL_DMASEL_MASK;
  80         ctrl |= TEGRA_MMC_HOSTCTL_DMASEL_SDMA;
  81         writeb(ctrl, &host->reg->hostctl);
  82
  83         /* We do not handle DMA boundaries, so set it to max (512 KiB) */
  84         writew((7 << 12) | (data->blocksize & 0xFFF), &host->reg->blksize);
  85         writew(data->blocks, &host->reg->blkcnt);
  86 }
  87
  88 static void mmc_set_transfer_mode(struct mmc_host *host, struct mmc_data *data)
  89 {
  90         unsigned short mode;
  91         debug(" mmc_set_transfer_mode called\n");
  92         /*
  93          * TRNMOD
  94          * MUL1SIN0[5]  : Multi/Single Block Select
  95          * RD1WT0[4]    : Data Transfer Direction Select
  96          *      1 = read
  97          *      0 = write
  98          * ENACMD12[2]  : Auto CMD12 Enable
  99          * ENBLKCNT[1]  : Block Count Enable
 100          * ENDMA[0]     : DMA Enable
 101          */
 102         mode = (TEGRA_MMC_TRNMOD_DMA_ENABLE |
 103                 TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE);
 104
 105         if (data->blocks > 1)
 106                 mode |= TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT;
 107
 108         if (data->flags & MMC_DATA_READ)
 109                 mode |= TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ;
 110
 111         writew(mode, &host->reg->trnmod);
 112 }
 113
 114 static int mmc_wait_inhibit(struct mmc_host *host,
 115                             struct mmc_cmd *cmd,
 116                             struct mmc_data *data,
 117                             unsigned int timeout)
 118 {
 119         /*
 120          * PRNSTS
 121          * CMDINHDAT[1] : Command Inhibit (DAT)
 122          * CMDINHCMD[0] : Command Inhibit (CMD)
 123          */
 124         unsigned int mask = TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD;
 125
 126         /*
 127          * We shouldn't wait for data inhibit for stop commands, even
 128          * though they might use busy signaling
 129          */
 130         if ((data == NULL) && (cmd->resp_type & MMC_RSP_BUSY))
 131                 mask |= TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT;
 132
 133         while (readl(&host->reg->prnsts) & mask) {
 134                 if (timeout == 0) {
 135                         printf("%s: timeout error\n", __func__);
 136                         return -1;
 137                 }
 138                 timeout--;
 139                 udelay(1000);
 140         }
 141
 142         return 0;
 143 }
 144
 145 static int mmc_send_cmd_bounced(struct mmc *mmc, struct mmc_cmd *cmd,
 146                         struct mmc_data *data, struct bounce_buffer *bbstate)
 147 {
 148         struct mmc_host *host = (struct mmc_host *)mmc->priv;
 149         int flags, i;
 150         int result;
 151         unsigned int mask = 0;
 152         unsigned int retry = 0x100000;
 153         debug(" mmc_send_cmd called\n");
 154
 155         result = mmc_wait_inhibit(host, cmd, data, 10 /* ms */);
 156
 157         if (result < 0)
 158                 return result;
 159
 160         if (data)
 161                 mmc_prepare_data(host, data, bbstate);
 162
 163         debug("cmd->arg: %08x\n", cmd->cmdarg);
 164         writel(cmd->cmdarg, &host->reg->argument);
 165
 166         if (data)
 167                 mmc_set_transfer_mode(host, data);
 168
 169         if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
 170                 return -1;
 171
 172         /*
 173          * CMDREG
 174          * CMDIDX[13:8] : Command index
 175          * DATAPRNT[5]  : Data Present Select
 176          * ENCMDIDX[4]  : Command Index Check Enable
 177          * ENCMDCRC[3]  : Command CRC Check Enable
 178          * RSPTYP[1:0]
 179          *      00 = No Response
 180          *      01 = Length 136
 181          *      10 = Length 48
 182          *      11 = Length 48 Check busy after response
 183          */
 184         if (!(cmd->resp_type & MMC_RSP_PRESENT))
 185                 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE;
 186         else if (cmd->resp_type & MMC_RSP_136)
 187                 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136;
 188         else if (cmd->resp_type & MMC_RSP_BUSY)
 189                 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY;
 190         else
 191                 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48;
 192
 193         if (cmd->resp_type & MMC_RSP_CRC)
 194                 flags |= TEGRA_MMC_TRNMOD_CMD_CRC_CHECK;
 195         if (cmd->resp_type & MMC_RSP_OPCODE)
 196                 flags |= TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK;
 197         if (data)
 198                 flags |= TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER;
 199
 200         debug("cmd: %d\n", cmd->cmdidx);
 201
 202         writew((cmd->cmdidx << 8) | flags, &host->reg->cmdreg);
 203
 204         for (i = 0; i < retry; i++) {
 205                 mask = readl(&host->reg->norintsts);
 206                 /* Command Complete */
 207                 if (mask & TEGRA_MMC_NORINTSTS_CMD_COMPLETE) {
 208                         if (!data)
 209                                 writel(mask, &host->reg->norintsts);
 210                         break;
 211                 }
 212         }
 213
 214         if (i == retry) {
 215                 printf("%s: waiting for status update\n", __func__);
 216                 writel(mask, &host->reg->norintsts);
 217                 return TIMEOUT;
 218         }
 219
 220         if (mask & TEGRA_MMC_NORINTSTS_CMD_TIMEOUT) {
 221                 /* Timeout Error */
 222                 debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx);
 223                 writel(mask, &host->reg->norintsts);
 224                 return TIMEOUT;
 225         } else if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
 226                 /* Error Interrupt */
 227                 debug("error: %08x cmd %d\n", mask, cmd->cmdidx);
 228                 writel(mask, &host->reg->norintsts);
 229                 return -1;
 230         }
 231
 232         if (cmd->resp_type & MMC_RSP_PRESENT) {
 233                 if (cmd->resp_type & MMC_RSP_136) {
 234                         /* CRC is stripped so we need to do some shifting. */
 235                         for (i = 0; i < 4; i++) {
 236                                 unsigned int offset =
 237                                         (unsigned int)(&host->reg->rspreg3 - i);
 238                                 cmd->response[i] = readl(offset) << 8;
 239
 240                                 if (i != 3) {
 241                                         cmd->response[i] |=
 242                                                 readb(offset - 1);
 243                                 }
 244                                 debug("cmd->resp[%d]: %08x\n",
 245                                                 i, cmd->response[i]);
 246                         }
 247                 } else if (cmd->resp_type & MMC_RSP_BUSY) {
 248                         for (i = 0; i < retry; i++) {
 249                                 /* PRNTDATA[23:20] : DAT[3:0] Line Signal */
 250                                 if (readl(&host->reg->prnsts)
 251                                         & (1 << 20))    /* DAT[0] */
 252                                         break;
 253                         }
 254
 255                         if (i == retry) {
 256                                 printf("%s: card is still busy\n", __func__);
 257                                 writel(mask, &host->reg->norintsts);
 258                                 return TIMEOUT;
 259                         }
 260
 261                         cmd->response[0] = readl(&host->reg->rspreg0);
 262                         debug("cmd->resp[0]: %08x\n", cmd->response[0]);
 263                 } else {
 264                         cmd->response[0] = readl(&host->reg->rspreg0);
 265                         debug("cmd->resp[0]: %08x\n", cmd->response[0]);
 266                 }
 267         }
 268
 269         if (data) {
 270                 unsigned long   start = get_timer(0);
 271
 272                 while (1) {
 273                         mask = readl(&host->reg->norintsts);
 274
 275                         if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
 276                                 /* Error Interrupt */
 277                                 writel(mask, &host->reg->norintsts);
 278                                 printf("%s: error during transfer: 0x%08x\n",
 279                                                 __func__, mask);
 280                                 return -1;
 281                         } else if (mask & TEGRA_MMC_NORINTSTS_DMA_INTERRUPT) {
 282                                 /*
 283                                  * DMA Interrupt, restart the transfer where
 284                                  * it was interrupted.
 285                                  */
 286                                 unsigned int address = readl(&host->reg->sysad);
 287
 288                                 debug("DMA end\n");
 289                                 writel(TEGRA_MMC_NORINTSTS_DMA_INTERRUPT,
 290                                        &host->reg->norintsts);
 291                                 writel(address, &host->reg->sysad);
 292                         } else if (mask & TEGRA_MMC_NORINTSTS_XFER_COMPLETE) {
 293                                 /* Transfer Complete */
 294                                 debug("r/w is done\n");
 295                                 break;
 296                         } else if (get_timer(start) > 2000UL) {
 297                                 writel(mask, &host->reg->norintsts);
 298                                 printf("%s: MMC Timeout\n"
 299                                        "    Interrupt status        0x%08x\n"
 300                                        "    Interrupt status enable 0x%08x\n"
 301                                        "    Interrupt signal enable 0x%08x\n"
 302                                        "    Present status          0x%08x\n",
 303                                        __func__, mask,
 304                                        readl(&host->reg->norintstsen),
 305                                        readl(&host->reg->norintsigen),
 306                                        readl(&host->reg->prnsts));
 307                                 return -1;
 308                         }
 309                 }
 310                 writel(mask, &host->reg->norintsts);
 311         }
 312
 313         udelay(1000);
 314         return 0;
 315 }
 316
 317 static int tegra_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 318                         struct mmc_data *data)
 319 {
 320         void *buf;
 321         unsigned int bbflags;
 322         size_t len;
 323         struct bounce_buffer bbstate;
 324         int ret;
 325
 326         if (data) {
 327                 if (data->flags & MMC_DATA_READ) {
 328                         buf = data->dest;
 329                         bbflags = GEN_BB_WRITE;
 330                 } else {
 331                         buf = (void *)data->src;
 332                         bbflags = GEN_BB_READ;
 333                 }
 334                 len = data->blocks * data->blocksize;
 335
 336                 bounce_buffer_start(&bbstate, buf, len, bbflags);
 337         }
 338
 339         ret = mmc_send_cmd_bounced(mmc, cmd, data, &bbstate);
 340
 341         if (data)
 342                 bounce_buffer_stop(&bbstate);
 343
 344         return ret;
 345 }
 346
 347 static void mmc_change_clock(struct mmc_host *host, uint clock)
 348 {
 349         int div;
 350         unsigned short clk;
 351         unsigned long timeout;
 352
 353         debug(" mmc_change_clock called\n");
 354
 355         /*
 356          * Change Tegra SDMMCx clock divisor here. Source is PLLP_OUT0
 357          */
 358         if (clock == 0)
 359                 goto out;
 360         clock_adjust_periph_pll_div(host->mmc_id, CLOCK_ID_PERIPH, clock,
 361                                     &div);
 362         debug("div = %d\n", div);
 363
 364         writew(0, &host->reg->clkcon);
 365
 366         /*
 367          * CLKCON
 368          * SELFREQ[15:8]        : base clock divided by value
 369          * ENSDCLK[2]           : SD Clock Enable
 370          * STBLINTCLK[1]        : Internal Clock Stable
 371          * ENINTCLK[0]          : Internal Clock Enable
 372          */
 373         div >>= 1;
 374         clk = ((div << TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT) |
 375                TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE);
 376         writew(clk, &host->reg->clkcon);
 377
 378         /* Wait max 10 ms */
 379         timeout = 10;
 380         while (!(readw(&host->reg->clkcon) &
 381                  TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE)) {
 382                 if (timeout == 0) {
 383                         printf("%s: timeout error\n", __func__);
 384                         return;
 385                 }
 386                 timeout--;
 387                 udelay(1000);
 388         }
 389
 390         clk |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
 391         writew(clk, &host->reg->clkcon);
 392
 393         debug("mmc_change_clock: clkcon = %08X\n", clk);
 394
 395 out:
 396         host->clock = clock;
 397 }
 398
 399 static void tegra_mmc_set_ios(struct mmc *mmc)
 400 {
 401         struct mmc_host *host = mmc->priv;
 402         unsigned char ctrl;
 403         debug(" mmc_set_ios called\n");
 404
 405         debug("bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock);
 406
 407         /* Change clock first */
 408         mmc_change_clock(host, mmc->clock);
 409
 410         ctrl = readb(&host->reg->hostctl);
 411
 412         /*
 413          * WIDE8[5]
 414          * 0 = Depend on WIDE4
 415          * 1 = 8-bit mode
 416          * WIDE4[1]
 417          * 1 = 4-bit mode
 418          * 0 = 1-bit mode
 419          */
 420         if (mmc->bus_width == 8)
 421                 ctrl |= (1 << 5);
 422         else if (mmc->bus_width == 4)
 423                 ctrl |= (1 << 1);
 424         else
 425                 ctrl &= ~(1 << 1);
 426
 427         writeb(ctrl, &host->reg->hostctl);
 428         debug("mmc_set_ios: hostctl = %08X\n", ctrl);
 429 }
 430
 431 static void mmc_reset(struct mmc_host *host, struct mmc *mmc)
 432 {
 433         unsigned int timeout;
 434         debug(" mmc_reset called\n");
 435
 436         /*
 437          * RSTALL[0] : Software reset for all
 438          * 1 = reset
 439          * 0 = work
 440          */
 441         writeb(TEGRA_MMC_SWRST_SW_RESET_FOR_ALL, &host->reg->swrst);
 442
 443         host->clock = 0;
 444
 445         /* Wait max 100 ms */
 446         timeout = 100;
 447
 448         /* hw clears the bit when it's done */
 449         while (readb(&host->reg->swrst) & TEGRA_MMC_SWRST_SW_RESET_FOR_ALL) {
 450                 if (timeout == 0) {
 451                         printf("%s: timeout error\n", __func__);
 452                         return;
 453                 }
 454                 timeout--;
 455                 udelay(1000);
 456         }
 457
 458         /* Set SD bus voltage & enable bus power */
 459         mmc_set_power(host, fls(mmc->voltages) - 1);
 460         debug("%s: power control = %02X, host control = %02X\n", __func__,
 461                 readb(&host->reg->pwrcon), readb(&host->reg->hostctl));
 462
 463         /* Make sure SDIO pads are set up */
 464         pad_init_mmc(host);
 465 }
 466
 467 static int tegra_mmc_core_init(struct mmc *mmc)
 468 {
 469         struct mmc_host *host = (struct mmc_host *)mmc->priv;
 470         unsigned int mask;
 471         debug(" mmc_core_init called\n");
 472
 473         mmc_reset(host, mmc);
 474
 475         host->version = readw(&host->reg->hcver);
 476         debug("host version = %x\n", host->version);
 477
 478         /* mask all */
 479         writel(0xffffffff, &host->reg->norintstsen);
 480         writel(0xffffffff, &host->reg->norintsigen);
 481
 482         writeb(0xe, &host->reg->timeoutcon);    /* TMCLK * 2^27 */
 483         /*
 484          * NORMAL Interrupt Status Enable Register init
 485          * [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable
 486          * [4] ENSTABUFWTRDY : Buffer write Ready Status Enable
 487          * [3] ENSTADMAINT   : DMA boundary interrupt
 488          * [1] ENSTASTANSCMPLT : Transfre Complete Status Enable
 489          * [0] ENSTACMDCMPLT : Command Complete Status Enable
 490         */
 491         mask = readl(&host->reg->norintstsen);
 492         mask &= ~(0xffff);
 493         mask |= (TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE |
 494                  TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE |
 495                  TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT |
 496                  TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY |
 497                  TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY);
 498         writel(mask, &host->reg->norintstsen);
 499
 500         /*
 501          * NORMAL Interrupt Signal Enable Register init
 502          * [1] ENSTACMDCMPLT : Transfer Complete Signal Enable
 503          */
 504         mask = readl(&host->reg->norintsigen);
 505         mask &= ~(0xffff);
 506         mask |= TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE;
 507         writel(mask, &host->reg->norintsigen);
 508
 509         return 0;
 510 }
 511
 512 int tegra_mmc_getcd(struct mmc *mmc)
 513 {
 514         struct mmc_host *host = (struct mmc_host *)mmc->priv;
 515
 516         debug("tegra_mmc_getcd called\n");
 517
 518         if (fdt_gpio_isvalid(&host->cd_gpio))
 519                 return fdtdec_get_gpio(&host->cd_gpio);
 520
 521         return 1;
 522 }
 523
 524 static const struct mmc_ops tegra_mmc_ops = {
 525         .send_cmd       = tegra_mmc_send_cmd,
 526         .set_ios        = tegra_mmc_set_ios,
 527         .init           = tegra_mmc_core_init,
 528         .getcd          = tegra_mmc_getcd,
 529 };
 530
 531 static int do_mmc_init(int dev_index)
 532 {
 533         struct mmc_host *host;
 534         char gpusage[12]; /* "SD/MMCn PWR" or "SD/MMCn CD" */
 535         struct mmc *mmc;
 536
 537         /* DT should have been read & host config filled in */
 538         host = &mmc_host[dev_index];
 539         if (!host->enabled)
 540                 return -1;
 541
 542         debug(" do_mmc_init: index %d, bus width %d "
 543                 "pwr_gpio %d cd_gpio %d\n",
 544                 dev_index, host->width,
 545                 host->pwr_gpio.gpio, host->cd_gpio.gpio);
 546
 547         host->clock = 0;
 548         clock_start_periph_pll(host->mmc_id, CLOCK_ID_PERIPH, 20000000);
 549
 550         if (fdt_gpio_isvalid(&host->pwr_gpio)) {
 551                 sprintf(gpusage, "SD/MMC%d PWR", dev_index);
 552                 gpio_request(host->pwr_gpio.gpio, gpusage);
 553                 gpio_direction_output(host->pwr_gpio.gpio, 1);
 554                 debug(" Power GPIO name = %s\n", host->pwr_gpio.name);
 555         }
 556
 557         if (fdt_gpio_isvalid(&host->cd_gpio)) {
 558                 sprintf(gpusage, "SD/MMC%d CD", dev_index);
 559                 gpio_request(host->cd_gpio.gpio, gpusage);
 560                 gpio_direction_input(host->cd_gpio.gpio);
 561                 debug(" CD GPIO name = %s\n", host->cd_gpio.name);
 562         }
 563
 564         mmc = &mmc_dev[dev_index];
 565
 566         sprintf(mmc->name, "Tegra SD/MMC");
 567         mmc->priv = host;
 568         mmc->ops = &tegra_mmc_ops;
 569
 570         mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
 571         mmc->host_caps = 0;
 572         if (host->width == 8)
 573                 mmc->host_caps |= MMC_MODE_8BIT;
 574         if (host->width >= 4)
 575                 mmc->host_caps |= MMC_MODE_4BIT;
 576         mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_HC;
 577
 578         /*
 579          * min freq is for card identification, and is the highest
 580          *  low-speed SDIO card frequency (actually 400KHz)
 581          * max freq is highest HS eMMC clock as per the SD/MMC spec
 582          *  (actually 52MHz)
 583          */
 584         mmc->f_min = 375000;
 585         mmc->f_max = 48000000;
 586
 587         mmc_register(mmc);
 588
 589         return 0;
 590 }
 591
 592 /**
 593  * Get the host address and peripheral ID for a node.
 594  *
 595  * @param blob          fdt blob
 596  * @param node          Device index (0-3)
 597  * @param host          Structure to fill in (reg, width, mmc_id)
 598  */
 599 static int mmc_get_config(const void *blob, int node, struct mmc_host *host)
 600 {
 601         debug("%s: node = %d\n", __func__, node);
 602
 603         host->enabled = fdtdec_get_is_enabled(blob, node);
 604
 605         host->reg = (struct tegra_mmc *)fdtdec_get_addr(blob, node, "reg");
 606         if ((fdt_addr_t)host->reg == FDT_ADDR_T_NONE) {
 607                 debug("%s: no sdmmc base reg info found\n", __func__);
 608                 return -FDT_ERR_NOTFOUND;
 609         }
 610
 611         host->mmc_id = clock_decode_periph_id(blob, node);
 612         if (host->mmc_id == PERIPH_ID_NONE) {
 613                 debug("%s: could not decode periph id\n", __func__);
 614                 return -FDT_ERR_NOTFOUND;
 615         }
 616
 617         /*
 618          * NOTE: mmc->bus_width is determined by mmc.c dynamically.
 619          * TBD: Override it with this value?
 620          */
 621         host->width = fdtdec_get_int(blob, node, "bus-width", 0);
 622         if (!host->width)
 623                 debug("%s: no sdmmc width found\n", __func__);
 624
 625         /* These GPIOs are optional */
 626         fdtdec_decode_gpio(blob, node, "cd-gpios", &host->cd_gpio);
 627         fdtdec_decode_gpio(blob, node, "wp-gpios", &host->wp_gpio);
 628         fdtdec_decode_gpio(blob, node, "power-gpios", &host->pwr_gpio);
 629
 630         debug("%s: found controller at %p, width = %d, periph_id = %d\n",
 631                 __func__, host->reg, host->width, host->mmc_id);
 632         return 0;
 633 }
 634
 635 /*
 636  * Process a list of nodes, adding them to our list of SDMMC ports.
 637  *
 638  * @param blob          fdt blob
 639  * @param node_list     list of nodes to process (any <=0 are ignored)
 640  * @param count         number of nodes to process
 641  * @return 0 if ok, -1 on error
 642  */
 643 static int process_nodes(const void *blob, int node_list[], int count)
 644 {
 645         struct mmc_host *host;
 646         int i, node;
 647
 648         debug("%s: count = %d\n", __func__, count);
 649
 650         /* build mmc_host[] for each controller */
 651         for (i = 0; i < count; i++) {
 652                 node = node_list[i];
 653                 if (node <= 0)
 654                         continue;
 655
 656                 host = &mmc_host[i];
 657                 host->id = i;
 658
 659                 if (mmc_get_config(blob, node, host)) {
 660                         printf("%s: failed to decode dev %d\n", __func__, i);
 661                         return -1;
 662                 }
 663                 do_mmc_init(i);
 664         }
 665         return 0;
 666 }
 667
 668 void tegra_mmc_init(void)
 669 {
 670         int node_list[MAX_HOSTS], count;
 671         const void *blob = gd->fdt_blob;
 672         debug("%s entry\n", __func__);
 673
 674         /* See if any Tegra124 MMC controllers are present */
 675         count = fdtdec_find_aliases_for_id(blob, "sdhci",
 676                 COMPAT_NVIDIA_TEGRA124_SDMMC, node_list, MAX_HOSTS);
 677         debug("%s: count of Tegra124 sdhci nodes is %d\n", __func__, count);
 678         if (process_nodes(blob, node_list, count)) {
 679                 printf("%s: Error processing T30 mmc node(s)!\n", __func__);
 680                 return;
 681         }
 682
 683         /* See if any Tegra30 MMC controllers are present */
 684         count = fdtdec_find_aliases_for_id(blob, "sdhci",
 685                 COMPAT_NVIDIA_TEGRA30_SDMMC, node_list, MAX_HOSTS);
 686         debug("%s: count of T30 sdhci nodes is %d\n", __func__, count);
 687         if (process_nodes(blob, node_list, count)) {
 688                 printf("%s: Error processing T30 mmc node(s)!\n", __func__);
 689                 return;
 690         }
 691
 692         /* Now look for any Tegra20 MMC controllers */
 693         count = fdtdec_find_aliases_for_id(blob, "sdhci",
 694                 COMPAT_NVIDIA_TEGRA20_SDMMC, node_list, MAX_HOSTS);
 695         debug("%s: count of T20 sdhci nodes is %d\n", __func__, count);
 696         if (process_nodes(blob, node_list, count)) {
 697                 printf("%s: Error processing T20 mmc node(s)!\n", __func__);
 698                 return;
 699         }
 700 }