board/dhelectronics/dh_imx6/dh_imx6_spl.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * DHCOM DH-iMX6 PDK SPL support
   4  *
   5  * Copyright (C) 2017 Marek Vasut <[email protected]>
   6  */
   7
   8 #include <common.h>
   9 #include <cpu_func.h>
  10 #include <init.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/crm_regs.h>
  13 #include <asm/arch/imx-regs.h>
  14 #include <asm/arch/iomux.h>
  15 #include <asm/arch/mx6-ddr.h>
  16 #include <asm/arch/mx6-pins.h>
  17 #include <asm/arch/sys_proto.h>
  18 #include <asm/cache.h>
  19 #include <asm/gpio.h>
  20 #include <asm/mach-imx/boot_mode.h>
  21 #include <asm/mach-imx/iomux-v3.h>
  22 #include <asm/mach-imx/mxc_i2c.h>
  23 #include <asm/io.h>
  24 #include <asm/system.h>
  25 #include <errno.h>
  26 #include <fuse.h>
  27 #include <fsl_esdhc_imx.h>
  28 #include <i2c.h>
  29 #include <mmc.h>
  30 #include <spl.h>
  31 #include <linux/delay.h>
  32
  33 #define ENET_PAD_CTRL                                                   \
  34         (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |  \
  35          PAD_CTL_HYS)
  36
  37 #define GPIO_PAD_CTRL                                                   \
  38         (PAD_CTL_HYS | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
  39
  40 #define SPI_PAD_CTRL                                                    \
  41         (PAD_CTL_HYS | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |          \
  42         PAD_CTL_SRE_FAST)
  43
  44 #define UART_PAD_CTRL                                                   \
  45         (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |  \
  46          PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  47
  48 #define USDHC_PAD_CTRL                                                  \
  49         (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |   \
  50          PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  51
  52 static const struct mx6dq_iomux_ddr_regs dhcom6dq_ddr_ioregs = {
  53         .dram_sdclk_0   = 0x00020030,
  54         .dram_sdclk_1   = 0x00020030,
  55         .dram_cas       = 0x00020030,
  56         .dram_ras       = 0x00020030,
  57         .dram_reset     = 0x00020030,
  58         .dram_sdcke0    = 0x00003000,
  59         .dram_sdcke1    = 0x00003000,
  60         .dram_sdba2     = 0x00000000,
  61         .dram_sdodt0    = 0x00003030,
  62         .dram_sdodt1    = 0x00003030,
  63         .dram_sdqs0     = 0x00000030,
  64         .dram_sdqs1     = 0x00000030,
  65         .dram_sdqs2     = 0x00000030,
  66         .dram_sdqs3     = 0x00000030,
  67         .dram_sdqs4     = 0x00000030,
  68         .dram_sdqs5     = 0x00000030,
  69         .dram_sdqs6     = 0x00000030,
  70         .dram_sdqs7     = 0x00000030,
  71         .dram_dqm0      = 0x00020030,
  72         .dram_dqm1      = 0x00020030,
  73         .dram_dqm2      = 0x00020030,
  74         .dram_dqm3      = 0x00020030,
  75         .dram_dqm4      = 0x00020030,
  76         .dram_dqm5      = 0x00020030,
  77         .dram_dqm6      = 0x00020030,
  78         .dram_dqm7      = 0x00020030,
  79 };
  80
  81 static const struct mx6dq_iomux_grp_regs dhcom6dq_grp_ioregs = {
  82         .grp_ddr_type   = 0x000C0000,
  83         .grp_ddrmode_ctl = 0x00020000,
  84         .grp_ddrpke     = 0x00000000,
  85         .grp_addds      = 0x00000030,
  86         .grp_ctlds      = 0x00000030,
  87         .grp_ddrmode    = 0x00020000,
  88         .grp_b0ds       = 0x00000030,
  89         .grp_b1ds       = 0x00000030,
  90         .grp_b2ds       = 0x00000030,
  91         .grp_b3ds       = 0x00000030,
  92         .grp_b4ds       = 0x00000030,
  93         .grp_b5ds       = 0x00000030,
  94         .grp_b6ds       = 0x00000030,
  95         .grp_b7ds       = 0x00000030,
  96 };
  97
  98 static const struct mx6sdl_iomux_ddr_regs dhcom6sdl_ddr_ioregs = {
  99         .dram_sdclk_0   = 0x00020030,
 100         .dram_sdclk_1   = 0x00020030,
 101         .dram_cas       = 0x00020030,
 102         .dram_ras       = 0x00020030,
 103         .dram_reset     = 0x00020030,
 104         .dram_sdcke0    = 0x00003000,
 105         .dram_sdcke1    = 0x00003000,
 106         .dram_sdba2     = 0x00000000,
 107         .dram_sdodt0    = 0x00003030,
 108         .dram_sdodt1    = 0x00003030,
 109         .dram_sdqs0     = 0x00000030,
 110         .dram_sdqs1     = 0x00000030,
 111         .dram_sdqs2     = 0x00000030,
 112         .dram_sdqs3     = 0x00000030,
 113         .dram_sdqs4     = 0x00000030,
 114         .dram_sdqs5     = 0x00000030,
 115         .dram_sdqs6     = 0x00000030,
 116         .dram_sdqs7     = 0x00000030,
 117         .dram_dqm0      = 0x00020030,
 118         .dram_dqm1      = 0x00020030,
 119         .dram_dqm2      = 0x00020030,
 120         .dram_dqm3      = 0x00020030,
 121         .dram_dqm4      = 0x00020030,
 122         .dram_dqm5      = 0x00020030,
 123         .dram_dqm6      = 0x00020030,
 124         .dram_dqm7      = 0x00020030,
 125 };
 126
 127 static const struct mx6sdl_iomux_grp_regs dhcom6sdl_grp_ioregs = {
 128         .grp_ddr_type   = 0x000C0000,
 129         .grp_ddrmode_ctl = 0x00020000,
 130         .grp_ddrpke     = 0x00000000,
 131         .grp_addds      = 0x00000030,
 132         .grp_ctlds      = 0x00000030,
 133         .grp_ddrmode    = 0x00020000,
 134         .grp_b0ds       = 0x00000030,
 135         .grp_b1ds       = 0x00000030,
 136         .grp_b2ds       = 0x00000030,
 137         .grp_b3ds       = 0x00000030,
 138         .grp_b4ds       = 0x00000030,
 139         .grp_b5ds       = 0x00000030,
 140         .grp_b6ds       = 0x00000030,
 141         .grp_b7ds       = 0x00000030,
 142 };
 143
 144 static const struct mx6_mmdc_calibration dhcom_mmdc_calib_4x4g_1066 = {
 145         .p0_mpwldectrl0 = 0x00150019,
 146         .p0_mpwldectrl1 = 0x001C000B,
 147         .p1_mpwldectrl0 = 0x00020018,
 148         .p1_mpwldectrl1 = 0x0002000C,
 149         .p0_mpdgctrl0   = 0x43140320,
 150         .p0_mpdgctrl1   = 0x03080304,
 151         .p1_mpdgctrl0   = 0x43180320,
 152         .p1_mpdgctrl1   = 0x03100254,
 153         .p0_mprddlctl   = 0x4830383C,
 154         .p1_mprddlctl   = 0x3836323E,
 155         .p0_mpwrdlctl   = 0x3E444642,
 156         .p1_mpwrdlctl   = 0x42344442,
 157 };
 158
 159 static const struct mx6_mmdc_calibration dhcom_mmdc_calib_2x4g_800 = {
 160         .p0_mpwldectrl0 = 0x0040003C,
 161         .p0_mpwldectrl1 = 0x0032003E,
 162         .p0_mpdgctrl0   = 0x42350231,
 163         .p0_mpdgctrl1   = 0x021A0218,
 164         .p0_mprddlctl   = 0x4B4B4E49,
 165         .p0_mpwrdlctl   = 0x3F3F3035,
 166 };
 167
 168 static const struct mx6_mmdc_calibration dhcom_mmdc_calib_4x2g_1066 = {
 169         .p0_mpwldectrl0 = 0x001a001a,
 170         .p0_mpwldectrl1 = 0x00260015,
 171         .p0_mpdgctrl0   = 0x030c0320,
 172         .p0_mpdgctrl1   = 0x03100304,
 173         .p0_mprddlctl   = 0x432e3538,
 174         .p0_mpwrdlctl   = 0x363f423d,
 175         .p1_mpwldectrl0 = 0x0006001e,
 176         .p1_mpwldectrl1 = 0x00050015,
 177         .p1_mpdgctrl0   = 0x031c0324,
 178         .p1_mpdgctrl1   = 0x030c0258,
 179         .p1_mprddlctl   = 0x3834313f,
 180         .p1_mpwrdlctl   = 0x47374a42,
 181 };
 182
 183 static const struct mx6_mmdc_calibration dhcom_mmdc_calib_4x2g_800 = {
 184         .p0_mpwldectrl0 = 0x003A003A,
 185         .p0_mpwldectrl1 = 0x0030002F,
 186         .p1_mpwldectrl0 = 0x002F0038,
 187         .p1_mpwldectrl1 = 0x00270039,
 188         .p0_mpdgctrl0   = 0x420F020F,
 189         .p0_mpdgctrl1   = 0x01760175,
 190         .p1_mpdgctrl0   = 0x41640171,
 191         .p1_mpdgctrl1   = 0x015E0160,
 192         .p0_mprddlctl   = 0x45464B4A,
 193         .p1_mprddlctl   = 0x49484A46,
 194         .p0_mpwrdlctl   = 0x40402E32,
 195         .p1_mpwrdlctl   = 0x3A3A3231,
 196 };
 197
 198 static const struct mx6_mmdc_calibration dhcom_mmdc_calib_2x2g_800 = {
 199         .p0_mpwldectrl0 = 0x0040003C,
 200         .p0_mpwldectrl1 = 0x0032003E,
 201         .p0_mpdgctrl0   = 0x42350231,
 202         .p0_mpdgctrl1   = 0x021A0218,
 203         .p0_mprddlctl   = 0x4B4B4E49,
 204         .p0_mpwrdlctl   = 0x3F3F3035,
 205 };
 206
 207 /*
 208  * 2 Gbit DDR3 memory
 209  *   - NANYA #NT5CC128M16IP-DII
 210  *   - NANYA #NT5CB128M16FP-DII
 211  */
 212 static const struct mx6_ddr3_cfg dhcom_mem_ddr_2g = {
 213         .mem_speed      = 1600,
 214         .density        = 2,
 215         .width          = 16,
 216         .banks          = 8,
 217         .rowaddr        = 14,
 218         .coladdr        = 10,
 219         .pagesz         = 2,
 220         .trcd           = 1375,
 221         .trcmin         = 5863,
 222         .trasmin        = 3750,
 223 };
 224
 225 /*
 226  * 4 Gbit DDR3 memory
 227  *   - Intelligent Memory #IM4G16D3EABG-125I
 228  */
 229 static const struct mx6_ddr3_cfg dhcom_mem_ddr_4g = {
 230         .mem_speed      = 1600,
 231         .density        = 4,
 232         .width          = 16,
 233         .banks          = 8,
 234         .rowaddr        = 15,
 235         .coladdr        = 10,
 236         .pagesz         = 2,
 237         .trcd           = 1375,
 238         .trcmin         = 4875,
 239         .trasmin        = 3500,
 240 };
 241
 242 /* DDR3 64bit */
 243 static const struct mx6_ddr_sysinfo dhcom_ddr_64bit = {
 244         /* width of data bus:0=16,1=32,2=64 */
 245         .dsize          = 2,
 246         .cs_density     = 32,
 247         .ncs            = 1,    /* single chip select */
 248         .cs1_mirror     = 1,
 249         .rtt_wr         = 1,    /* DDR3_RTT_60_OHM, RTT_Wr = RZQ/4 */
 250         .rtt_nom        = 1,    /* DDR3_RTT_60_OHM, RTT_Nom = RZQ/4 */
 251         .walat          = 1,    /* Write additional latency */
 252         .ralat          = 5,    /* Read additional latency */
 253         .mif3_mode      = 3,    /* Command prediction working mode */
 254         .bi_on          = 1,    /* Bank interleaving enabled */
 255         .sde_to_rst     = 0x10, /* 14 cycles, 200us (JEDEC default) */
 256         .rst_to_cke     = 0x23, /* 33 cycles, 500us (JEDEC default) */
 257         .refsel         = 1,    /* Refresh cycles at 32KHz */
 258         .refr           = 3,    /* 4 refresh commands per refresh cycle */
 259 };
 260
 261 /* DDR3 32bit */
 262 static const struct mx6_ddr_sysinfo dhcom_ddr_32bit = {
 263         /* width of data bus:0=16,1=32,2=64 */
 264         .dsize          = 1,
 265         .cs_density     = 32,
 266         .ncs            = 1,    /* single chip select */
 267         .cs1_mirror     = 1,
 268         .rtt_wr         = 1,    /* DDR3_RTT_60_OHM, RTT_Wr = RZQ/4 */
 269         .rtt_nom        = 1,    /* DDR3_RTT_60_OHM, RTT_Nom = RZQ/4 */
 270         .walat          = 1,    /* Write additional latency */
 271         .ralat          = 5,    /* Read additional latency */
 272         .mif3_mode      = 3,    /* Command prediction working mode */
 273         .bi_on          = 1,    /* Bank interleaving enabled */
 274         .sde_to_rst     = 0x10, /* 14 cycles, 200us (JEDEC default) */
 275         .rst_to_cke     = 0x23, /* 33 cycles, 500us (JEDEC default) */
 276         .refsel         = 1,    /* Refresh cycles at 32KHz */
 277         .refr           = 3,    /* 4 refresh commands per refresh cycle */
 278 };
 279
 280 static void ccgr_init(void)
 281 {
 282         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 283
 284         writel(0x00C03F3F, &ccm->CCGR0);
 285         writel(0x0030FC03, &ccm->CCGR1);
 286         writel(0x0FFFC000, &ccm->CCGR2);
 287         writel(0x3FF00000, &ccm->CCGR3);
 288         writel(0x00FFF300, &ccm->CCGR4);
 289         writel(0x0F0000C3, &ccm->CCGR5);
 290         writel(0x000003FF, &ccm->CCGR6);
 291 }
 292
 293 /* Board ID */
 294 static iomux_v3_cfg_t const hwcode_pads[] = {
 295         IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19      | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 296         IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06      | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 297         IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16      | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 298 };
 299
 300 static void setup_iomux_boardid(void)
 301 {
 302         /* HW code pins: Setup alternate function and configure pads */
 303         SETUP_IOMUX_PADS(hwcode_pads);
 304 }
 305
 306 /* DDR Code */
 307 static iomux_v3_cfg_t const ddrcode_pads[] = {
 308         IOMUX_PADS(PAD_EIM_A16__GPIO2_IO22      | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 309         IOMUX_PADS(PAD_EIM_A17__GPIO2_IO21      | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 310 };
 311
 312 static void setup_iomux_ddrcode(void)
 313 {
 314         /* ddr code pins */
 315         SETUP_IOMUX_PADS(ddrcode_pads);
 316 }
 317
 318 enum dhcom_ddr3_code {
 319         DH_DDR3_SIZE_256MIB = 0x00,
 320         DH_DDR3_SIZE_512MIB = 0x01,
 321         DH_DDR3_SIZE_1GIB   = 0x02,
 322         DH_DDR3_SIZE_2GIB   = 0x03
 323 };
 324
 325 #define DDR3_CODE_BIT_0   IMX_GPIO_NR(2, 22)
 326 #define DDR3_CODE_BIT_1   IMX_GPIO_NR(2, 21)
 327
 328 enum dhcom_ddr3_code dhcom_get_ddr3_code(void)
 329 {
 330         enum dhcom_ddr3_code ddr3_code;
 331
 332         gpio_request(DDR3_CODE_BIT_0, "DDR3_CODE_BIT_0");
 333         gpio_request(DDR3_CODE_BIT_1, "DDR3_CODE_BIT_1");
 334
 335         gpio_direction_input(DDR3_CODE_BIT_0);
 336         gpio_direction_input(DDR3_CODE_BIT_1);
 337
 338         /* 256MB = 0b00; 512MB = 0b01; 1GB = 0b10; 2GB = 0b11 */
 339         ddr3_code = (!!gpio_get_value(DDR3_CODE_BIT_1) << 1)
 340              | (!!gpio_get_value(DDR3_CODE_BIT_0));
 341
 342         return ddr3_code;
 343 }
 344
 345 /* GPIO */
 346 static iomux_v3_cfg_t const gpio_pads[] = {
 347         IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02       | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 348         IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04       | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 349         IOMUX_PADS(PAD_GPIO_5__GPIO1_IO05       | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 350         IOMUX_PADS(PAD_CSI0_DAT17__GPIO6_IO03   | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 351         IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05      | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 352         IOMUX_PADS(PAD_DI0_PIN4__GPIO4_IO20     | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 353         IOMUX_PADS(PAD_EIM_D27__GPIO3_IO27      | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 354         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07     | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 355         IOMUX_PADS(PAD_KEY_COL1__GPIO4_IO08     | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 356         IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14    | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 357         IOMUX_PADS(PAD_NANDF_CS2__GPIO6_IO15    | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 358         IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09     | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 359         IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00     | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 360         IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01     | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 361         IOMUX_PADS(PAD_CSI0_VSYNC__GPIO5_IO21   | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 362         IOMUX_PADS(PAD_GPIO_18__GPIO7_IO13      | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 363         IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18      | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 364         IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16     | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 365         IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17     | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 366         IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19     | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 367         IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20      | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 368         IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18  | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 369         IOMUX_PADS(PAD_CSI0_MCLK__GPIO5_IO19    | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 370 };
 371
 372 static void setup_iomux_gpio(void)
 373 {
 374         SETUP_IOMUX_PADS(gpio_pads);
 375 }
 376
 377 /* Ethernet */
 378 static iomux_v3_cfg_t const enet_pads[] = {
 379         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 380         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC       | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 381         IOMUX_PADS(PAD_ENET_TX_EN__ENET_TX_EN   | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 382         IOMUX_PADS(PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 383         IOMUX_PADS(PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 384         IOMUX_PADS(PAD_GPIO_16__ENET_REF_CLK    | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 385         IOMUX_PADS(PAD_ENET_RX_ER__ENET_RX_ER   | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 386         IOMUX_PADS(PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 387         IOMUX_PADS(PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 388         IOMUX_PADS(PAD_ENET_CRS_DV__ENET_RX_EN  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 389         /* SMSC PHY Reset */
 390         IOMUX_PADS(PAD_EIM_WAIT__GPIO5_IO00     | MUX_PAD_CTRL(NO_PAD_CTRL)),
 391         /* ENET_VIO_GPIO */
 392         IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07       | MUX_PAD_CTRL(NO_PAD_CTRL)),
 393         /* ENET_Interrupt - (not used) */
 394         IOMUX_PADS(PAD_RGMII_RD0__GPIO6_IO25    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 395 };
 396
 397 static void setup_iomux_enet(void)
 398 {
 399         SETUP_IOMUX_PADS(enet_pads);
 400 }
 401
 402 /* SD interface */
 403 static iomux_v3_cfg_t const usdhc2_pads[] = {
 404         IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 405         IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 406         IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 407         IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 408         IOMUX_PADS(PAD_SD2_CLK__SD2_CLK         | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 409         IOMUX_PADS(PAD_SD2_CMD__SD2_CMD         | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 410         IOMUX_PADS(PAD_NANDF_CS3__GPIO6_IO16    | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
 411 };
 412
 413 /* onboard microSD */
 414 static iomux_v3_cfg_t const usdhc3_pads[] = {
 415         IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 416         IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 417         IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 418         IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 419         IOMUX_PADS(PAD_SD3_CLK__SD3_CLK         | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 420         IOMUX_PADS(PAD_SD3_CMD__SD3_CMD         | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 421         IOMUX_PADS(PAD_SD3_RST__GPIO7_IO08      | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
 422 };
 423
 424 /* eMMC */
 425 static iomux_v3_cfg_t const usdhc4_pads[] = {
 426         IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 427         IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 428         IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 429         IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 430         IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 431         IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 432         IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 433         IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 434         IOMUX_PADS(PAD_SD4_CLK__SD4_CLK         | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 435         IOMUX_PADS(PAD_SD4_CMD__SD4_CMD         | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 436 };
 437
 438 /* SD */
 439 static void setup_iomux_sd(void)
 440 {
 441         SETUP_IOMUX_PADS(usdhc2_pads);
 442         SETUP_IOMUX_PADS(usdhc3_pads);
 443         SETUP_IOMUX_PADS(usdhc4_pads);
 444 }
 445
 446 /* SPI */
 447 static iomux_v3_cfg_t const ecspi1_pads[] = {
 448         /* SS0 - SS of boot flash */
 449         IOMUX_PADS(PAD_EIM_EB2__GPIO2_IO30      |
 450                 MUX_PAD_CTRL(SPI_PAD_CTRL | PAD_CTL_PUS_100K_UP)),
 451         /* SS2 - SS of DHCOM SPI1 */
 452         IOMUX_PADS(PAD_KEY_ROW2__GPIO4_IO11     |
 453                 MUX_PAD_CTRL(SPI_PAD_CTRL | PAD_CTL_PUS_100K_UP)),
 454
 455         IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO     | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 456         IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI     | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 457         IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK     | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 458 };
 459
 460 static void setup_iomux_spi(void)
 461 {
 462         SETUP_IOMUX_PADS(ecspi1_pads);
 463 }
 464
 465 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 466 {
 467         if (bus == 0 && cs == 0)
 468                 return IMX_GPIO_NR(2, 30);
 469         else
 470                 return -1;
 471 }
 472
 473 /* UART */
 474 static iomux_v3_cfg_t const uart1_pads[] = {
 475         IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA  | MUX_PAD_CTRL(UART_PAD_CTRL)),
 476         IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA  | MUX_PAD_CTRL(UART_PAD_CTRL)),
 477 };
 478
 479 static void setup_iomux_uart(void)
 480 {
 481         SETUP_IOMUX_PADS(uart1_pads);
 482 }
 483
 484 #ifdef CONFIG_FSL_USDHC
 485 struct fsl_esdhc_cfg usdhc_cfg[1] = {
 486         {USDHC4_BASE_ADDR},
 487 };
 488
 489 int board_mmc_get_env_dev(int devno)
 490 {
 491         return devno - 1;
 492 }
 493
 494 int board_mmc_getcd(struct mmc *mmc)
 495 {
 496         return 1; /* eMMC/uSDHC4 is always present */
 497 }
 498
 499 int board_mmc_init(struct bd_info *bis)
 500 {
 501         SETUP_IOMUX_PADS(usdhc4_pads);
 502         usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
 503         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 504         usdhc_cfg[0].max_bus_width = 8;
 505
 506         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 507 }
 508 #endif
 509
 510 /* USB */
 511 static iomux_v3_cfg_t const usb_pads[] = {
 512         IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID       | MUX_PAD_CTRL(NO_PAD_CTRL)),
 513         IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31      | MUX_PAD_CTRL(NO_PAD_CTRL)),
 514 };
 515
 516 static void setup_iomux_usb(void)
 517 {
 518         SETUP_IOMUX_PADS(usb_pads);
 519 }
 520
 521 /* Perform DDR DRAM calibration */
 522 static int spl_dram_perform_cal(struct mx6_ddr_sysinfo const *sysinfo)
 523 {
 524         int ret = 0;
 525
 526 #ifdef CONFIG_MX6_DDRCAL
 527         udelay(100);
 528         ret = mmdc_do_write_level_calibration(sysinfo);
 529         if (ret) {
 530                 printf("DDR3: Write level calibration error [%d]\n", ret);
 531                 return ret;
 532         }
 533
 534         ret = mmdc_do_dqs_calibration(sysinfo);
 535         if (ret) {
 536                 printf("DDR3: DQS calibration error [%d]\n", ret);
 537                 return ret;
 538         }
 539 #endif /* CONFIG_MX6_DDRCAL */
 540
 541         return ret;
 542 }
 543
 544
 545 /* DRAM */
 546 static void dhcom_spl_dram_init(void)
 547 {
 548         enum dhcom_ddr3_code ddr3_code = dhcom_get_ddr3_code();
 549
 550         if (is_mx6dq()) {
 551                 mx6dq_dram_iocfg(64, &dhcom6dq_ddr_ioregs,
 552                                         &dhcom6dq_grp_ioregs);
 553                 switch (ddr3_code) {
 554                 default:
 555                         printf("imx6qd: unsupported ddr3 code %d\n", ddr3_code);
 556                         printf("        choosing 1024 MB\n");
 557                         /* fall through */
 558                 case DH_DDR3_SIZE_1GIB:
 559                         mx6_dram_cfg(&dhcom_ddr_64bit,
 560                                      &dhcom_mmdc_calib_4x2g_1066,
 561                                      &dhcom_mem_ddr_2g);
 562                         break;
 563                 case DH_DDR3_SIZE_2GIB:
 564                         mx6_dram_cfg(&dhcom_ddr_64bit,
 565                                      &dhcom_mmdc_calib_4x4g_1066,
 566                                      &dhcom_mem_ddr_4g);
 567                         break;
 568                 }
 569
 570                 /* Perform DDR DRAM calibration */
 571                 spl_dram_perform_cal(&dhcom_ddr_64bit);
 572
 573         } else if (is_cpu_type(MXC_CPU_MX6DL)) {
 574                 mx6sdl_dram_iocfg(64, &dhcom6sdl_ddr_ioregs,
 575                                           &dhcom6sdl_grp_ioregs);
 576                 switch (ddr3_code) {
 577                 default:
 578                         printf("imx6dl: unsupported ddr3 code %d\n", ddr3_code);
 579                         printf("        choosing 1024 MB\n");
 580                         /* fall through */
 581                 case DH_DDR3_SIZE_1GIB:
 582                         mx6_dram_cfg(&dhcom_ddr_64bit,
 583                                      &dhcom_mmdc_calib_4x2g_800,
 584                                      &dhcom_mem_ddr_2g);
 585                         break;
 586                 }
 587
 588                 /* Perform DDR DRAM calibration */
 589                 spl_dram_perform_cal(&dhcom_ddr_64bit);
 590
 591         } else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
 592                 mx6sdl_dram_iocfg(32, &dhcom6sdl_ddr_ioregs,
 593                                           &dhcom6sdl_grp_ioregs);
 594                 switch (ddr3_code) {
 595                 default:
 596                         printf("imx6s: unsupported ddr3 code %d\n", ddr3_code);
 597                         printf("       choosing 512 MB\n");
 598                         /* fall through */
 599                 case DH_DDR3_SIZE_512MIB:
 600                         mx6_dram_cfg(&dhcom_ddr_32bit,
 601                                      &dhcom_mmdc_calib_2x2g_800,
 602                                      &dhcom_mem_ddr_2g);
 603                         break;
 604                 case DH_DDR3_SIZE_1GIB:
 605                         mx6_dram_cfg(&dhcom_ddr_32bit,
 606                                      &dhcom_mmdc_calib_2x4g_800,
 607                                      &dhcom_mem_ddr_4g);
 608                         break;
 609                 }
 610
 611                 /* Perform DDR DRAM calibration */
 612                 spl_dram_perform_cal(&dhcom_ddr_32bit);
 613         }
 614 }
 615
 616 void dram_bank_mmu_setup(int bank)
 617 {
 618         int i;
 619
 620         set_section_dcache(ROMCP_ARB_BASE_ADDR >> MMU_SECTION_SHIFT, DCACHE_DEFAULT_OPTION);
 621         set_section_dcache(IRAM_BASE_ADDR >> MMU_SECTION_SHIFT, DCACHE_DEFAULT_OPTION);
 622
 623         for (i = MMDC0_ARB_BASE_ADDR >> MMU_SECTION_SHIFT;
 624                         i < ((MMDC0_ARB_BASE_ADDR >> MMU_SECTION_SHIFT) +
 625                         (SZ_1G >> MMU_SECTION_SHIFT));
 626                         i++)
 627                 set_section_dcache(i, DCACHE_DEFAULT_OPTION);
 628 }
 629
 630 void board_init_f(ulong dummy)
 631 {
 632         /* setup AIPS and disable watchdog */
 633         arch_cpu_init();
 634
 635         ccgr_init();
 636         gpr_init();
 637
 638         /* setup GP timer */
 639         timer_init();
 640
 641         setup_iomux_boardid();
 642         setup_iomux_ddrcode();
 643         setup_iomux_gpio();
 644         setup_iomux_enet();
 645         setup_iomux_sd();
 646         setup_iomux_spi();
 647         setup_iomux_uart();
 648         setup_iomux_usb();
 649
 650         /* UART clocks enabled and gd valid - init serial console */
 651         preloader_console_init();
 652
 653         /* DDR3 initialization */
 654         dhcom_spl_dram_init();
 655
 656         /* Set up early MMU tables at the beginning of DRAM and start d-cache */
 657         gd->arch.tlb_addr = MMDC0_ARB_BASE_ADDR + SZ_32M;
 658         gd->arch.tlb_size = PGTABLE_SIZE;
 659         enable_caches();
 660
 661         /* Clear the BSS. */
 662         memset(__bss_start, 0, __bss_end - __bss_start);
 663
 664         /* load/boot image from boot device */
 665         board_init_r(NULL, 0);
 666 }
 667
 668 void spl_board_prepare_for_boot(void)
 669 {
 670         /*
 671          * Flush and disable dcache. Without it, the following bootstage might fail randomly because
 672          * dirty cache lines may not have been written back to DRAM.
 673          *
 674          * If dcache_disable() would be omitted, the following scenario may occur:
 675          *
 676          * The SPL enables dcache and cachelines get populated with data. Then dcache gets disabled
 677          * in U-Boot proper, but still contains dirty data, i.e. the corresponding DRAM locations
 678          * have not yet been updated. When U-Boot reads these locations, it sees an (incorrect) old
 679          * state of the content.
 680          *
 681          * Furthermore, the DRAM contents have likely been modified by U-Boot while dcache was
 682          * disabled. Thus, U-Boot flushing dcache would corrupt DRAM with stale data.
 683          */
 684         dcache_disable(); /* implies flush_dcache_all() */
 685 }