include/configs/at91sam9m10g45ek.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2007-2008
   4  * Stelian Pop <[email protected]>
   5  * Lead Tech Design <www.leadtechdesign.com>
   6  *
   7  * Configuation settings for the AT91SAM9M10G45EK board(and AT91SAM9G45EKES).
   8  */
   9
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 /* ARM asynchronous clock */
  14 #define CFG_SYS_AT91_SLOW_CLOCK      32768
  15 #define CFG_SYS_AT91_MAIN_CLOCK      12000000 /* from 12 MHz crystal */
  16
  17 /* SDRAM */
  18 #define CFG_SYS_SDRAM_BASE           0x70000000
  19 #define CFG_SYS_SDRAM_SIZE              0x08000000
  20
  21 /* NAND flash */
  22 #ifdef CONFIG_CMD_NAND
  23 #define CFG_SYS_NAND_BASE                       ATMEL_BASE_CS3
  24 /* our ALE is AD21 */
  25 #define CFG_SYS_NAND_MASK_ALE           (1 << 21)
  26 /* our CLE is AD22 */
  27 #define CFG_SYS_NAND_MASK_CLE           (1 << 22)
  28 #define CFG_SYS_NAND_ENABLE_PIN         AT91_PIN_PC14
  29 #define CFG_SYS_NAND_READY_PIN          AT91_PIN_PC8
  30
  31 #endif
  32
  33 #ifdef CONFIG_SD_BOOT
  34 #elif CONFIG_NAND_BOOT
  35 #define CFG_SYS_NAND_U_BOOT_SIZE        0x80000
  36
  37 #define CFG_SYS_NAND_ECCSIZE            256
  38 #define CFG_SYS_NAND_ECCBYTES   3
  39 #define CFG_SYS_NAND_ECCPOS             { 40, 41, 42, 43, 44, 45, 46, 47, \
  40                                           48, 49, 50, 51, 52, 53, 54, 55, \
  41                                           56, 57, 58, 59, 60, 61, 62, 63, }
  42 #endif
  43
  44 #define CFG_SYS_MASTER_CLOCK            132096000
  45 #define CFG_SYS_AT91_PLLA               0x20c73f03
  46 #define CFG_SYS_MCKR                    0x1301
  47 #define CFG_SYS_MCKR_CSS                0x1302
  48
  49 #endif