drivers/mmc/sdhci.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2011, Marvell Semiconductor Inc.
   4  * Lei Wen <[email protected]>
   5  *
   6  * Back ported to the 8xx platform (from the 8260 platform) by
   7  * [email protected], 27-Jan-01.
   8  */
   9
  10 #include <cpu_func.h>
  11 #include <dm.h>
  12 #include <errno.h>
  13 #include <log.h>
  14 #include <malloc.h>
  15 #include <mmc.h>
  16 #include <sdhci.h>
  17 #include <time.h>
  18 #include <asm/cache.h>
  19 #include <linux/bitops.h>
  20 #include <linux/delay.h>
  21 #include <linux/dma-mapping.h>
  22 #include <linux/printk.h>
  23 #include <phys2bus.h>
  24 #include <power/regulator.h>
  25
  26 static void sdhci_reset(struct sdhci_host *host, u8 mask)
  27 {
  28         unsigned long timeout;
  29
  30         /* Wait max 100 ms */
  31         timeout = 100;
  32         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
  33         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
  34                 if (timeout == 0) {
  35                         log_warning("Reset %#x never completed\n", mask);
  36                         return;
  37                 }
  38                 timeout--;
  39                 udelay(1000);
  40         }
  41 }
  42
  43 static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
  44 {
  45         int i;
  46         if (cmd->resp_type & MMC_RSP_136) {
  47                 /* CRC is stripped so we need to do some shifting. */
  48                 for (i = 0; i < 4; i++) {
  49                         cmd->response[i] = sdhci_readl(host,
  50                                         SDHCI_RESPONSE + (3-i)*4) << 8;
  51                         if (i != 3)
  52                                 cmd->response[i] |= sdhci_readb(host,
  53                                                 SDHCI_RESPONSE + (3-i)*4-1);
  54                 }
  55         } else {
  56                 cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
  57         }
  58 }
  59
  60 static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
  61 {
  62         int i;
  63         char *offs;
  64         for (i = 0; i < data->blocksize; i += 4) {
  65                 offs = data->dest + i;
  66                 if (data->flags == MMC_DATA_READ)
  67                         *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
  68                 else
  69                         sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
  70         }
  71 }
  72
  73 #if (CONFIG_IS_ENABLED(MMC_SDHCI_SDMA) || CONFIG_IS_ENABLED(MMC_SDHCI_ADMA))
  74 static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
  75                               int *is_aligned, int trans_bytes)
  76 {
  77         dma_addr_t dma_addr;
  78         unsigned char ctrl;
  79         void *buf;
  80
  81         if (data->flags == MMC_DATA_READ)
  82                 buf = data->dest;
  83         else
  84                 buf = (void *)data->src;
  85
  86         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
  87         ctrl &= ~SDHCI_CTRL_DMA_MASK;
  88         if (host->flags & USE_ADMA64)
  89                 ctrl |= SDHCI_CTRL_ADMA64;
  90         else if (host->flags & USE_ADMA)
  91                 ctrl |= SDHCI_CTRL_ADMA32;
  92         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
  93
  94         if (host->flags & USE_SDMA &&
  95             (host->force_align_buffer ||
  96              (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR &&
  97               ((unsigned long)buf & 0x7) != 0x0))) {
  98                 *is_aligned = 0;
  99                 if (data->flags != MMC_DATA_READ)
 100                         memcpy(host->align_buffer, buf, trans_bytes);
 101                 buf = host->align_buffer;
 102         }
 103
 104         host->start_addr = dma_map_single(buf, trans_bytes,
 105                                           mmc_get_dma_dir(data));
 106
 107         if (host->flags & USE_SDMA) {
 108                 dma_addr = dev_phys_to_bus(mmc_to_dev(host->mmc), host->start_addr);
 109                 sdhci_writel(host, dma_addr, SDHCI_DMA_ADDRESS);
 110         }
 111 #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
 112         else if (host->flags & (USE_ADMA | USE_ADMA64)) {
 113                 sdhci_prepare_adma_table(host, host->adma_desc_table, data,
 114                                          host->start_addr);
 115
 116                 sdhci_writel(host, lower_32_bits(host->adma_addr),
 117                              SDHCI_ADMA_ADDRESS);
 118                 if (host->flags & USE_ADMA64)
 119                         sdhci_writel(host, upper_32_bits(host->adma_addr),
 120                                      SDHCI_ADMA_ADDRESS_HI);
 121         }
 122 #endif
 123 }
 124 #else
 125 static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
 126                               int *is_aligned, int trans_bytes)
 127 {}
 128 #endif
 129 static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data)
 130 {
 131         dma_addr_t start_addr = host->start_addr;
 132         unsigned int stat, rdy, mask, timeout, block = 0;
 133         bool transfer_done = false;
 134
 135         timeout = 1000000;
 136         rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
 137         mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
 138         do {
 139                 stat = sdhci_readl(host, SDHCI_INT_STATUS);
 140                 if (stat & SDHCI_INT_ERROR) {
 141                         log_debug("Error detected in status(%#x)!\n", stat);
 142                         return -EIO;
 143                 }
 144                 if (!transfer_done && (stat & rdy)) {
 145                         if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
 146                                 continue;
 147                         sdhci_writel(host, rdy, SDHCI_INT_STATUS);
 148                         sdhci_transfer_pio(host, data);
 149                         data->dest += data->blocksize;
 150                         if (++block >= data->blocks) {
 151                                 /* Keep looping until the SDHCI_INT_DATA_END is
 152                                  * cleared, even if we finished sending all the
 153                                  * blocks.
 154                                  */
 155                                 transfer_done = true;
 156                                 continue;
 157                         }
 158                 }
 159                 if ((host->flags & USE_DMA) && !transfer_done &&
 160                     (stat & SDHCI_INT_DMA_END)) {
 161                         sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
 162                         if (host->flags & USE_SDMA) {
 163                                 start_addr &=
 164                                 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
 165                                 start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
 166                                 start_addr = dev_phys_to_bus(mmc_to_dev(host->mmc),
 167                                                              start_addr);
 168                                 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
 169                         }
 170                 }
 171                 if (timeout-- > 0)
 172                         udelay(10);
 173                 else {
 174                         log_err("Transfer data timeout\n");
 175                         return -ETIMEDOUT;
 176                 }
 177         } while (!(stat & SDHCI_INT_DATA_END));
 178
 179 #if (CONFIG_IS_ENABLED(MMC_SDHCI_SDMA) || CONFIG_IS_ENABLED(MMC_SDHCI_ADMA))
 180         dma_unmap_single(host->start_addr, data->blocks * data->blocksize,
 181                          mmc_get_dma_dir(data));
 182 #endif
 183
 184         return 0;
 185 }
 186
 187 /*
 188  * No command will be sent by driver if card is busy, so driver must wait
 189  * for card ready state.
 190  * Every time when card is busy after timeout then (last) timeout value will be
 191  * increased twice but only if it doesn't exceed global defined maximum.
 192  * Each function call will use last timeout value.
 193  */
 194 #define SDHCI_CMD_MAX_TIMEOUT                   3200
 195 #define SDHCI_CMD_DEFAULT_TIMEOUT               100
 196 #define SDHCI_READ_STATUS_TIMEOUT               1000
 197
 198 #ifdef CONFIG_DM_MMC
 199 static int sdhci_send_command(struct udevice *dev, struct mmc_cmd *cmd,
 200                               struct mmc_data *data)
 201 {
 202         struct mmc *mmc = mmc_get_mmc_dev(dev);
 203
 204 #else
 205 static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
 206                               struct mmc_data *data)
 207 {
 208 #endif
 209         struct sdhci_host *host = mmc->priv;
 210         unsigned int stat = 0;
 211         int ret = 0;
 212         int trans_bytes = 0, is_aligned = 1;
 213         u32 mask, flags, mode = 0;
 214         unsigned int time = 0;
 215         int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
 216         ulong start = get_timer(0);
 217
 218         host->start_addr = 0;
 219         /* Timeout unit - ms */
 220         static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT;
 221
 222         mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
 223
 224         /* We shouldn't wait for data inihibit for stop commands, even
 225            though they might use busy signaling */
 226         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION ||
 227             ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
 228               cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data))
 229                 mask &= ~SDHCI_DATA_INHIBIT;
 230
 231         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 232                 if (time >= cmd_timeout) {
 233                         log_warning("mmc%d busy ", mmc_dev);
 234                         if (2 * cmd_timeout <= SDHCI_CMD_MAX_TIMEOUT) {
 235                                 cmd_timeout += cmd_timeout;
 236                                 log_warning("timeout increasing to: %u ms\n",
 237                                             cmd_timeout);
 238                         } else {
 239                                 log_warning("timeout\n");
 240                                 return -ECOMM;
 241                         }
 242                 }
 243                 time++;
 244                 udelay(1000);
 245         }
 246
 247         sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
 248
 249         mask = SDHCI_INT_RESPONSE;
 250         if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
 251              cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data)
 252                 mask = SDHCI_INT_DATA_AVAIL;
 253
 254         if (!(cmd->resp_type & MMC_RSP_PRESENT))
 255                 flags = SDHCI_CMD_RESP_NONE;
 256         else if (cmd->resp_type & MMC_RSP_136)
 257                 flags = SDHCI_CMD_RESP_LONG;
 258         else if (cmd->resp_type & MMC_RSP_BUSY) {
 259                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
 260                 mask |= SDHCI_INT_DATA_END;
 261         } else
 262                 flags = SDHCI_CMD_RESP_SHORT;
 263
 264         if (cmd->resp_type & MMC_RSP_CRC)
 265                 flags |= SDHCI_CMD_CRC;
 266         if (cmd->resp_type & MMC_RSP_OPCODE)
 267                 flags |= SDHCI_CMD_INDEX;
 268         if (data || cmd->cmdidx ==  MMC_CMD_SEND_TUNING_BLOCK ||
 269             cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
 270                 flags |= SDHCI_CMD_DATA;
 271
 272         /* Set Transfer mode regarding to data flag */
 273         if (data) {
 274                 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
 275
 276                 if (!(host->quirks & SDHCI_QUIRK_SUPPORT_SINGLE))
 277                         mode = SDHCI_TRNS_BLK_CNT_EN;
 278                 trans_bytes = data->blocks * data->blocksize;
 279                 if (data->blocks > 1)
 280                         mode |= SDHCI_TRNS_MULTI | SDHCI_TRNS_BLK_CNT_EN;
 281
 282                 if (data->flags == MMC_DATA_READ)
 283                         mode |= SDHCI_TRNS_READ;
 284
 285                 if (host->flags & USE_DMA) {
 286                         mode |= SDHCI_TRNS_DMA;
 287                         sdhci_prepare_dma(host, data, &is_aligned, trans_bytes);
 288                 }
 289
 290                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
 291                                 data->blocksize),
 292                                 SDHCI_BLOCK_SIZE);
 293                 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
 294                 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
 295         } else if (cmd->resp_type & MMC_RSP_BUSY) {
 296                 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
 297         }
 298
 299         sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
 300         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
 301         start = get_timer(0);
 302         do {
 303                 stat = sdhci_readl(host, SDHCI_INT_STATUS);
 304                 if (stat & SDHCI_INT_ERROR)
 305                         break;
 306
 307                 if (host->quirks & SDHCI_QUIRK_BROKEN_R1B &&
 308                     cmd->resp_type & MMC_RSP_BUSY && !data) {
 309                         unsigned int state =
 310                                 sdhci_readl(host, SDHCI_PRESENT_STATE);
 311
 312                         if (!(state & SDHCI_DAT_ACTIVE))
 313                                 return 0;
 314                 }
 315
 316                 if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
 317                         log_warning("Timeout for status update: %08x %08x\n",
 318                                     stat, mask);
 319                         return -ETIMEDOUT;
 320                 }
 321         } while ((stat & mask) != mask);
 322
 323         if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
 324                 sdhci_cmd_done(host, cmd);
 325                 sdhci_writel(host, mask, SDHCI_INT_STATUS);
 326         } else
 327                 ret = -1;
 328
 329         if (!ret && data)
 330                 ret = sdhci_transfer_data(host, data);
 331
 332         if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
 333                 udelay(1000);
 334
 335         stat = sdhci_readl(host, SDHCI_INT_STATUS);
 336         sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
 337         if (!ret) {
 338                 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
 339                                 !is_aligned && (data->flags == MMC_DATA_READ))
 340                         memcpy(data->dest, host->align_buffer, trans_bytes);
 341                 return 0;
 342         }
 343
 344         sdhci_reset(host, SDHCI_RESET_CMD);
 345         sdhci_reset(host, SDHCI_RESET_DATA);
 346         if (stat & SDHCI_INT_TIMEOUT)
 347                 return -ETIMEDOUT;
 348         else
 349                 return -ECOMM;
 350 }
 351
 352 #if defined(CONFIG_DM_MMC) && CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING)
 353 static int sdhci_execute_tuning(struct udevice *dev, uint opcode)
 354 {
 355         int err;
 356         struct mmc *mmc = mmc_get_mmc_dev(dev);
 357         struct sdhci_host *host = mmc->priv;
 358
 359         log_debug("sdhci tuning\n");
 360
 361         if (host->ops && host->ops->platform_execute_tuning) {
 362                 err = host->ops->platform_execute_tuning(mmc, opcode);
 363                 if (err)
 364                         return err;
 365                 return 0;
 366         }
 367         return 0;
 368 }
 369 #endif
 370 int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
 371 {
 372         struct sdhci_host *host = mmc->priv;
 373         unsigned int div, clk = 0, timeout;
 374         int ret;
 375
 376         /* Wait max 20 ms */
 377         timeout = 200;
 378         while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
 379                            (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) {
 380                 if (timeout == 0) {
 381                         log_err("Timeout waiting for cmd & data inhibit\n");
 382                         return -EBUSY;
 383                 }
 384
 385                 timeout--;
 386                 udelay(100);
 387         }
 388
 389         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
 390
 391         if (clock == 0)
 392                 return 0;
 393
 394         if (host->ops && host->ops->set_delay) {
 395                 ret = host->ops->set_delay(host);
 396                 if (ret) {
 397                         log_err("Error while setting tap delay\n");
 398                         return ret;
 399                 }
 400         }
 401
 402         if (host->ops && host->ops->config_dll) {
 403                 ret = host->ops->config_dll(host, clock, false);
 404                 if (ret) {
 405                         log_err("Error configuring dll\n");
 406                         return ret;
 407                 }
 408         }
 409
 410         if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
 411                 /*
 412                  * Check if the Host Controller supports Programmable Clock
 413                  * Mode.
 414                  */
 415                 if (host->clk_mul) {
 416                         for (div = 1; div <= 1024; div++) {
 417                                 if ((host->max_clk / div) <= clock)
 418                                         break;
 419                         }
 420
 421                         /*
 422                          * Set Programmable Clock Mode in the Clock
 423                          * Control register.
 424                          */
 425                         clk = SDHCI_PROG_CLOCK_MODE;
 426                         div--;
 427                 } else {
 428                         /* Version 3.00 divisors must be a multiple of 2. */
 429                         if (host->max_clk <= clock) {
 430                                 div = 1;
 431                         } else {
 432                                 for (div = 2;
 433                                      div < SDHCI_MAX_DIV_SPEC_300;
 434                                      div += 2) {
 435                                         if ((host->max_clk / div) <= clock)
 436                                                 break;
 437                                 }
 438                         }
 439                         div >>= 1;
 440                 }
 441         } else {
 442                 /* Version 2.00 divisors must be a power of 2. */
 443                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
 444                         if ((host->max_clk / div) <= clock)
 445                                 break;
 446                 }
 447                 div >>= 1;
 448         }
 449
 450         if (host->ops && host->ops->set_clock)
 451                 host->ops->set_clock(host, div);
 452
 453         if (host->ops && host->ops->config_dll) {
 454                 ret = host->ops->config_dll(host, clock, true);
 455                 if (ret) {
 456                         log_err("Error while configuring dll\n");
 457                         return ret;
 458                 }
 459         }
 460
 461         clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
 462         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
 463                 << SDHCI_DIVIDER_HI_SHIFT;
 464         clk |= SDHCI_CLOCK_INT_EN;
 465         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 466
 467         /* Wait max 20 ms */
 468         timeout = 20;
 469         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
 470                 & SDHCI_CLOCK_INT_STABLE)) {
 471                 if (timeout == 0) {
 472                         log_err("Internal clock never stabilised.\n");
 473                         return -EBUSY;
 474                 }
 475                 timeout--;
 476                 udelay(1000);
 477         }
 478
 479         clk |= SDHCI_CLOCK_CARD_EN;
 480         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 481         return 0;
 482 }
 483
 484 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
 485 {
 486         u8 pwr = 0;
 487
 488         if (power != (unsigned short)-1) {
 489                 switch (1 << power) {
 490                 case MMC_VDD_165_195:
 491                         pwr = SDHCI_POWER_180;
 492                         break;
 493                 case MMC_VDD_29_30:
 494                 case MMC_VDD_30_31:
 495                         pwr = SDHCI_POWER_300;
 496                         break;
 497                 case MMC_VDD_32_33:
 498                 case MMC_VDD_33_34:
 499                         pwr = SDHCI_POWER_330;
 500                         break;
 501                 }
 502         }
 503
 504         if (pwr == 0) {
 505                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
 506                 return;
 507         }
 508
 509         pwr |= SDHCI_POWER_ON;
 510
 511         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
 512 }
 513
 514 void sdhci_set_uhs_timing(struct sdhci_host *host)
 515 {
 516         struct mmc *mmc = host->mmc;
 517         u32 reg;
 518
 519         reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 520         reg &= ~SDHCI_CTRL_UHS_MASK;
 521
 522         switch (mmc->selected_mode) {
 523         case UHS_SDR25:
 524         case MMC_HS:
 525                 reg |= SDHCI_CTRL_UHS_SDR25;
 526                 break;
 527         case UHS_SDR50:
 528         case MMC_HS_52:
 529                 reg |= SDHCI_CTRL_UHS_SDR50;
 530                 break;
 531         case UHS_DDR50:
 532         case MMC_DDR_52:
 533                 reg |= SDHCI_CTRL_UHS_DDR50;
 534                 break;
 535         case UHS_SDR104:
 536         case MMC_HS_200:
 537                 reg |= SDHCI_CTRL_UHS_SDR104;
 538                 break;
 539         case MMC_HS_400:
 540         case MMC_HS_400_ES:
 541                 reg |= SDHCI_CTRL_HS400;
 542                 break;
 543         default:
 544                 reg |= SDHCI_CTRL_UHS_SDR12;
 545         }
 546
 547         sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
 548 }
 549
 550 static void sdhci_set_voltage(struct sdhci_host *host)
 551 {
 552         if (IS_ENABLED(CONFIG_MMC_IO_VOLTAGE)) {
 553                 struct mmc *mmc = (struct mmc *)host->mmc;
 554                 u32 ctrl;
 555
 556                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 557
 558                 switch (mmc->signal_voltage) {
 559                 case MMC_SIGNAL_VOLTAGE_330:
 560 #if CONFIG_IS_ENABLED(DM_REGULATOR)
 561                         if (mmc->vqmmc_supply) {
 562                                 if (regulator_set_enable_if_allowed(mmc->vqmmc_supply, false)) {
 563                                         pr_err("failed to disable vqmmc-supply\n");
 564                                         return;
 565                                 }
 566
 567                                 if (regulator_set_value(mmc->vqmmc_supply, 3300000)) {
 568                                         pr_err("failed to set vqmmc-voltage to 3.3V\n");
 569                                         return;
 570                                 }
 571
 572                                 if (regulator_set_enable_if_allowed(mmc->vqmmc_supply, true)) {
 573                                         pr_err("failed to enable vqmmc-supply\n");
 574                                         return;
 575                                 }
 576                         }
 577 #endif
 578                         if (IS_SD(mmc)) {
 579                                 ctrl &= ~SDHCI_CTRL_VDD_180;
 580                                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
 581                         }
 582
 583                         /* Wait for 5ms */
 584                         mdelay(5);
 585
 586                         /* 3.3V regulator output should be stable within 5 ms */
 587                         if (IS_SD(mmc)) {
 588                                 if (ctrl & SDHCI_CTRL_VDD_180) {
 589                                         pr_err("3.3V regulator output did not become stable\n");
 590                                         return;
 591                                 }
 592                         }
 593
 594                         break;
 595                 case MMC_SIGNAL_VOLTAGE_180:
 596 #if CONFIG_IS_ENABLED(DM_REGULATOR)
 597                         if (mmc->vqmmc_supply) {
 598                                 if (regulator_set_enable_if_allowed(mmc->vqmmc_supply, false)) {
 599                                         pr_err("failed to disable vqmmc-supply\n");
 600                                         return;
 601                                 }
 602
 603                                 if (regulator_set_value(mmc->vqmmc_supply, 1800000)) {
 604                                         pr_err("failed to set vqmmc-voltage to 1.8V\n");
 605                                         return;
 606                                 }
 607
 608                                 if (regulator_set_enable_if_allowed(mmc->vqmmc_supply, true)) {
 609                                         pr_err("failed to enable vqmmc-supply\n");
 610                                         return;
 611                                 }
 612                         }
 613 #endif
 614                         if (IS_SD(mmc)) {
 615                                 ctrl |= SDHCI_CTRL_VDD_180;
 616                                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
 617                         }
 618
 619                         /* Wait for 5 ms */
 620                         mdelay(5);
 621
 622                         /* 1.8V regulator output has to be stable within 5 ms */
 623                         if (IS_SD(mmc)) {
 624                                 if (!(ctrl & SDHCI_CTRL_VDD_180)) {
 625                                         pr_err("1.8V regulator output did not become stable\n");
 626                                         return;
 627                                 }
 628                         }
 629
 630                         break;
 631                 default:
 632                         /* No signal voltage switch required */
 633                         return;
 634                 }
 635         }
 636 }
 637
 638 void sdhci_set_control_reg(struct sdhci_host *host)
 639 {
 640         sdhci_set_voltage(host);
 641         sdhci_set_uhs_timing(host);
 642 }
 643
 644 #ifdef CONFIG_DM_MMC
 645 static int sdhci_set_ios(struct udevice *dev)
 646 {
 647         struct mmc *mmc = mmc_get_mmc_dev(dev);
 648 #else
 649 static int sdhci_set_ios(struct mmc *mmc)
 650 {
 651 #endif
 652         u32 ctrl;
 653         struct sdhci_host *host = mmc->priv;
 654         bool no_hispd_bit = false;
 655
 656         if (host->ops && host->ops->set_control_reg)
 657                 host->ops->set_control_reg(host);
 658
 659         if (mmc->clock != host->clock)
 660                 sdhci_set_clock(mmc, mmc->clock);
 661
 662         if (mmc->clk_disable)
 663                 sdhci_set_clock(mmc, 0);
 664
 665         /* Set bus width */
 666         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 667         if (mmc->bus_width == 8) {
 668                 ctrl &= ~SDHCI_CTRL_4BITBUS;
 669                 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
 670                                 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
 671                         ctrl |= SDHCI_CTRL_8BITBUS;
 672         } else {
 673                 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
 674                                 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
 675                         ctrl &= ~SDHCI_CTRL_8BITBUS;
 676                 if (mmc->bus_width == 4)
 677                         ctrl |= SDHCI_CTRL_4BITBUS;
 678                 else
 679                         ctrl &= ~SDHCI_CTRL_4BITBUS;
 680         }
 681
 682         if ((host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) ||
 683             (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE)) {
 684                 ctrl &= ~SDHCI_CTRL_HISPD;
 685                 no_hispd_bit = true;
 686         }
 687
 688         if (!no_hispd_bit) {
 689                 if (mmc->selected_mode == MMC_HS ||
 690                     mmc->selected_mode == SD_HS ||
 691                     mmc->selected_mode == MMC_HS_52 ||
 692                     mmc->selected_mode == MMC_DDR_52 ||
 693                     mmc->selected_mode == MMC_HS_200 ||
 694                     mmc->selected_mode == MMC_HS_400 ||
 695                     mmc->selected_mode == MMC_HS_400_ES ||
 696                     mmc->selected_mode == UHS_SDR25 ||
 697                     mmc->selected_mode == UHS_SDR50 ||
 698                     mmc->selected_mode == UHS_SDR104 ||
 699                     mmc->selected_mode == UHS_DDR50)
 700                         ctrl |= SDHCI_CTRL_HISPD;
 701                 else
 702                         ctrl &= ~SDHCI_CTRL_HISPD;
 703         }
 704
 705         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 706
 707         /* If available, call the driver specific "post" set_ios() function */
 708         if (host->ops && host->ops->set_ios_post)
 709                 return host->ops->set_ios_post(host);
 710
 711         return 0;
 712 }
 713
 714 static int sdhci_init(struct mmc *mmc)
 715 {
 716         struct sdhci_host *host = mmc->priv;
 717 #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_GPIO)
 718         struct udevice *dev = mmc->dev;
 719
 720         gpio_request_by_name(dev, "cd-gpios", 0,
 721                              &host->cd_gpio, GPIOD_IS_IN);
 722 #endif
 723
 724         sdhci_reset(host, SDHCI_RESET_ALL);
 725
 726 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
 727         host->align_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER;
 728         /*
 729          * Always use this bounce-buffer when CONFIG_FIXED_SDHCI_ALIGNED_BUFFER
 730          * is defined.
 731          */
 732         host->force_align_buffer = true;
 733 #else
 734         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) {
 735                 host->align_buffer = memalign(8, 512 * 1024);
 736                 if (!host->align_buffer) {
 737                         log_err("Aligned buffer alloc failed\n");
 738                         return -ENOMEM;
 739                 }
 740         }
 741 #endif
 742
 743         sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);
 744
 745         if (host->ops && host->ops->get_cd)
 746                 host->ops->get_cd(host);
 747
 748         /* Enable only interrupts served by the SD controller */
 749         sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
 750                      SDHCI_INT_ENABLE);
 751         /* Mask all sdhci interrupt sources */
 752         sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
 753
 754         return 0;
 755 }
 756
 757 #ifdef CONFIG_DM_MMC
 758 int sdhci_probe(struct udevice *dev)
 759 {
 760         struct mmc *mmc = mmc_get_mmc_dev(dev);
 761
 762         return sdhci_init(mmc);
 763 }
 764
 765 static int sdhci_deferred_probe(struct udevice *dev)
 766 {
 767         int err;
 768         struct mmc *mmc = mmc_get_mmc_dev(dev);
 769         struct sdhci_host *host = mmc->priv;
 770
 771         if (host->ops && host->ops->deferred_probe) {
 772                 err = host->ops->deferred_probe(host);
 773                 if (err)
 774                         return err;
 775         }
 776         return 0;
 777 }
 778
 779 static int sdhci_get_cd(struct udevice *dev)
 780 {
 781         struct mmc *mmc = mmc_get_mmc_dev(dev);
 782         struct sdhci_host *host = mmc->priv;
 783         int value;
 784
 785         /* If nonremovable, assume that the card is always present. */
 786         if (mmc->cfg->host_caps & MMC_CAP_NONREMOVABLE)
 787                 return 1;
 788         /* If polling, assume that the card is always present. */
 789         if (mmc->cfg->host_caps & MMC_CAP_NEEDS_POLL)
 790                 return 1;
 791
 792 #if CONFIG_IS_ENABLED(DM_GPIO)
 793         value = dm_gpio_get_value(&host->cd_gpio);
 794         if (value >= 0) {
 795                 if (mmc->cfg->host_caps & MMC_CAP_CD_ACTIVE_HIGH)
 796                         return !value;
 797                 else
 798                         return value;
 799         }
 800 #endif
 801         value = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
 802                    SDHCI_CARD_PRESENT);
 803         if (mmc->cfg->host_caps & MMC_CAP_CD_ACTIVE_HIGH)
 804                 return !value;
 805         else
 806                 return value;
 807 }
 808
 809 static int sdhci_wait_dat0(struct udevice *dev, int state,
 810                            int timeout_us)
 811 {
 812         int tmp;
 813         struct mmc *mmc = mmc_get_mmc_dev(dev);
 814         struct sdhci_host *host = mmc->priv;
 815         unsigned long timeout = timer_get_us() + timeout_us;
 816
 817         // readx_poll_timeout is unsuitable because sdhci_readl accepts
 818         // two arguments
 819         do {
 820                 tmp = sdhci_readl(host, SDHCI_PRESENT_STATE);
 821                 if (!!(tmp & SDHCI_DATA_0_LVL_MASK) == !!state)
 822                         return 0;
 823         } while (!timeout_us || !time_after(timer_get_us(), timeout));
 824
 825         return -ETIMEDOUT;
 826 }
 827
 828 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
 829 static int sdhci_set_enhanced_strobe(struct udevice *dev)
 830 {
 831         struct mmc *mmc = mmc_get_mmc_dev(dev);
 832         struct sdhci_host *host = mmc->priv;
 833
 834         if (host->ops && host->ops->set_enhanced_strobe)
 835                 return host->ops->set_enhanced_strobe(host);
 836
 837         return -ENOTSUPP;
 838 }
 839 #endif
 840
 841 const struct dm_mmc_ops sdhci_ops = {
 842         .send_cmd       = sdhci_send_command,
 843         .set_ios        = sdhci_set_ios,
 844         .get_cd         = sdhci_get_cd,
 845         .deferred_probe = sdhci_deferred_probe,
 846 #if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING)
 847         .execute_tuning = sdhci_execute_tuning,
 848 #endif
 849         .wait_dat0      = sdhci_wait_dat0,
 850 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
 851         .set_enhanced_strobe = sdhci_set_enhanced_strobe,
 852 #endif
 853 };
 854 #else
 855 static const struct mmc_ops sdhci_ops = {
 856         .send_cmd       = sdhci_send_command,
 857         .set_ios        = sdhci_set_ios,
 858         .init           = sdhci_init,
 859 };
 860 #endif
 861
 862 int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
 863                 u32 f_max, u32 f_min)
 864 {
 865         u32 caps, caps_1 = 0;
 866 #if CONFIG_IS_ENABLED(DM_MMC)
 867         u64 dt_caps, dt_caps_mask;
 868
 869         dt_caps_mask = dev_read_u64_default(host->mmc->dev,
 870                                             "sdhci-caps-mask", 0);
 871         dt_caps = dev_read_u64_default(host->mmc->dev,
 872                                        "sdhci-caps", 0);
 873         caps = ~lower_32_bits(dt_caps_mask) &
 874                sdhci_readl(host, SDHCI_CAPABILITIES);
 875         caps |= lower_32_bits(dt_caps);
 876 #else
 877         caps = sdhci_readl(host, SDHCI_CAPABILITIES);
 878 #endif
 879         log_debug("caps: %#x\n", caps);
 880
 881 #if CONFIG_IS_ENABLED(MMC_SDHCI_SDMA)
 882         if ((caps & SDHCI_CAN_DO_SDMA)) {
 883                 host->flags |= USE_SDMA;
 884         } else {
 885                 log_debug("Controller doesn't support SDMA\n");
 886         }
 887 #endif
 888 #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
 889         if (!(caps & SDHCI_CAN_DO_ADMA2)) {
 890                 log_err("Controller doesn't support ADMA\n");
 891                 return -EINVAL;
 892         }
 893         if (!host->adma_desc_table) {
 894                 host->adma_desc_table = sdhci_adma_init();
 895                 host->adma_addr = virt_to_phys(host->adma_desc_table);
 896         }
 897
 898         if (IS_ENABLED(CONFIG_MMC_SDHCI_ADMA_64BIT))
 899                 host->flags |= USE_ADMA64;
 900         else
 901                 host->flags |= USE_ADMA;
 902 #endif
 903         if (host->quirks & SDHCI_QUIRK_REG32_RW)
 904                 host->version =
 905                         sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
 906         else
 907                 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
 908
 909         cfg->name = host->name;
 910 #ifndef CONFIG_DM_MMC
 911         cfg->ops = &sdhci_ops;
 912 #endif
 913
 914         /* Check whether the clock multiplier is supported or not */
 915         if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
 916 #if CONFIG_IS_ENABLED(DM_MMC)
 917                 caps_1 = ~upper_32_bits(dt_caps_mask) &
 918                          sdhci_readl(host, SDHCI_CAPABILITIES_1);
 919                 caps_1 |= upper_32_bits(dt_caps);
 920 #else
 921                 caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
 922 #endif
 923                 log_debug("caps_1: %#x\n", caps_1);
 924                 host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
 925                                 SDHCI_CLOCK_MUL_SHIFT;
 926
 927                 /*
 928                  * In case the value in Clock Multiplier is 0, then programmable
 929                  * clock mode is not supported, otherwise the actual clock
 930                  * multiplier is one more than the value of Clock Multiplier
 931                  * in the Capabilities Register.
 932                  */
 933                 if (host->clk_mul)
 934                         host->clk_mul += 1;
 935         }
 936
 937         if (host->max_clk == 0) {
 938                 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
 939                         host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
 940                                 SDHCI_CLOCK_BASE_SHIFT;
 941                 else
 942                         host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >>
 943                                 SDHCI_CLOCK_BASE_SHIFT;
 944                 host->max_clk *= 1000000;
 945                 if (host->clk_mul)
 946                         host->max_clk *= host->clk_mul;
 947         }
 948         if (host->max_clk == 0) {
 949                 log_err("Hardware doesn't specify base clock frequency\n");
 950                 return -EINVAL;
 951         }
 952         if (f_max && (f_max < host->max_clk))
 953                 cfg->f_max = f_max;
 954         else
 955                 cfg->f_max = host->max_clk;
 956         if (f_min)
 957                 cfg->f_min = f_min;
 958         else {
 959                 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
 960                         cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300;
 961                 else
 962                         cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_200;
 963         }
 964         cfg->voltages = 0;
 965         if (caps & SDHCI_CAN_VDD_330)
 966                 cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
 967         if (caps & SDHCI_CAN_VDD_300)
 968                 cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
 969         if (caps & SDHCI_CAN_VDD_180)
 970                 cfg->voltages |= MMC_VDD_165_195;
 971
 972         if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
 973                 cfg->voltages |= host->voltages;
 974
 975         if (caps & SDHCI_CAN_DO_HISPD)
 976                 cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
 977
 978         cfg->host_caps |= MMC_MODE_4BIT;
 979
 980         /* Since Host Controller Version3.0 */
 981         if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
 982                 if (!(caps & SDHCI_CAN_DO_8BIT))
 983                         cfg->host_caps &= ~MMC_MODE_8BIT;
 984         }
 985
 986         if (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE) {
 987                 cfg->host_caps &= ~MMC_MODE_HS;
 988                 cfg->host_caps &= ~MMC_MODE_HS_52MHz;
 989         }
 990
 991         if (!(cfg->voltages & MMC_VDD_165_195) ||
 992             (host->quirks & SDHCI_QUIRK_NO_1_8_V))
 993                 caps_1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
 994                             SDHCI_SUPPORT_DDR50);
 995
 996         if (caps_1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
 997                       SDHCI_SUPPORT_DDR50))
 998                 cfg->host_caps |= MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25);
 999
1000         if (caps_1 & SDHCI_SUPPORT_SDR104) {
1001                 cfg->host_caps |= MMC_CAP(UHS_SDR104) | MMC_CAP(UHS_SDR50);
1002                 /*
1003                  * SD3.0: SDR104 is supported so (for eMMC) the caps2
1004                  * field can be promoted to support HS200.
1005                  */
1006                 cfg->host_caps |= MMC_CAP(MMC_HS_200);
1007         } else if (caps_1 & SDHCI_SUPPORT_SDR50) {
1008                 cfg->host_caps |= MMC_CAP(UHS_SDR50);
1009         }
1010
1011         if ((host->quirks & SDHCI_QUIRK_CAPS_BIT63_FOR_HS400) &&
1012             (caps_1 & SDHCI_SUPPORT_HS400))
1013                 cfg->host_caps |= MMC_CAP(MMC_HS_400);
1014
1015         if (caps_1 & SDHCI_SUPPORT_DDR50)
1016                 cfg->host_caps |= MMC_CAP(UHS_DDR50);
1017
1018         if (host->host_caps)
1019                 cfg->host_caps |= host->host_caps;
1020
1021         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1022
1023         return 0;
1024 }
1025
1026 #ifdef CONFIG_BLK
1027 int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
1028 {
1029         return mmc_bind(dev, mmc, cfg);
1030 }
1031 #else
1032 int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min)
1033 {
1034         int ret;
1035
1036         ret = sdhci_setup_cfg(&host->cfg, host, f_max, f_min);
1037         if (ret)
1038                 return ret;
1039
1040         host->mmc = mmc_create(&host->cfg, host);
1041         if (host->mmc == NULL) {
1042                 log_err("mmc create fail\n");
1043                 return -ENOMEM;
1044         }
1045
1046         return 0;
1047 }
1048 #endif