drivers/fpga/versalpl.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * (C) Copyright 2019, Xilinx, Inc,
   4  * Siva Durga Prasad Paladugu <[email protected]>>
   5  */
   6
   7 #include <cpu_func.h>
   8 #include <log.h>
   9 #include <asm/arch/sys_proto.h>
  10 #include <memalign.h>
  11 #include <versalpl.h>
  12 #include <zynqmp_firmware.h>
  13 #include <asm/cache.h>
  14
  15 static ulong versal_align_dma_buffer(ulong *buf, u32 len)
  16 {
  17         ulong *new_buf;
  18
  19         if ((ulong)buf != ALIGN((ulong)buf, ARCH_DMA_MINALIGN)) {
  20                 new_buf = (ulong *)ALIGN((ulong)buf, ARCH_DMA_MINALIGN);
  21                 memcpy(new_buf, buf, len);
  22                 buf = new_buf;
  23         }
  24
  25         return (ulong)buf;
  26 }
  27
  28 static int versal_load(xilinx_desc *desc, const void *buf, size_t bsize,
  29                        bitstream_type bstype, int flags)
  30 {
  31         ulong bin_buf;
  32         int ret;
  33         u32 buf_lo, buf_hi;
  34         u32 ret_payload[PAYLOAD_ARG_CNT];
  35
  36         bin_buf = versal_align_dma_buffer((ulong *)buf, bsize);
  37
  38         debug("%s called!\n", __func__);
  39         flush_dcache_range(bin_buf, bin_buf + bsize);
  40
  41         buf_lo = lower_32_bits(bin_buf);
  42         buf_hi = upper_32_bits(bin_buf);
  43
  44         ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo,
  45                                 buf_hi, 0, ret_payload);
  46         if (ret)
  47                 printf("PL FPGA LOAD failed with err: 0x%08x\n", ret);
  48
  49         return ret;
  50 }
  51
  52 struct xilinx_fpga_op versal_op = {
  53         .load = versal_load,
  54 };