drivers/clk/at91/pmc.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2016 Atmel Corporation
   4  *               Wenyou.Yang <[email protected]>
   5  */
   6
   7 #ifndef __AT91_PMC_H__
   8 #define __AT91_PMC_H__
   9
  10 #include <linux/bitops.h>
  11 #include <linux/io.h>
  12
  13 /* Keep a range of 256 available clocks for every clock type. */
  14 #define AT91_TO_CLK_ID(_t, _i)          (((_t) << 8) | ((_i) & 0xff))
  15 #define AT91_CLK_ID_TO_DID(_i)          ((_i) & 0xff)
  16
  17 struct clk_range {
  18         unsigned long min;
  19         unsigned long max;
  20 };
  21
  22 struct clk_master_layout {
  23         u32 offset;
  24         u32 mask;
  25         u8 pres_shift;
  26 };
  27
  28 extern const struct clk_master_layout at91rm9200_master_layout;
  29 extern const struct clk_master_layout at91sam9x5_master_layout;
  30
  31 struct clk_master_characteristics {
  32         struct clk_range output;
  33         u32 divisors[5];
  34         u8 have_div3_pres;
  35 };
  36
  37 struct clk_pll_characteristics {
  38         struct clk_range input;
  39         int num_output;
  40         const struct clk_range *output;
  41         u16 *icpll;
  42         u8 *out;
  43         u8 upll : 1;
  44 };
  45
  46 struct clk_pll_layout {
  47         u32 pllr_mask;
  48         u32 mul_mask;
  49         u32 frac_mask;
  50         u32 div_mask;
  51         u32 endiv_mask;
  52         u8 mul_shift;
  53         u8 frac_shift;
  54         u8 div_shift;
  55         u8 endiv_shift;
  56 };
  57
  58 struct clk_programmable_layout {
  59         u8 pres_mask;
  60         u8 pres_shift;
  61         u8 css_mask;
  62         u8 have_slck_mck;
  63         u8 is_pres_direct;
  64 };
  65
  66 struct clk_pcr_layout {
  67         u32 offset;
  68         u32 cmd;
  69         u32 div_mask;
  70         u32 gckcss_mask;
  71         u32 pid_mask;
  72 };
  73
  74 struct clk_usbck_layout {
  75         u32 offset;
  76         u32 usbs_mask;
  77         u32 usbdiv_mask;
  78 };
  79
  80 /**
  81  * Clock setup description
  82  * @cid:        clock id corresponding to clock subsystem
  83  * @pid:        parent clock id corresponding to clock subsystem
  84  * @rate:       clock rate
  85  * @prate:      parent rate
  86  */
  87 struct pmc_clk_setup {
  88         unsigned int cid;
  89         unsigned int pid;
  90         unsigned long rate;
  91         unsigned long prate;
  92 };
  93
  94 extern const struct clk_programmable_layout at91rm9200_programmable_layout;
  95 extern const struct clk_programmable_layout at91sam9g45_programmable_layout;
  96 extern const struct clk_programmable_layout at91sam9x5_programmable_layout;
  97
  98 extern const struct clk_ops at91_clk_ops;
  99
 100 struct clk *at91_clk_main_rc(void __iomem *reg, const char *name,
 101                         const char *parent_name);
 102 struct clk *at91_clk_main_osc(void __iomem *reg, const char *name,
 103                         const char *parent_name, bool bypass);
 104 struct clk *at91_clk_rm9200_main(void __iomem *reg, const char *name,
 105                         const char *parent_name);
 106 struct clk *at91_clk_sam9x5_main(void __iomem *reg, const char *name,
 107                         const char * const *parent_names, int num_parents,
 108                         const u32 *mux_table, int type);
 109 struct clk *
 110 sam9x60_clk_register_usb(void __iomem *base,  const char *name,
 111                          const char * const *parent_names, u8 num_parents,
 112                          const struct clk_usbck_layout *usbck_layout,
 113                          const u32 *clk_mux_table, const u32 *mux_table, u8 id);
 114 struct clk *
 115 sam9x60_clk_register_div_pll(void __iomem *base, const char *name,
 116                         const char *parent_name, u8 id,
 117                         const struct clk_pll_characteristics *characteristics,
 118                         const struct clk_pll_layout *layout, bool critical);
 119 struct clk *
 120 sam9x60_clk_register_frac_pll(void __iomem *base, const char *name,
 121                         const char *parent_name, u8 id,
 122                         const struct clk_pll_characteristics *characteristics,
 123                         const struct clk_pll_layout *layout, bool critical);
 124 struct clk *
 125 at91_clk_register_master_pres(void __iomem *base, const char *name,
 126                         const char * const *parent_names, int num_parents,
 127                         const struct clk_master_layout *layout,
 128                         const struct clk_master_characteristics *characteristics,
 129                         const u32 *mux_table);
 130 struct clk *
 131 at91_clk_register_master_div(void __iomem *base,
 132                         const char *name, const char *parent_name,
 133                         const struct clk_master_layout *layout,
 134                         const struct clk_master_characteristics *characteristics);
 135 struct clk *
 136 at91_clk_sama7g5_register_master(void __iomem *base, const char *name,
 137                         const char * const *parent_names, int num_parents,
 138                         const u32 *mux_table, const u32 *clk_mux_table,
 139                         bool critical, u8 id);
 140 struct clk *
 141 at91_clk_register_utmi(void __iomem *base, struct udevice *dev,
 142                         const char *name, const char *parent_name);
 143 struct clk *
 144 at91_clk_sama7g5_register_utmi(void __iomem *base, const char *name,
 145                         const char *parent_name);
 146 struct clk *
 147 at91_clk_register_programmable(void __iomem *base, const char *name,
 148                         const char * const *parent_names, u8 num_parents, u8 id,
 149                         const struct clk_programmable_layout *layout,
 150                         const u32 *clk_mux_table, const u32 *mux_table);
 151 struct clk *
 152 at91_clk_register_system(void __iomem *base, const char *name,
 153                         const char *parent_name, u8 id);
 154 struct clk *
 155 at91_clk_register_peripheral(void __iomem *base, const char *name,
 156                         const char *parent_name, u32 id);
 157 struct clk *
 158 at91_clk_register_sam9x5_peripheral(void __iomem *base,
 159                         const struct clk_pcr_layout *layout,
 160                         const char *name, const char *parent_name,
 161                         u32 id, const struct clk_range *range);
 162 struct clk *
 163 at91_clk_register_generic(void __iomem *base,
 164                         const struct clk_pcr_layout *layout, const char *name,
 165                         const char * const *parent_names,
 166                         const u32 *clk_mux_table, const u32 *mux_table,
 167                         u8 num_parents, u8 id, const struct clk_range *range);
 168
 169 int at91_clk_mux_val_to_index(const u32 *table, u32 num_parents, u32 val);
 170 int at91_clk_mux_index_to_val(const u32 *table, u32 num_parents, u32 index);
 171
 172 void pmc_read(void __iomem *base, unsigned int off, unsigned int *val);
 173 void pmc_write(void __iomem *base, unsigned int off, unsigned int val);
 174 void pmc_update_bits(void __iomem *base, unsigned int off, unsigned int mask,
 175                         unsigned int bits);
 176
 177 int at91_clk_setup(const struct pmc_clk_setup *setup, int size);
 178
 179 #endif