arch/arm/mach-zynq/clk.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2013 Soren Brinkmann <[email protected]>
   4  * Copyright (C) 2013 Xilinx, Inc. All rights reserved.
   5  */
   6 #include <clk.h>
   7 #include <dm.h>
   8 #include <init.h>
   9 #include <malloc.h>
  10 #include <asm/arch/clk.h>
  11 #include <asm/global_data.h>
  12
  13 DECLARE_GLOBAL_DATA_PTR;
  14
  15 /**
  16  * set_cpu_clk_info() - Setup clock information
  17  *
  18  * This function is called from common code after relocation and sets up the
  19  * clock information.
  20  */
  21 int set_cpu_clk_info(void)
  22 {
  23         struct clk clk;
  24         struct udevice *dev;
  25         ulong rate;
  26         int i, ret;
  27
  28         ret = uclass_get_device_by_driver(UCLASS_CLK,
  29                 DM_DRIVER_GET(zynq_clk), &dev);
  30         if (ret)
  31                 return ret;
  32
  33         for (i = 0; i < 2; i++) {
  34                 clk.id = i ? ddr3x_clk : cpu_6or4x_clk;
  35                 ret = clk_request(dev, &clk);
  36                 if (ret < 0)
  37                         return ret;
  38
  39                 rate = clk_get_rate(&clk) / 1000000;
  40                 if (i) {
  41                         gd->bd->bi_ddr_freq = rate;
  42                 } else {
  43                         gd->bd->bi_arm_freq = rate;
  44                         gd->cpu_clk = clk_get_rate(&clk);
  45                 }
  46         }
  47         gd->bd->bi_dsp_freq = 0;
  48
  49         return 0;
  50 }