1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * Copyright (C) 2020, STMicroelectronics - All Rights Reserved
15 #include <asm/arch/stm32mp1_smc.h>
16 #include <asm/global_data.h>
17 #include <dm/device_compat.h>
18 #include <dm/uclass.h>
19 #include <jffs2/load_kernel.h>
20 #include <linux/list.h>
21 #include <linux/list_sort.h>
22 #include <linux/mtd/mtd.h>
23 #include <linux/printk.h>
24 #include <linux/sizes.h>
26 #include "stm32prog.h"
28 /* Primary GPT header size for 128 entries : 17kB = 34 LBA of 512B */
29 #define GPT_HEADER_SZ 34
31 #define OPT_SELECT BIT(0)
32 #define OPT_EMPTY BIT(1)
33 #define OPT_DELETE BIT(2)
35 #define IS_SELECT(part) ((part)->option & OPT_SELECT)
36 #define IS_EMPTY(part) ((part)->option & OPT_EMPTY)
37 #define IS_DELETE(part) ((part)->option & OPT_DELETE)
39 #define ALT_BUF_LEN SZ_1K
41 #define ROOTFS_MMC0_UUID \
42 EFI_GUID(0xE91C4E10, 0x16E6, 0x4C0E, \
43 0xBD, 0x0E, 0x77, 0xBE, 0xCF, 0x4A, 0x35, 0x82)
45 #define ROOTFS_MMC1_UUID \
46 EFI_GUID(0x491F6117, 0x415D, 0x4F53, \
47 0x88, 0xC9, 0x6E, 0x0D, 0xE5, 0x4D, 0xEA, 0xC6)
49 #define ROOTFS_MMC2_UUID \
50 EFI_GUID(0xFD58F1C7, 0xBE0D, 0x4338, \
51 0x88, 0xE9, 0xAD, 0x8F, 0x05, 0x0A, 0xEB, 0x18)
53 /* RAW partition (binary / bootloader) used Linux - reserved UUID */
54 #define LINUX_RESERVED_UUID "8DA63339-0007-60C0-C436-083AC8230908"
57 * unique partition guid (uuid) for partition named "rootfs"
58 * on each MMC instance = SD Card or eMMC
59 * allow fixed kernel bootcmd: "rootf=PARTUID=e91c4e10-..."
61 static const efi_guid_t uuid_mmc[3] = {
68 * GUID value defined in the FWU specification for identification
69 * of the FWU metadata partition.
71 #define FWU_MDATA_UUID "8a7a84a0-8387-40f6-ab41-a8b9a5a60d23"
73 /* FIP type partition UUID used by TF-A*/
74 #define FIP_TYPE_UUID "19D5DF83-11B0-457B-BE2C-7559C13142A5"
76 /* unique partition guid (uuid) for FIP partitions A/B */
78 EFI_GUID(0x4FD84C93, 0x54EF, 0x463F, \
79 0xA7, 0xEF, 0xAE, 0x25, 0xFF, 0x88, 0x70, 0x87)
82 EFI_GUID(0x09C54952, 0xD5BF, 0x45AF, \
83 0xAC, 0xEE, 0x33, 0x53, 0x03, 0x76, 0x6F, 0xB3)
85 static const char * const fip_part_name[] = {
90 static const efi_guid_t fip_part_uuid[] = {
95 /* order of column in flash layout file */
96 enum stm32prog_col_t {
106 #define FIP_TOC_HEADER_NAME 0xAA640001
108 struct fip_toc_header {
114 #define TA_NVMEM_UUID { 0x1a8342cc, 0x81a5, 0x4512, \
115 { 0x99, 0xfe, 0x9e, 0x2b, 0x3e, 0x37, 0xd6, 0x26 } }
118 * Read NVMEM memory for STM32CubeProgrammer
120 * [in] value[0].a: Type (0 for OTP access)
121 * [out] memref[1].buffer Output buffer to return all read values
122 * [out] memref[1].size Size of buffer to be read
125 * TEE_SUCCESS - Invoke command success
126 * TEE_ERROR_BAD_PARAMETERS - Incorrect input param
128 #define TA_NVMEM_READ 0x0
131 * Write NVMEM memory for STM32CubeProgrammer
133 * [in] value[0].a Type (0 for OTP access)
134 * [in] memref[1].buffer Input buffer with the values to write
135 * [in] memref[1].size Size of buffer to be written
138 * TEE_SUCCESS - Invoke command success
139 * TEE_ERROR_BAD_PARAMETERS - Incorrect input param
141 #define TA_NVMEM_WRITE 0x1
143 /* value of TA_NVMEM type = value[in] a */
146 DECLARE_GLOBAL_DATA_PTR;
148 /* OPTEE TA NVMEM open helper */
149 static int optee_ta_open(struct stm32prog_data *data)
151 const struct tee_optee_ta_uuid uuid = TA_NVMEM_UUID;
152 struct tee_open_session_arg arg;
153 struct udevice *tee = NULL;
159 tee = tee_find_device(NULL, NULL, NULL, NULL);
163 memset(&arg, 0, sizeof(arg));
164 tee_optee_ta_uuid_to_octets(arg.uuid, &uuid);
165 rc = tee_open_session(tee, &arg, 0, NULL);
170 data->tee_session = arg.session;
175 /* OPTEE TA NVMEM invoke helper */
176 static int optee_ta_invoke(struct stm32prog_data *data, int cmd, int type,
177 void *buff, ulong size)
179 struct tee_invoke_arg arg;
180 struct tee_param param[2];
181 struct tee_shm *buff_shm;
184 rc = tee_shm_register(data->tee, buff, size, 0, &buff_shm);
188 memset(&arg, 0, sizeof(arg));
190 arg.session = data->tee_session;
192 memset(param, 0, sizeof(param));
193 param[0].attr = TEE_PARAM_ATTR_TYPE_VALUE_INPUT;
194 param[0].u.value.a = type;
196 if (cmd == TA_NVMEM_WRITE)
197 param[1].attr = TEE_PARAM_ATTR_TYPE_MEMREF_INPUT;
199 param[1].attr = TEE_PARAM_ATTR_TYPE_MEMREF_OUTPUT;
201 param[1].u.memref.shm = buff_shm;
202 param[1].u.memref.size = size;
204 rc = tee_invoke_func(data->tee, &arg, 2, param);
205 if (rc < 0 || arg.ret != 0) {
207 "TA_NVMEM invoke failed TEE err: %x, err:%x\n",
213 tee_shm_free(buff_shm);
218 char *stm32prog_get_error(struct stm32prog_data *data)
220 static const char error_msg[] = "Unspecified";
222 if (strlen(data->error) == 0)
223 strcpy(data->error, error_msg);
228 static bool stm32prog_is_fip_header(struct fip_toc_header *header)
230 return (header->name == FIP_TOC_HEADER_NAME) && header->serial_number;
233 static bool stm32prog_is_stm32_header_v1(struct stm32_header_v1 *header)
237 if (header->magic_number !=
238 (('S' << 0) | ('T' << 8) | ('M' << 16) | (0x32 << 24))) {
239 log_debug("%s:invalid magic number : 0x%x\n",
240 __func__, header->magic_number);
243 if (header->header_version != 0x00010000) {
244 log_debug("%s:invalid header version : 0x%x\n",
245 __func__, header->header_version);
249 if (header->reserved1 || header->reserved2) {
250 log_debug("%s:invalid reserved field\n", __func__);
253 for (i = 0; i < sizeof(header->padding); i++) {
254 if (header->padding[i] != 0) {
255 log_debug("%s:invalid padding field\n", __func__);
263 static bool stm32prog_is_stm32_header_v2(struct stm32_header_v2 *header)
267 if (header->magic_number !=
268 (('S' << 0) | ('T' << 8) | ('M' << 16) | (0x32 << 24))) {
269 log_debug("%s:invalid magic number : 0x%x\n",
270 __func__, header->magic_number);
273 if (header->header_version != 0x00020000) {
274 log_debug("%s:invalid header version : 0x%x\n",
275 __func__, header->header_version);
278 if (header->reserved1 || header->reserved2)
281 for (i = 0; i < sizeof(header->padding); i++) {
282 if (header->padding[i] != 0) {
283 log_debug("%s:invalid padding field\n", __func__);
291 void stm32prog_header_check(uintptr_t raw_header, struct image_header_s *header)
293 struct stm32_header_v1 *v1_header = (struct stm32_header_v1 *)raw_header;
294 struct stm32_header_v2 *v2_header = (struct stm32_header_v2 *)raw_header;
296 if (!raw_header || !header) {
297 log_debug("%s:no header data\n", __func__);
301 if (stm32prog_is_fip_header((struct fip_toc_header *)raw_header)) {
302 header->type = HEADER_FIP;
306 if (stm32prog_is_stm32_header_v1(v1_header)) {
307 header->type = HEADER_STM32IMAGE;
308 header->image_checksum = le32_to_cpu(v1_header->image_checksum);
309 header->image_length = le32_to_cpu(v1_header->image_length);
310 header->length = sizeof(struct stm32_header_v1);
313 if (stm32prog_is_stm32_header_v2(v2_header)) {
314 header->type = HEADER_STM32IMAGE_V2;
315 header->image_checksum = le32_to_cpu(v2_header->image_checksum);
316 header->image_length = le32_to_cpu(v2_header->image_length);
317 header->length = sizeof(struct stm32_header_v1) +
318 v2_header->extension_headers_length;
322 header->type = HEADER_NONE;
323 header->image_checksum = 0x0;
324 header->image_length = 0x0;
327 static u32 stm32prog_header_checksum(uintptr_t addr, struct image_header_s *header)
332 /* compute checksum on payload */
333 payload = (u8 *)addr;
335 for (i = header->image_length; i > 0; i--)
336 checksum += *(payload++);
341 /* FLASHLAYOUT PARSING *****************************************/
342 static int parse_option(struct stm32prog_data *data,
343 int i, char *p, struct stm32prog_part_t *part)
355 part->option |= OPT_SELECT;
358 part->option |= OPT_EMPTY;
361 part->option |= OPT_DELETE;
365 stm32prog_err("Layout line %d: invalid option '%c' in %s)",
371 if (!(part->option & OPT_SELECT)) {
372 stm32prog_err("Layout line %d: missing 'P' in option %s", i, p);
379 static int parse_id(struct stm32prog_data *data,
380 int i, char *p, struct stm32prog_part_t *part)
385 result = strict_strtoul(p, 0, &value);
387 if (result || value > PHASE_LAST_USER) {
388 stm32prog_err("Layout line %d: invalid phase value = %s", i, p);
395 static int parse_name(struct stm32prog_data *data,
396 int i, char *p, struct stm32prog_part_t *part)
400 if (strlen(p) < sizeof(part->name)) {
401 strcpy(part->name, p);
403 stm32prog_err("Layout line %d: partition name too long [%zd]: %s",
411 static int parse_type(struct stm32prog_data *data,
412 int i, char *p, struct stm32prog_part_t *part)
418 if (!strncmp(p, "Binary", 6)) {
419 part->part_type = PART_BINARY;
421 /* search for Binary(X) case */
431 dectoul(&p[7], NULL);
433 } else if (!strcmp(p, "FIP")) {
434 part->part_type = PART_FIP;
435 } else if (!strcmp(p, "FWU_MDATA")) {
436 part->part_type = PART_FWU_MDATA;
437 } else if (!strcmp(p, "ENV")) {
438 part->part_type = PART_ENV;
439 } else if (!strcmp(p, "System")) {
440 part->part_type = PART_SYSTEM;
441 } else if (!strcmp(p, "ESP")) {
442 part->part_type = PART_ESP;
443 } else if (!strcmp(p, "FileSystem")) {
444 part->part_type = PART_FILESYSTEM;
445 } else if (!strcmp(p, "RawImage")) {
446 part->part_type = RAW_IMAGE;
451 stm32prog_err("Layout line %d: type parsing error : '%s'",
457 static int parse_ip(struct stm32prog_data *data,
458 int i, char *p, struct stm32prog_part_t *part)
461 unsigned int len = 0;
464 if (!strcmp(p, "none")) {
465 part->target = STM32PROG_NONE;
466 } else if (!strncmp(p, "mmc", 3)) {
467 part->target = STM32PROG_MMC;
469 } else if (!strncmp(p, "nor", 3)) {
470 part->target = STM32PROG_NOR;
472 } else if (!strncmp(p, "nand", 4)) {
473 part->target = STM32PROG_NAND;
475 } else if (!strncmp(p, "spi-nand", 8)) {
476 part->target = STM32PROG_SPI_NAND;
478 } else if (!strncmp(p, "ram", 3)) {
479 part->target = STM32PROG_RAM;
485 /* only one digit allowed for device id */
486 if (strlen(p) != len + 1) {
489 part->dev_id = p[len] - '0';
490 if (part->dev_id > 9)
495 stm32prog_err("Layout line %d: ip parsing error: '%s'", i, p);
500 static int parse_offset(struct stm32prog_data *data,
501 int i, char *p, struct stm32prog_part_t *part)
509 /* eMMC boot parttion */
510 if (!strncmp(p, "boot", 4)) {
511 if (strlen(p) != 5) {
516 else if (p[4] == '2')
522 stm32prog_err("Layout line %d: invalid part '%s'",
525 part->addr = simple_strtoull(p, &tail, 10);
526 if (tail == p || *tail != '\0') {
527 stm32prog_err("Layout line %d: invalid offset '%s'",
537 int (* const parse[COL_NB_STM32])(struct stm32prog_data *data, int i, char *p,
538 struct stm32prog_part_t *part) = {
539 [COL_OPTION] = parse_option,
541 [COL_NAME] = parse_name,
542 [COL_TYPE] = parse_type,
544 [COL_OFFSET] = parse_offset,
547 static int parse_flash_layout(struct stm32prog_data *data,
551 int column = 0, part_nb = 0, ret;
552 bool end_of_line, eof;
553 char *p, *start, *last, *col;
554 struct stm32prog_part_t *part;
555 struct image_header_s header;
561 /* check if STM32image is detected */
562 stm32prog_header_check(addr, &header);
563 if (header.type == HEADER_STM32IMAGE) {
566 addr = addr + header.length;
567 size = header.image_length;
569 checksum = stm32prog_header_checksum(addr, &header);
570 if (checksum != header.image_checksum) {
571 stm32prog_err("Layout: invalid checksum : 0x%x expected 0x%x",
572 checksum, header.image_checksum);
579 start = (char *)addr;
582 *last = 0x0; /* force null terminated string */
583 log_debug("flash layout =\n%s\n", start);
585 /* calculate expected number of partitions */
588 while (*p && (p < last)) {
591 if (p < last && *p == '#')
595 if (part_list_size > PHASE_LAST_USER) {
596 stm32prog_err("Layout: too many partition (%d)",
600 part = calloc(sizeof(struct stm32prog_part_t), part_list_size);
602 stm32prog_err("Layout: alloc failed");
605 data->part_array = part;
607 /* main parsing loop */
611 col = start; /* 1st column */
615 /* CR is ignored and replaced by NULL character */
630 /* comment line is skipped */
631 if (column == 0 && p == col) {
632 while ((p < last) && *p)
637 if (p >= last || !*p) {
644 /* by default continue with the next character */
650 /* replace by \0: allow string parsing for each column */
658 /* skip empty line and multiple TAB in tsv file */
659 if (strlen(col) == 0) {
661 /* skip empty line */
662 if (column == 0 && end_of_line) {
669 if (column < COL_NB_STM32) {
670 ret = parse[column](data, i, col, part);
675 /* save the beginning of the next column */
682 /* end of the line detected */
685 if (column < COL_NB_STM32) {
686 stm32prog_err("Layout line %d: no enought column", i);
693 if (part_nb >= part_list_size) {
696 stm32prog_err("Layout: no enought memory for %d part",
702 data->part_nb = part_nb;
703 if (data->part_nb == 0) {
704 stm32prog_err("Layout: no partition found");
711 static int __init part_cmp(void *priv, struct list_head *a, struct list_head *b)
713 struct stm32prog_part_t *parta, *partb;
715 parta = container_of(a, struct stm32prog_part_t, list);
716 partb = container_of(b, struct stm32prog_part_t, list);
718 if (parta->part_id != partb->part_id)
719 return parta->part_id - partb->part_id;
721 return parta->addr > partb->addr ? 1 : -1;
724 static void get_mtd_by_target(char *string, enum stm32prog_target target,
736 case STM32PROG_SPI_NAND:
737 dev_str = "spi-nand";
743 sprintf(string, "%s%d", dev_str, dev_id);
746 static int init_device(struct stm32prog_data *data,
747 struct stm32prog_dev_t *dev)
749 struct mmc *mmc = NULL;
750 struct blk_desc *block_dev = NULL;
751 struct mtd_info *mtd = NULL;
752 struct mtd_info *partition;
756 u64 first_addr = 0, last_addr = 0;
757 struct stm32prog_part_t *part, *next_part;
758 u64 part_addr, part_size;
760 const char *part_name;
763 switch (dev->target) {
765 if (!IS_ENABLED(CONFIG_MMC)) {
766 stm32prog_err("unknown device type = %d", dev->target);
769 mmc = find_mmc_device(dev->dev_id);
770 if (!mmc || mmc_init(mmc)) {
771 stm32prog_err("mmc device %d not found", dev->dev_id);
774 block_dev = mmc_get_blk_desc(mmc);
776 stm32prog_err("mmc device %d not probed", dev->dev_id);
779 dev->erase_size = mmc->erase_grp_size * block_dev->blksz;
782 /* reserve a full erase group for each GTP headers */
783 if (mmc->erase_grp_size > GPT_HEADER_SZ) {
784 first_addr = dev->erase_size;
785 last_addr = (u64)(block_dev->lba -
786 mmc->erase_grp_size) *
789 first_addr = (u64)GPT_HEADER_SZ * block_dev->blksz;
790 last_addr = (u64)(block_dev->lba - GPT_HEADER_SZ - 1) *
793 log_debug("MMC %d: lba=%lld blksz=%ld\n", dev->dev_id,
794 (u64)block_dev->lba, block_dev->blksz);
795 log_debug(" available address = 0x%llx..0x%llx\n",
796 first_addr, last_addr);
797 log_debug(" full_update = %d\n", dev->full_update);
801 case STM32PROG_SPI_NAND:
802 if (!IS_ENABLED(CONFIG_MTD)) {
803 stm32prog_err("unknown device type = %d", dev->target);
806 /* register partitions with MTDIDS/MTDPARTS or OF fallback */
808 get_mtd_by_target(mtd_id, dev->target, dev->dev_id);
809 log_debug("%s\n", mtd_id);
811 mtd = get_mtd_device_nm(mtd_id);
813 stm32prog_err("MTD device %s not found", mtd_id);
817 last_addr = mtd->size;
818 dev->erase_size = mtd->erasesize;
819 log_debug("MTD device %s: size=%lld erasesize=%d\n",
820 mtd_id, mtd->size, mtd->erasesize);
821 log_debug(" available address = 0x%llx..0x%llx\n",
822 first_addr, last_addr);
826 first_addr = gd->bd->bi_dram[0].start;
827 last_addr = first_addr + gd->bd->bi_dram[0].size;
831 stm32prog_err("unknown device type = %d", dev->target);
834 log_debug(" erase size = 0x%x\n", dev->erase_size);
835 log_debug(" full_update = %d\n", dev->full_update);
837 /* order partition list in offset order */
838 list_sort(NULL, &dev->part_list, &part_cmp);
840 log_debug("id : Opt Phase Name target.n dev.n addr size part_off part_size\n");
841 list_for_each_entry(part, &dev->part_list, list) {
842 if (part->bin_nb > 1) {
843 if ((dev->target != STM32PROG_NAND &&
844 dev->target != STM32PROG_SPI_NAND) ||
845 part->id >= PHASE_FIRST_USER ||
846 strncmp(part->name, "fsbl", 4)) {
847 stm32prog_err("%s (0x%x): multiple binary %d not supported",
848 part->name, part->id,
853 if (part->part_type == RAW_IMAGE) {
857 part->size = block_dev->lba * block_dev->blksz;
859 part->size = last_addr;
860 log_debug("-- : %1d %02x %14s %02d.%d %02d.%02d %08llx %08llx\n",
861 part->option, part->id, part->name,
862 part->part_type, part->bin_nb, part->target,
863 part->dev_id, part->addr, part->size);
866 if (part->part_id < 0) { /* boot hw partition for eMMC */
868 part->size = mmc->capacity_boot;
870 stm32prog_err("%s (0x%x): hw partition not expected : %d",
871 part->name, part->id,
876 part->part_id = part_id++;
878 /* last partition : size to the end of the device */
879 if (part->list.next != &dev->part_list) {
881 container_of(part->list.next,
882 struct stm32prog_part_t,
884 if (part->addr < next_part->addr) {
885 part->size = next_part->addr -
888 stm32prog_err("%s (0x%x): same address : 0x%llx == %s (0x%x): 0x%llx",
889 part->name, part->id,
897 if (part->addr <= last_addr) {
898 part->size = last_addr - part->addr;
900 stm32prog_err("%s (0x%x): invalid address 0x%llx (max=0x%llx)",
901 part->name, part->id,
902 part->addr, last_addr);
906 if (part->addr < first_addr) {
907 stm32prog_err("%s (0x%x): invalid address 0x%llx (min=0x%llx)",
908 part->name, part->id,
909 part->addr, first_addr);
913 if ((part->addr & ((u64)part->dev->erase_size - 1)) != 0) {
914 stm32prog_err("%s (0x%x): not aligned address : 0x%llx on erase size 0x%x",
915 part->name, part->id, part->addr,
916 part->dev->erase_size);
919 log_debug("%02d : %1d %02x %14s %02d.%d %02d.%02d %08llx %08llx",
920 part->part_id, part->option, part->id, part->name,
921 part->part_type, part->bin_nb, part->target,
922 part->dev_id, part->addr, part->size);
928 /* check coherency with existing partition */
931 * block devices with GPT: check user partition size
932 * only for partial update, the GPT partions are be
933 * created for full update
935 if (dev->full_update || part->part_id < 0) {
939 struct disk_partition partinfo;
941 ret = part_get_info(block_dev, part->part_id,
945 stm32prog_err("%s (0x%x):Couldn't find part %d on device mmc %d",
946 part->name, part->id,
947 part_id, part->dev_id);
950 part_addr = (u64)partinfo.start * partinfo.blksz;
951 part_size = (u64)partinfo.size * partinfo.blksz;
952 part_name = (char *)partinfo.name;
956 if (IS_ENABLED(CONFIG_MTD) && mtd) {
958 list_for_each_entry(partition, &mtd->partitions, node) {
959 if ((part->part_id - 1) == i) {
966 part_addr = partition->offset;
967 part_size = partition->size;
968 part_name = partition->name;
970 stm32prog_err("%s (0x%x):Couldn't find part %d on device mtd %s",
971 part->name, part->id, part->part_id, mtd_id);
976 /* no partition for this device */
982 log_debug(" %08llx %08llx\n", part_addr, part_size);
984 if (part->addr != part_addr) {
985 stm32prog_err("%s (0x%x): Bad address for partition %d (%s) = 0x%llx <> 0x%llx expected",
986 part->name, part->id, part->part_id,
987 part_name, part->addr, part_addr);
990 if (part->size != part_size) {
991 stm32prog_err("%s (0x%x): Bad size for partition %d (%s) at 0x%llx = 0x%llx <> 0x%llx expected",
992 part->name, part->id, part->part_id,
993 part_name, part->addr, part->size,
1001 static int treat_partition_list(struct stm32prog_data *data)
1004 struct stm32prog_part_t *part;
1006 for (j = 0; j < STM32PROG_MAX_DEV; j++) {
1007 data->dev[j].target = STM32PROG_NONE;
1008 INIT_LIST_HEAD(&data->dev[j].part_list);
1011 data->fsbl_nor_detected = false;
1012 for (i = 0; i < data->part_nb; i++) {
1013 part = &data->part_array[i];
1016 /* skip partition with IP="none" */
1017 if (part->target == STM32PROG_NONE) {
1018 if (IS_SELECT(part)) {
1019 stm32prog_err("Layout: selected none phase = 0x%x for part %s",
1020 part->id, part->name);
1026 if (part->id == PHASE_FLASHLAYOUT ||
1027 part->id > PHASE_LAST_USER) {
1028 stm32prog_err("Layout: invalid phase = 0x%x for part %s",
1029 part->id, part->name);
1032 for (j = i + 1; j < data->part_nb; j++) {
1033 if (part->id == data->part_array[j].id) {
1034 stm32prog_err("Layout: duplicated phase 0x%x for part %s and %s",
1035 part->id, part->name, data->part_array[j].name);
1039 for (j = 0; j < STM32PROG_MAX_DEV; j++) {
1040 if (data->dev[j].target == STM32PROG_NONE) {
1041 /* new device found */
1042 data->dev[j].target = part->target;
1043 data->dev[j].dev_id = part->dev_id;
1044 data->dev[j].full_update = true;
1047 } else if ((part->target == data->dev[j].target) &&
1048 (part->dev_id == data->dev[j].dev_id)) {
1052 if (j == STM32PROG_MAX_DEV) {
1053 stm32prog_err("Layout: too many device");
1056 switch (part->target) {
1058 if (!data->fsbl_nor_detected &&
1059 !strncmp(part->name, "fsbl", 4))
1060 data->fsbl_nor_detected = true;
1065 part->dev = &data->dev[j];
1066 if (!IS_SELECT(part))
1067 part->dev->full_update = false;
1068 list_add_tail(&part->list, &data->dev[j].part_list);
1074 static int create_gpt_partitions(struct stm32prog_data *data)
1077 const int buflen = SZ_8K;
1079 char uuid[UUID_STR_LEN + 1];
1080 unsigned char *uuid_bin;
1081 unsigned int mmc_id;
1084 struct stm32prog_part_t *part;
1085 const char *type_str;
1087 buf = malloc(buflen);
1091 /* initialize the selected device */
1092 for (i = 0; i < data->dev_nb; i++) {
1093 /* create gpt partition support only for full update on MMC */
1094 if (data->dev[i].target != STM32PROG_MMC ||
1095 !data->dev[i].full_update)
1098 printf("partitions on mmc%d: ", data->dev[i].dev_id);
1100 rootfs_found = false;
1101 memset(buf, 0, buflen);
1103 list_for_each_entry(part, &data->dev[i].part_list, list) {
1104 /* skip eMMC boot partitions */
1105 if (part->part_id < 0)
1107 /* skip Raw Image */
1108 if (part->part_type == RAW_IMAGE)
1111 if (offset + 100 > buflen) {
1112 log_debug("\n%s: buffer too small, %s skippped",
1113 __func__, part->name);
1118 offset += sprintf(buf, "gpt write mmc %d \"",
1119 data->dev[i].dev_id);
1121 offset += snprintf(buf + offset, buflen - offset,
1122 "name=%s,start=0x%llx,size=0x%llx",
1127 switch (part->part_type) {
1129 type_str = LINUX_RESERVED_UUID;
1132 type_str = "u-boot-env";
1135 type_str = FIP_TYPE_UUID;
1137 case PART_FWU_MDATA:
1138 type_str = FWU_MDATA_UUID;
1141 /* EFI System Partition */
1142 type_str = "system";
1144 default: /* PART_FILESYSTEM or PART_SYSTEM for distro */
1148 offset += snprintf(buf + offset,
1150 ",type=%s", type_str);
1152 if (part->part_type == PART_SYSTEM)
1153 offset += snprintf(buf + offset,
1157 /* partition UUID */
1159 if (!rootfs_found && !strcmp(part->name, "rootfs")) {
1160 mmc_id = part->dev_id;
1161 rootfs_found = true;
1162 if (mmc_id < ARRAY_SIZE(uuid_mmc))
1163 uuid_bin = (unsigned char *)uuid_mmc[mmc_id].b;
1165 if (part->part_type == PART_FIP) {
1166 for (j = 0; j < ARRAY_SIZE(fip_part_name); j++)
1167 if (!strcmp(part->name, fip_part_name[j])) {
1168 uuid_bin = (unsigned char *)fip_part_uuid[j].b;
1173 uuid_bin_to_str(uuid_bin, uuid, UUID_STR_FORMAT_GUID);
1174 offset += snprintf(buf + offset,
1179 offset += snprintf(buf + offset, buflen - offset, ";");
1183 offset += snprintf(buf + offset, buflen - offset, "\"");
1184 log_debug("\ncmd: %s\n", buf);
1185 if (run_command(buf, 0)) {
1186 stm32prog_err("GPT partitionning fail: %s",
1194 if (data->dev[i].mmc)
1195 part_init(mmc_get_blk_desc(data->dev[i].mmc));
1198 sprintf(buf, "gpt verify mmc %d", data->dev[i].dev_id);
1199 log_debug("\ncmd: %s", buf);
1200 if (run_command(buf, 0))
1205 sprintf(buf, "part list mmc %d", data->dev[i].dev_id);
1206 run_command(buf, 0);
1212 run_command("mtd list", 0);
1219 static int stm32prog_alt_add(struct stm32prog_data *data,
1220 struct dfu_entity *dfu,
1221 struct stm32prog_part_t *part)
1227 char buf[ALT_BUF_LEN];
1229 char multiplier, type;
1231 /* max 3 digit for sector size */
1232 if (part->size > SZ_1G) {
1233 size = (u32)(part->size / SZ_1G);
1235 } else if (part->size > SZ_1M) {
1236 size = (u32)(part->size / SZ_1M);
1238 } else if (part->size > SZ_1K) {
1239 size = (u32)(part->size / SZ_1K);
1242 size = (u32)part->size;
1245 if (IS_SELECT(part) && !IS_EMPTY(part))
1246 type = 'e'; /*Readable and Writeable*/
1248 type = 'a';/*Readable*/
1250 memset(buf, 0, sizeof(buf));
1251 offset = snprintf(buf, ALT_BUF_LEN - offset,
1252 "@%s/0x%02x/1*%d%c%c ",
1253 part->name, part->id,
1254 size, multiplier, type);
1256 if (part->target == STM32PROG_RAM) {
1257 offset += snprintf(buf + offset, ALT_BUF_LEN - offset,
1258 "ram 0x%llx 0x%llx",
1259 part->addr, part->size);
1260 } else if (part->part_type == RAW_IMAGE) {
1263 if (part->dev->target == STM32PROG_MMC)
1264 dfu_size = part->size / part->dev->mmc->read_bl_len;
1266 dfu_size = part->size;
1267 offset += snprintf(buf + offset, ALT_BUF_LEN - offset,
1268 "raw 0x0 0x%llx", dfu_size);
1269 } else if (part->part_id < 0) {
1270 u64 nb_blk = part->size / part->dev->mmc->read_bl_len;
1272 offset += snprintf(buf + offset, ALT_BUF_LEN - offset,
1273 "raw 0x%llx 0x%llx",
1274 part->addr, nb_blk);
1275 offset += snprintf(buf + offset, ALT_BUF_LEN - offset,
1276 " mmcpart %d", -(part->part_id));
1278 if (part->part_type == PART_SYSTEM &&
1279 (part->target == STM32PROG_NAND ||
1280 part->target == STM32PROG_NOR ||
1281 part->target == STM32PROG_SPI_NAND))
1282 offset += snprintf(buf + offset,
1283 ALT_BUF_LEN - offset,
1286 offset += snprintf(buf + offset,
1287 ALT_BUF_LEN - offset,
1289 /* dev_id requested by DFU MMC */
1290 if (part->target == STM32PROG_MMC)
1291 offset += snprintf(buf + offset, ALT_BUF_LEN - offset,
1292 " %d", part->dev_id);
1293 offset += snprintf(buf + offset, ALT_BUF_LEN - offset,
1294 " %d", part->part_id);
1297 switch (part->target) {
1299 if (IS_ENABLED(CONFIG_MMC)) {
1301 sprintf(dfustr, "mmc");
1302 sprintf(devstr, "%d", part->dev_id);
1305 case STM32PROG_NAND:
1307 case STM32PROG_SPI_NAND:
1308 if (IS_ENABLED(CONFIG_MTD)) {
1310 sprintf(dfustr, "mtd");
1311 get_mtd_by_target(devstr, part->target, part->dev_id);
1316 sprintf(dfustr, "ram");
1317 sprintf(devstr, "0");
1323 stm32prog_err("invalid target: %d", part->target);
1326 log_debug("dfu_alt_add(%s,%s,%s)\n", dfustr, devstr, buf);
1327 ret = dfu_alt_add(dfu, dfustr, devstr, buf);
1328 log_debug("dfu_alt_add(%s,%s,%s) result %d\n",
1329 dfustr, devstr, buf, ret);
1334 static int stm32prog_alt_add_virt(struct dfu_entity *dfu,
1335 char *name, int phase, int size)
1339 char buf[ALT_BUF_LEN];
1341 sprintf(devstr, "%d", phase);
1342 sprintf(buf, "@%s/0x%02x/1*%dBe", name, phase, size);
1343 ret = dfu_alt_add(dfu, "virt", devstr, buf);
1344 log_debug("dfu_alt_add(virt,%s,%s) result %d\n", devstr, buf, ret);
1349 static int dfu_init_entities(struct stm32prog_data *data)
1352 int phase, i, alt_id;
1353 struct stm32prog_part_t *part;
1354 struct dfu_entity *dfu;
1358 alt_nb = 1; /* number of virtual = CMD*/
1360 if (IS_ENABLED(CONFIG_CMD_STM32PROG_OTP)) {
1361 /* OTP_SIZE_SMC = 0 if SMC is not supported */
1362 otp_size = OTP_SIZE_SMC;
1363 /* check if PTA BSEC is supported */
1364 ret = optee_ta_open(data);
1365 log_debug("optee_ta_open(PTA_NVMEM) result %d\n", ret);
1366 if (!ret && data->tee)
1367 otp_size = OTP_SIZE_TA;
1372 if (CONFIG_IS_ENABLED(DM_PMIC))
1373 alt_nb++; /* PMIC NVMEM*/
1375 if (data->part_nb == 0)
1376 alt_nb++; /* +1 for FlashLayout */
1378 for (i = 0; i < data->part_nb; i++) {
1379 if (data->part_array[i].target != STM32PROG_NONE)
1383 if (dfu_alt_init(alt_nb, &dfu))
1386 puts("DFU alt info setting: ");
1387 if (data->part_nb) {
1391 (phase <= PHASE_LAST_USER) &&
1392 (alt_id < alt_nb) && !ret;
1394 /* ordering alt setting by phase id */
1396 for (i = 0; i < data->part_nb; i++) {
1397 if (phase == data->part_array[i].id) {
1398 part = &data->part_array[i];
1404 if (part->target == STM32PROG_NONE)
1406 part->alt_id = alt_id;
1409 ret = stm32prog_alt_add(data, dfu, part);
1412 char buf[ALT_BUF_LEN];
1414 sprintf(buf, "@FlashLayout/0x%02x/1*256Ke ram %x 40000",
1415 PHASE_FLASHLAYOUT, CONFIG_SYS_LOAD_ADDR);
1416 ret = dfu_alt_add(dfu, "ram", NULL, buf);
1417 log_debug("dfu_alt_add(ram, NULL,%s) result %d\n", buf, ret);
1421 ret = stm32prog_alt_add_virt(dfu, "virtual", PHASE_CMD, CMD_SIZE);
1423 if (!ret && IS_ENABLED(CONFIG_CMD_STM32PROG_OTP) && otp_size)
1424 ret = stm32prog_alt_add_virt(dfu, "OTP", PHASE_OTP, otp_size);
1426 if (!ret && CONFIG_IS_ENABLED(DM_PMIC))
1427 ret = stm32prog_alt_add_virt(dfu, "PMIC", PHASE_PMIC, PMIC_SIZE);
1430 stm32prog_err("dfu init failed: %d", ret);
1434 dfu_show_entities();
1439 int stm32prog_otp_write(struct stm32prog_data *data, u32 offset, u8 *buffer,
1442 u32 otp_size = data->tee ? OTP_SIZE_TA : OTP_SIZE_SMC;
1443 log_debug("%s: %x %lx\n", __func__, offset, *size);
1445 if (!IS_ENABLED(CONFIG_CMD_STM32PROG_OTP)) {
1446 stm32prog_err("OTP update not supported");
1451 if (!data->otp_part) {
1452 data->otp_part = memalign(CONFIG_SYS_CACHELINE_SIZE, otp_size);
1453 if (!data->otp_part) {
1454 stm32prog_err("OTP write issue %d", -ENOMEM);
1461 memset(data->otp_part, 0, otp_size);
1463 if (offset + *size > otp_size)
1464 *size = otp_size - offset;
1466 memcpy((void *)((uintptr_t)data->otp_part + offset), buffer, *size);
1471 int stm32prog_otp_read(struct stm32prog_data *data, u32 offset, u8 *buffer,
1474 u32 otp_size = data->tee ? OTP_SIZE_TA : OTP_SIZE_SMC;
1477 if (!IS_ENABLED(CONFIG_CMD_STM32PROG_OTP)) {
1478 stm32prog_err("OTP update not supported");
1483 log_debug("%s: %x %lx\n", __func__, offset, *size);
1484 /* alway read for first packet */
1486 if (!data->otp_part)
1488 memalign(CONFIG_SYS_CACHELINE_SIZE, otp_size);
1490 if (!data->otp_part) {
1495 /* init struct with 0 */
1496 memset(data->otp_part, 0, otp_size);
1498 /* call the service */
1499 result = -EOPNOTSUPP;
1500 if (data->tee && CONFIG_IS_ENABLED(OPTEE))
1501 result = optee_ta_invoke(data, TA_NVMEM_READ, NVMEM_OTP,
1502 data->otp_part, OTP_SIZE_TA);
1503 else if (IS_ENABLED(CONFIG_ARM_SMCCC))
1504 result = stm32_smc_exec(STM32_SMC_BSEC, STM32_SMC_READ_ALL,
1505 (unsigned long)data->otp_part, 0);
1510 if (!data->otp_part) {
1515 if (offset + *size > otp_size)
1516 *size = otp_size - offset;
1517 memcpy(buffer, (void *)((uintptr_t)data->otp_part + offset), *size);
1521 stm32prog_err("OTP read issue %d", result);
1522 log_debug("%s: result %i\n", __func__, result);
1527 int stm32prog_otp_start(struct stm32prog_data *data)
1530 struct arm_smccc_res res;
1532 if (!IS_ENABLED(CONFIG_CMD_STM32PROG_OTP)) {
1533 stm32prog_err("OTP update not supported");
1538 if (!data->otp_part) {
1539 stm32prog_err("start OTP without data");
1543 result = -EOPNOTSUPP;
1544 if (data->tee && CONFIG_IS_ENABLED(OPTEE)) {
1545 result = optee_ta_invoke(data, TA_NVMEM_WRITE, NVMEM_OTP,
1546 data->otp_part, OTP_SIZE_TA);
1547 } else if (IS_ENABLED(CONFIG_ARM_SMCCC)) {
1548 arm_smccc_smc(STM32_SMC_BSEC, STM32_SMC_WRITE_ALL,
1549 (uintptr_t)data->otp_part, 0, 0, 0, 0, 0, &res);
1557 stm32prog_err("Provisioning");
1561 log_err("%s: OTP incorrect value (err = %ld)\n",
1567 log_err("%s: Failed to exec svc=%x op=%x in secure mode (err = %ld)\n",
1568 __func__, STM32_SMC_BSEC, STM32_SMC_WRITE_ALL, res.a0);
1573 free(data->otp_part);
1574 data->otp_part = NULL;
1576 stm32prog_err("OTP write issue %d", result);
1577 log_debug("%s: result %i\n", __func__, result);
1582 int stm32prog_pmic_write(struct stm32prog_data *data, u32 offset, u8 *buffer,
1585 log_debug("%s: %x %lx\n", __func__, offset, *size);
1588 memset(data->pmic_part, 0, PMIC_SIZE);
1590 if (offset + *size > PMIC_SIZE)
1591 *size = PMIC_SIZE - offset;
1593 memcpy(&data->pmic_part[offset], buffer, *size);
1598 int stm32prog_pmic_read(struct stm32prog_data *data, u32 offset, u8 *buffer,
1601 int result = 0, ret;
1602 struct udevice *dev;
1604 if (!IS_ENABLED(CONFIG_PMIC_STPMIC1)) {
1605 stm32prog_err("PMIC update not supported");
1610 log_debug("%s: %x %lx\n", __func__, offset, *size);
1611 ret = uclass_get_device_by_driver(UCLASS_MISC,
1612 DM_DRIVER_GET(stpmic1_nvm),
1617 /* alway request PMIC for first packet */
1619 /* init struct with 0 */
1620 memset(data->pmic_part, 0, PMIC_SIZE);
1622 ret = uclass_get_device_by_driver(UCLASS_MISC,
1623 DM_DRIVER_GET(stpmic1_nvm),
1628 ret = misc_read(dev, 0xF8, data->pmic_part, PMIC_SIZE);
1633 if (ret != PMIC_SIZE) {
1639 if (offset + *size > PMIC_SIZE)
1640 *size = PMIC_SIZE - offset;
1642 memcpy(buffer, &data->pmic_part[offset], *size);
1645 log_debug("%s: result %i\n", __func__, result);
1649 int stm32prog_pmic_start(struct stm32prog_data *data)
1652 struct udevice *dev;
1654 if (!IS_ENABLED(CONFIG_PMIC_STPMIC1)) {
1655 stm32prog_err("PMIC update not supported");
1660 ret = uclass_get_device_by_driver(UCLASS_MISC,
1661 DM_DRIVER_GET(stpmic1_nvm),
1666 return misc_write(dev, 0xF8, data->pmic_part, PMIC_SIZE);
1669 /* copy FSBL on NAND to improve reliability on NAND */
1670 static int stm32prog_copy_fsbl(struct stm32prog_part_t *part)
1674 struct image_header_s header;
1675 struct stm32_header_v2 raw_header; /* V2 size > v1 size */
1676 struct dfu_entity *dfu;
1679 if (part->target != STM32PROG_NAND &&
1680 part->target != STM32PROG_SPI_NAND)
1683 dfu = dfu_get_entity(part->alt_id);
1686 dfu_transaction_cleanup(dfu);
1687 size = sizeof(raw_header);
1688 ret = dfu->read_medium(dfu, 0, (void *)&raw_header, &size);
1692 stm32prog_header_check((ulong)&raw_header, &header);
1693 if (header.type != HEADER_STM32IMAGE &&
1694 header.type != HEADER_STM32IMAGE_V2)
1697 /* read header + payload */
1698 size = header.image_length + header.length;
1699 size = round_up(size, part->dev->mtd->erasesize);
1700 fsbl = calloc(1, size);
1703 ret = dfu->read_medium(dfu, 0, fsbl, &size);
1704 log_debug("%s read size=%lx ret=%d\n", __func__, size, ret);
1708 dfu_transaction_cleanup(dfu);
1710 for (i = part->bin_nb - 1; i > 0; i--) {
1712 /* write to the next erase block */
1713 ret = dfu->write_medium(dfu, offset, fsbl, &size);
1714 log_debug("%s copy at ofset=%lx size=%lx ret=%d",
1715 __func__, offset, size, ret);
1725 static void stm32prog_end_phase(struct stm32prog_data *data, u64 offset)
1727 if (data->phase == PHASE_FLASHLAYOUT) {
1728 #if defined(CONFIG_LEGACY_IMAGE_FORMAT)
1729 if (genimg_get_format((void *)CONFIG_SYS_LOAD_ADDR) == IMAGE_FORMAT_LEGACY) {
1730 data->script = CONFIG_SYS_LOAD_ADDR;
1731 data->phase = PHASE_END;
1732 log_notice("U-Boot script received\n");
1736 log_notice("\nFlashLayout received, size = %lld\n", offset);
1737 if (parse_flash_layout(data, CONFIG_SYS_LOAD_ADDR, offset))
1738 stm32prog_err("Layout: invalid FlashLayout");
1742 if (!data->cur_part)
1745 if (data->cur_part->target == STM32PROG_RAM) {
1746 if (data->cur_part->part_type == PART_SYSTEM)
1747 data->uimage = data->cur_part->addr;
1748 if (data->cur_part->part_type == PART_FILESYSTEM)
1749 data->dtb = data->cur_part->addr;
1750 if (data->cur_part->part_type == PART_BINARY) {
1751 data->initrd = data->cur_part->addr;
1752 data->initrd_size = offset;
1756 if (CONFIG_IS_ENABLED(MMC) &&
1757 data->cur_part->part_id < 0) {
1760 sprintf(cmdbuf, "mmc bootbus %d 0 0 0; mmc partconf %d 1 %d 0",
1761 data->cur_part->dev_id, data->cur_part->dev_id,
1762 -(data->cur_part->part_id));
1763 if (run_command(cmdbuf, 0)) {
1764 stm32prog_err("commands '%s' failed", cmdbuf);
1769 if (IS_ENABLED(CONFIG_MTD) &&
1770 data->cur_part->bin_nb > 1) {
1771 if (stm32prog_copy_fsbl(data->cur_part)) {
1772 stm32prog_err("%s (0x%x): copy of fsbl failed",
1773 data->cur_part->name, data->cur_part->id);
1779 void stm32prog_do_reset(struct stm32prog_data *data)
1781 if (data->phase == PHASE_RESET) {
1782 data->phase = PHASE_DO_RESET;
1783 puts("Reset requested\n");
1787 void stm32prog_next_phase(struct stm32prog_data *data)
1790 struct stm32prog_part_t *part;
1793 phase = data->phase;
1797 case PHASE_DO_RESET:
1801 /* found next selected partition */
1803 data->cur_part = NULL;
1804 data->phase = PHASE_END;
1808 if (phase > PHASE_LAST_USER)
1810 for (i = 0; i < data->part_nb; i++) {
1811 part = &data->part_array[i];
1812 if (part->id == phase) {
1813 if (IS_SELECT(part) && !IS_EMPTY(part)) {
1814 data->cur_part = part;
1815 data->phase = phase;
1823 if (data->phase == PHASE_END)
1824 puts("Phase=END\n");
1827 static int part_delete(struct stm32prog_data *data,
1828 struct stm32prog_part_t *part)
1831 unsigned long blks, blks_offset, blks_size;
1832 struct blk_desc *block_dev = NULL;
1836 printf("Erasing %s ", part->name);
1837 switch (part->target) {
1839 if (!IS_ENABLED(CONFIG_MMC)) {
1841 stm32prog_err("%s (0x%x): erase invalid",
1842 part->name, part->id);
1845 printf("on mmc %d: ", part->dev->dev_id);
1846 block_dev = mmc_get_blk_desc(part->dev->mmc);
1847 blks_offset = lldiv(part->addr, part->dev->mmc->read_bl_len);
1848 blks_size = lldiv(part->size, part->dev->mmc->read_bl_len);
1849 /* -1 or -2 : delete boot partition of MMC
1850 * need to switch to associated hwpart 1 or 2
1852 if (part->part_id < 0)
1853 if (blk_select_hwpart_devnum(UCLASS_MMC,
1858 blks = blk_derase(block_dev, blks_offset, blks_size);
1860 /* return to user partition */
1861 if (part->part_id < 0)
1862 blk_select_hwpart_devnum(UCLASS_MMC,
1863 part->dev->dev_id, 0);
1864 if (blks != blks_size) {
1866 stm32prog_err("%s (0x%x): MMC erase failed",
1867 part->name, part->id);
1871 case STM32PROG_NAND:
1872 case STM32PROG_SPI_NAND:
1873 if (!IS_ENABLED(CONFIG_MTD)) {
1875 stm32prog_err("%s (0x%x): erase invalid",
1876 part->name, part->id);
1879 get_mtd_by_target(devstr, part->target, part->dev->dev_id);
1880 printf("on %s: ", devstr);
1881 sprintf(cmdbuf, "mtd erase %s 0x%llx 0x%llx",
1882 devstr, part->addr, part->size);
1883 if (run_command(cmdbuf, 0)) {
1885 stm32prog_err("%s (0x%x): MTD erase commands failed (%s)",
1886 part->name, part->id, cmdbuf);
1891 memset((void *)(uintptr_t)part->addr, 0, (size_t)part->size);
1895 stm32prog_err("%s (0x%x): erase invalid", part->name, part->id);
1904 static void stm32prog_devices_init(struct stm32prog_data *data)
1908 struct stm32prog_part_t *part;
1910 ret = treat_partition_list(data);
1914 /* empty flashlayout */
1918 /* initialize the selected device */
1919 for (i = 0; i < data->dev_nb; i++) {
1920 ret = init_device(data, &data->dev[i]);
1925 /* delete RAW partition before create partition */
1926 for (i = 0; i < data->part_nb; i++) {
1927 part = &data->part_array[i];
1929 if (part->part_type != RAW_IMAGE)
1932 if (!IS_SELECT(part) || !IS_DELETE(part))
1935 ret = part_delete(data, part);
1940 if (IS_ENABLED(CONFIG_MMC)) {
1941 ret = create_gpt_partitions(data);
1946 /* delete partition GPT or MTD */
1947 for (i = 0; i < data->part_nb; i++) {
1948 part = &data->part_array[i];
1950 if (part->part_type == RAW_IMAGE)
1953 if (!IS_SELECT(part) || !IS_DELETE(part))
1956 ret = part_delete(data, part);
1967 int stm32prog_dfu_init(struct stm32prog_data *data)
1969 /* init device if no error */
1971 stm32prog_devices_init(data);
1974 stm32prog_next_phase(data);
1976 /* prepare DFU for device read/write */
1977 dfu_free_entities();
1978 return dfu_init_entities(data);
1981 int stm32prog_init(struct stm32prog_data *data, uintptr_t addr, ulong size)
1983 memset(data, 0x0, sizeof(*data));
1984 data->read_phase = PHASE_RESET;
1985 data->phase = PHASE_FLASHLAYOUT;
1987 return parse_flash_layout(data, addr, size);
1990 void stm32prog_clean(struct stm32prog_data *data)
1993 dfu_free_entities();
1994 free(data->part_array);
1995 free(data->otp_part);
1998 if (CONFIG_IS_ENABLED(OPTEE) && data->tee) {
1999 tee_close_session(data->tee, data->tee_session);
2001 data->tee_session = 0x0;
2005 /* DFU callback: used after serial and direct DFU USB access */
2006 void dfu_flush_callback(struct dfu_entity *dfu)
2008 if (!stm32prog_data)
2011 if (dfu->dev_type == DFU_DEV_VIRT) {
2012 if (dfu->data.virt.dev_num == PHASE_OTP)
2013 stm32prog_otp_start(stm32prog_data);
2014 else if (dfu->data.virt.dev_num == PHASE_PMIC)
2015 stm32prog_pmic_start(stm32prog_data);
2019 if (dfu->dev_type == DFU_DEV_RAM) {
2020 if (dfu->alt == 0 &&
2021 stm32prog_data->phase == PHASE_FLASHLAYOUT) {
2022 stm32prog_end_phase(stm32prog_data, dfu->offset);
2023 /* waiting DFU DETACH for reenumeration */
2027 if (!stm32prog_data->cur_part)
2030 if (dfu->alt == stm32prog_data->cur_part->alt_id) {
2031 stm32prog_end_phase(stm32prog_data, dfu->offset);
2032 stm32prog_next_phase(stm32prog_data);
2036 void dfu_initiated_callback(struct dfu_entity *dfu)
2038 if (!stm32prog_data)
2041 if (!stm32prog_data->cur_part)
2044 /* force the saved offset for the current partition */
2045 if (dfu->alt == stm32prog_data->cur_part->alt_id) {
2046 dfu->offset = stm32prog_data->offset;
2047 stm32prog_data->dfu_seq = 0;
2048 log_debug("dfu offset = 0x%llx\n", dfu->offset);
2052 void dfu_error_callback(struct dfu_entity *dfu, const char *msg)
2054 struct stm32prog_data *data = stm32prog_data;
2056 if (!stm32prog_data)
2059 if (!stm32prog_data->cur_part)
2062 if (dfu->alt == stm32prog_data->cur_part->alt_id)