drivers/pinctrl/rockchip/pinctrl-rockchip-core.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2019 Rockchip Electronics Co., Ltd
   4  */
   5
   6 #include <common.h>
   7 #include <dm.h>
   8 #include <log.h>
   9 #include <dm/pinctrl.h>
  10 #include <regmap.h>
  11 #include <syscon.h>
  12 #include <fdtdec.h>
  13 #include <linux/bitops.h>
  14 #include <linux/libfdt.h>
  15 #include <asm/global_data.h>
  16
  17 #include "pinctrl-rockchip.h"
  18
  19 #define MAX_ROCKCHIP_PINS_ENTRIES       30
  20 #define MAX_ROCKCHIP_GPIO_PER_BANK      32
  21 #define RK_FUNC_GPIO                    0
  22
  23 static int rockchip_verify_config(struct udevice *dev, u32 bank, u32 pin)
  24 {
  25         struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
  26         struct rockchip_pin_ctrl *ctrl = priv->ctrl;
  27
  28         if (bank >= ctrl->nr_banks) {
  29                 debug("pin conf bank %d >= nbanks %d\n", bank, ctrl->nr_banks);
  30                 return -EINVAL;
  31         }
  32
  33         if (pin >= MAX_ROCKCHIP_GPIO_PER_BANK) {
  34                 debug("pin conf pin %d >= %d\n", pin,
  35                       MAX_ROCKCHIP_GPIO_PER_BANK);
  36                 return -EINVAL;
  37         }
  38
  39         return 0;
  40 }
  41
  42 void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
  43                                int *reg, u8 *bit, int *mask)
  44 {
  45         struct rockchip_pinctrl_priv *priv = bank->priv;
  46         struct rockchip_pin_ctrl *ctrl = priv->ctrl;
  47         struct rockchip_mux_recalced_data *data;
  48         int i;
  49
  50         for (i = 0; i < ctrl->niomux_recalced; i++) {
  51                 data = &ctrl->iomux_recalced[i];
  52                 if (data->num == bank->bank_num &&
  53                     data->pin == pin)
  54                         break;
  55         }
  56
  57         if (i >= ctrl->niomux_recalced)
  58                 return;
  59
  60         *reg = data->reg;
  61         *mask = data->mask;
  62         *bit = data->bit;
  63 }
  64
  65 static enum rockchip_pin_route_type
  66 rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
  67                        int mux, u32 *reg, u32 *value)
  68 {
  69         struct rockchip_pinctrl_priv *priv = bank->priv;
  70         struct rockchip_pin_ctrl *ctrl = priv->ctrl;
  71         struct rockchip_mux_route_data *data;
  72         int i;
  73
  74         for (i = 0; i < ctrl->niomux_routes; i++) {
  75                 data = &ctrl->iomux_routes[i];
  76                 if (data->bank_num == bank->bank_num &&
  77                     data->pin == pin && data->func == mux)
  78                         break;
  79         }
  80
  81         if (i >= ctrl->niomux_routes)
  82                 return ROUTE_TYPE_INVALID;
  83
  84         *reg = data->route_offset;
  85         *value = data->route_val;
  86
  87         return data->route_type;
  88 }
  89
  90 int rockchip_get_mux_data(int mux_type, int pin, u8 *bit, int *mask)
  91 {
  92         int offset = 0;
  93
  94         if (mux_type & IOMUX_WIDTH_4BIT) {
  95                 if ((pin % 8) >= 4)
  96                         offset = 0x4;
  97                 *bit = (pin % 4) * 4;
  98                 *mask = 0xf;
  99         } else if (mux_type & IOMUX_WIDTH_3BIT) {
 100                 /*
 101                  * pin0 ~ pin4 are at first register, and
 102                  * pin5 ~ pin7 are at second register.
 103                  */
 104                 if ((pin % 8) >= 5)
 105                         offset = 0x4;
 106                 *bit = (pin % 8 % 5) * 3;
 107                 *mask = 0x7;
 108         } else {
 109                 *bit = (pin % 8) * 2;
 110                 *mask = 0x3;
 111         }
 112
 113         return offset;
 114 }
 115
 116 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
 117 {
 118         struct rockchip_pinctrl_priv *priv = bank->priv;
 119         int iomux_num = (pin / 8);
 120         struct regmap *regmap;
 121         unsigned int val;
 122         int reg, ret, mask, mux_type;
 123         u8 bit;
 124
 125         if (iomux_num > 3)
 126                 return -EINVAL;
 127
 128         if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
 129                 debug("pin %d is unrouted\n", pin);
 130                 return -EINVAL;
 131         }
 132
 133         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
 134                 return RK_FUNC_GPIO;
 135
 136         regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
 137                                 ? priv->regmap_pmu : priv->regmap_base;
 138
 139         /* get basic quadrupel of mux registers and the correct reg inside */
 140         mux_type = bank->iomux[iomux_num].type;
 141         reg = bank->iomux[iomux_num].offset;
 142         reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
 143
 144         if (bank->recalced_mask & BIT(pin))
 145                 rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
 146
 147         ret = regmap_read(regmap, reg, &val);
 148         if (ret)
 149                 return ret;
 150
 151         return ((val >> bit) & mask);
 152 }
 153
 154 static int rockchip_pinctrl_get_gpio_mux(struct udevice *dev, int banknum,
 155                                          int index)
 156 {       struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
 157         struct rockchip_pin_ctrl *ctrl = priv->ctrl;
 158
 159         return rockchip_get_mux(&ctrl->pin_banks[banknum], index);
 160 }
 161
 162 static int rockchip_verify_mux(struct rockchip_pin_bank *bank,
 163                                int pin, int mux)
 164 {
 165         int iomux_num = (pin / 8);
 166
 167         if (iomux_num > 3)
 168                 return -EINVAL;
 169
 170         if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
 171                 debug("pin %d is unrouted\n", pin);
 172                 return -EINVAL;
 173         }
 174
 175         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
 176                 if (mux != IOMUX_GPIO_ONLY) {
 177                         debug("pin %d only supports a gpio mux\n", pin);
 178                         return -ENOTSUPP;
 179                 }
 180         }
 181
 182         return 0;
 183 }
 184
 185 /*
 186  * Set a new mux function for a pin.
 187  *
 188  * The register is divided into the upper and lower 16 bit. When changing
 189  * a value, the previous register value is not read and changed. Instead
 190  * it seems the changed bits are marked in the upper 16 bit, while the
 191  * changed value gets set in the same offset in the lower 16 bit.
 192  * All pin settings seem to be 2 bit wide in both the upper and lower
 193  * parts.
 194  * @bank: pin bank to change
 195  * @pin: pin to change
 196  * @mux: new mux function to set
 197  */
 198 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
 199 {
 200         struct rockchip_pinctrl_priv *priv = bank->priv;
 201         struct rockchip_pin_ctrl *ctrl = priv->ctrl;
 202         int iomux_num = (pin / 8);
 203         int ret;
 204
 205         ret = rockchip_verify_mux(bank, pin, mux);
 206         if (ret < 0)
 207                 return ret;
 208
 209         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
 210                 return 0;
 211
 212         debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
 213
 214         if (!ctrl->set_mux)
 215                 return -ENOTSUPP;
 216
 217         ret = ctrl->set_mux(bank, pin, mux);
 218         if (ret)
 219                 return ret;
 220
 221         if (bank->route_mask & BIT(pin)) {
 222                 struct regmap *regmap;
 223                 u32 route_reg = 0, route_val = 0;
 224
 225                 ret = rockchip_get_mux_route(bank, pin, mux,
 226                                              &route_reg, &route_val);
 227                 switch (ret) {
 228                 case ROUTE_TYPE_DEFAULT:
 229                         if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
 230                                 regmap = priv->regmap_pmu;
 231                         else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU)
 232                                 regmap = (pin % 8 < 4) ? priv->regmap_pmu : priv->regmap_base;
 233                         else
 234                                 regmap = priv->regmap_base;
 235
 236                         regmap_write(regmap, route_reg, route_val);
 237                         break;
 238                 case ROUTE_TYPE_TOPGRF:
 239                         regmap_write(priv->regmap_base, route_reg, route_val);
 240                         break;
 241                 case ROUTE_TYPE_PMUGRF:
 242                         regmap_write(priv->regmap_pmu, route_reg, route_val);
 243                         break;
 244                 case ROUTE_TYPE_INVALID:
 245                         fallthrough;
 246                 default:
 247                         break;
 248                 }
 249         }
 250
 251         return 0;
 252 }
 253
 254 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
 255         { 2, 4, 8, 12, -1, -1, -1, -1 },
 256         { 3, 6, 9, 12, -1, -1, -1, -1 },
 257         { 5, 10, 15, 20, -1, -1, -1, -1 },
 258         { 4, 6, 8, 10, 12, 14, 16, 18 },
 259         { 4, 7, 10, 13, 16, 19, 22, 26 }
 260 };
 261
 262 int rockchip_translate_drive_value(int type, int strength)
 263 {
 264         int i, ret;
 265
 266         ret = -EINVAL;
 267         for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[type]); i++) {
 268                 if (rockchip_perpin_drv_list[type][i] == strength) {
 269                         ret = i;
 270                         break;
 271                 } else if (rockchip_perpin_drv_list[type][i] < 0) {
 272                         ret = rockchip_perpin_drv_list[type][i];
 273                         break;
 274                 }
 275         }
 276
 277         return ret;
 278 }
 279
 280 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
 281                                      int pin_num, int strength)
 282 {
 283         struct rockchip_pinctrl_priv *priv = bank->priv;
 284         struct rockchip_pin_ctrl *ctrl = priv->ctrl;
 285
 286         debug("setting drive of GPIO%d-%d to %d\n", bank->bank_num,
 287               pin_num, strength);
 288
 289         if (!ctrl->set_drive)
 290                 return -ENOTSUPP;
 291
 292         return ctrl->set_drive(bank, pin_num, strength);
 293 }
 294
 295 static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
 296         {
 297                 PIN_CONFIG_BIAS_DISABLE,
 298                 PIN_CONFIG_BIAS_PULL_UP,
 299                 PIN_CONFIG_BIAS_PULL_DOWN,
 300                 PIN_CONFIG_BIAS_BUS_HOLD
 301         },
 302         {
 303                 PIN_CONFIG_BIAS_DISABLE,
 304                 PIN_CONFIG_BIAS_PULL_DOWN,
 305                 PIN_CONFIG_BIAS_DISABLE,
 306                 PIN_CONFIG_BIAS_PULL_UP
 307         },
 308 };
 309
 310 int rockchip_translate_pull_value(int type, int pull)
 311 {
 312         int i, ret;
 313
 314         ret = -EINVAL;
 315         for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[type]);
 316                 i++) {
 317                 if (rockchip_pull_list[type][i] == pull) {
 318                         ret = i;
 319                         break;
 320                 }
 321         }
 322
 323         return ret;
 324 }
 325
 326 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
 327                              int pin_num, int pull)
 328 {
 329         struct rockchip_pinctrl_priv *priv = bank->priv;
 330         struct rockchip_pin_ctrl *ctrl = priv->ctrl;
 331
 332         debug("setting pull of GPIO%d-%d to %d\n", bank->bank_num,
 333               pin_num, pull);
 334
 335         if (!ctrl->set_pull)
 336                 return -ENOTSUPP;
 337
 338         return ctrl->set_pull(bank, pin_num, pull);
 339 }
 340
 341 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
 342                                 int pin_num, int enable)
 343 {
 344         struct rockchip_pinctrl_priv *priv = bank->priv;
 345         struct rockchip_pin_ctrl *ctrl = priv->ctrl;
 346
 347         debug("setting input schmitt of GPIO%d-%d to %d\n", bank->bank_num,
 348               pin_num, enable);
 349
 350         if (!ctrl->set_schmitt)
 351                 return -ENOTSUPP;
 352
 353         return ctrl->set_schmitt(bank, pin_num, enable);
 354 }
 355
 356 /* set the pin config settings for a specified pin */
 357 static int rockchip_pinconf_set(struct rockchip_pin_bank *bank,
 358                                 u32 pin, u32 param, u32 arg)
 359 {
 360         int rc;
 361
 362         switch (param) {
 363         case PIN_CONFIG_BIAS_DISABLE:
 364         case PIN_CONFIG_BIAS_PULL_UP:
 365         case PIN_CONFIG_BIAS_PULL_DOWN:
 366         case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
 367         case PIN_CONFIG_BIAS_BUS_HOLD:
 368                 rc = rockchip_set_pull(bank, pin, param);
 369                 if (rc)
 370                         return rc;
 371                 break;
 372
 373         case PIN_CONFIG_DRIVE_STRENGTH:
 374                 rc = rockchip_set_drive_perpin(bank, pin, arg);
 375                 if (rc < 0)
 376                         return rc;
 377                 break;
 378
 379         case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 380                 rc = rockchip_set_schmitt(bank, pin, arg);
 381                 if (rc < 0)
 382                         return rc;
 383                 break;
 384
 385         default:
 386                 break;
 387         }
 388
 389         return 0;
 390 }
 391
 392 static const struct pinconf_param rockchip_conf_params[] = {
 393         { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
 394         { "bias-bus-hold", PIN_CONFIG_BIAS_BUS_HOLD, 0 },
 395         { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
 396         { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
 397         { "bias-pull-pin-default", PIN_CONFIG_BIAS_PULL_PIN_DEFAULT, 1 },
 398         { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
 399         { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 },
 400         { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 },
 401 };
 402
 403 static int rockchip_pinconf_prop_name_to_param(const char *property,
 404                                                u32 *default_value)
 405 {
 406         const struct pinconf_param *p, *end;
 407
 408         p = rockchip_conf_params;
 409         end = p + sizeof(rockchip_conf_params) / sizeof(struct pinconf_param);
 410
 411         /* See if this pctldev supports this parameter */
 412         for (; p < end; p++) {
 413                 if (!strcmp(property, p->property)) {
 414                         *default_value = p->default_value;
 415                         return p->param;
 416                 }
 417         }
 418
 419         *default_value = 0;
 420         return -EPERM;
 421 }
 422
 423 static int rockchip_pinctrl_set_state(struct udevice *dev,
 424                                       struct udevice *config)
 425 {
 426         struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
 427         struct rockchip_pin_ctrl *ctrl = priv->ctrl;
 428         u32 cells[MAX_ROCKCHIP_PINS_ENTRIES * 4];
 429         u32 bank, pin, mux, conf, arg, default_val;
 430         int ret, count, i;
 431         const char *prop_name;
 432         const void *value;
 433         int prop_len, param;
 434         const u32 *data;
 435         ofnode node;
 436 #ifdef CONFIG_OF_LIVE
 437         const struct device_node *np;
 438         struct property *pp;
 439 #else
 440         int property_offset, pcfg_node;
 441         const void *blob = gd->fdt_blob;
 442 #endif
 443         data = dev_read_prop(config, "rockchip,pins", &count);
 444         if (count < 0) {
 445                 debug("%s: bad array size %d\n", __func__, count);
 446                 return -EINVAL;
 447         }
 448
 449         count /= sizeof(u32);
 450         if (count > MAX_ROCKCHIP_PINS_ENTRIES * 4) {
 451                 debug("%s: unsupported pins array count %d\n",
 452                       __func__, count);
 453                 return -EINVAL;
 454         }
 455
 456         for (i = 0; i < count; i++)
 457                 cells[i] = fdt32_to_cpu(data[i]);
 458
 459         for (i = 0; i < (count >> 2); i++) {
 460                 bank = cells[4 * i + 0];
 461                 pin = cells[4 * i + 1];
 462                 mux = cells[4 * i + 2];
 463                 conf = cells[4 * i + 3];
 464
 465                 ret = rockchip_verify_config(dev, bank, pin);
 466                 if (ret)
 467                         return ret;
 468
 469                 ret = rockchip_set_mux(&ctrl->pin_banks[bank], pin, mux);
 470                 if (ret)
 471                         return ret;
 472
 473                 node = ofnode_get_by_phandle(conf);
 474                 if (!ofnode_valid(node))
 475                         return -ENODEV;
 476 #ifdef CONFIG_OF_LIVE
 477                 np = ofnode_to_np(node);
 478                 for (pp = np->properties; pp; pp = pp->next) {
 479                         prop_name = pp->name;
 480                         prop_len = pp->length;
 481                         value = pp->value;
 482 #else
 483                 pcfg_node = ofnode_to_offset(node);
 484                 fdt_for_each_property_offset(property_offset, blob, pcfg_node) {
 485                         value = fdt_getprop_by_offset(blob, property_offset,
 486                                                       &prop_name, &prop_len);
 487                         if (!value)
 488                                 return -ENOENT;
 489 #endif
 490                         param = rockchip_pinconf_prop_name_to_param(prop_name,
 491                                                                     &default_val);
 492                         if (param < 0)
 493                                 break;
 494
 495                         if (prop_len >= sizeof(fdt32_t))
 496                                 arg = fdt32_to_cpu(*(fdt32_t *)value);
 497                         else
 498                                 arg = default_val;
 499
 500                         ret = rockchip_pinconf_set(&ctrl->pin_banks[bank], pin,
 501                                                    param, arg);
 502                         if (ret) {
 503                                 debug("%s: rockchip_pinconf_set fail: %d\n",
 504                                       __func__, ret);
 505                                 return ret;
 506                         }
 507                 }
 508         }
 509
 510         return 0;
 511 }
 512
 513 const struct pinctrl_ops rockchip_pinctrl_ops = {
 514         .set_state                      = rockchip_pinctrl_set_state,
 515         .get_gpio_mux                   = rockchip_pinctrl_get_gpio_mux,
 516 };
 517
 518 /* retrieve the soc specific data */
 519 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(struct udevice *dev)
 520 {
 521         struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
 522         struct rockchip_pin_ctrl *ctrl =
 523                         (struct rockchip_pin_ctrl *)dev_get_driver_data(dev);
 524         struct rockchip_pin_bank *bank;
 525         int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
 526
 527         grf_offs = ctrl->grf_mux_offset;
 528         pmu_offs = ctrl->pmu_mux_offset;
 529         drv_pmu_offs = ctrl->pmu_drv_offset;
 530         drv_grf_offs = ctrl->grf_drv_offset;
 531         bank = ctrl->pin_banks;
 532
 533         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
 534                 int bank_pins = 0;
 535
 536                 bank->priv = priv;
 537                 bank->pin_base = ctrl->nr_pins;
 538                 ctrl->nr_pins += bank->nr_pins;
 539
 540                 /* calculate iomux and drv offsets */
 541                 for (j = 0; j < 4; j++) {
 542                         struct rockchip_iomux *iom = &bank->iomux[j];
 543                         struct rockchip_drv *drv = &bank->drv[j];
 544                         int inc;
 545
 546                         if (bank_pins >= bank->nr_pins)
 547                                 break;
 548
 549                         /* preset iomux offset value, set new start value */
 550                         if (iom->offset >= 0) {
 551                                 if (iom->type & IOMUX_SOURCE_PMU)
 552                                         pmu_offs = iom->offset;
 553                                 else
 554                                         grf_offs = iom->offset;
 555                         } else { /* set current iomux offset */
 556                                 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
 557                                                         pmu_offs : grf_offs;
 558                         }
 559
 560                         /* preset drv offset value, set new start value */
 561                         if (drv->offset >= 0) {
 562                                 if (iom->type & IOMUX_SOURCE_PMU)
 563                                         drv_pmu_offs = drv->offset;
 564                                 else
 565                                         drv_grf_offs = drv->offset;
 566                         } else { /* set current drv offset */
 567                                 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
 568                                                 drv_pmu_offs : drv_grf_offs;
 569                         }
 570
 571                         debug("bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
 572                               i, j, iom->offset, drv->offset);
 573
 574                         /*
 575                          * Increase offset according to iomux width.
 576                          * 4bit iomux'es are spread over two registers.
 577                          */
 578                         inc = (iom->type & (IOMUX_WIDTH_4BIT |
 579                                             IOMUX_WIDTH_3BIT |
 580                                             IOMUX_8WIDTH_2BIT)) ? 8 : 4;
 581                         if ((iom->type & IOMUX_SOURCE_PMU) || (iom->type & IOMUX_L_SOURCE_PMU))
 582                                 pmu_offs += inc;
 583                         else
 584                                 grf_offs += inc;
 585
 586                         /*
 587                          * Increase offset according to drv width.
 588                          * 3bit drive-strenth'es are spread over two registers.
 589                          */
 590                         if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
 591                             (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
 592                                 inc = 8;
 593                         else
 594                                 inc = 4;
 595
 596                         if (iom->type & IOMUX_SOURCE_PMU)
 597                                 drv_pmu_offs += inc;
 598                         else
 599                                 drv_grf_offs += inc;
 600
 601                         bank_pins += 8;
 602                 }
 603
 604                 /* calculate the per-bank recalced_mask */
 605                 for (j = 0; j < ctrl->niomux_recalced; j++) {
 606                         int pin = 0;
 607
 608                         if (ctrl->iomux_recalced[j].num == bank->bank_num) {
 609                                 pin = ctrl->iomux_recalced[j].pin;
 610                                 bank->recalced_mask |= BIT(pin);
 611                         }
 612                 }
 613
 614                 /* calculate the per-bank route_mask */
 615                 for (j = 0; j < ctrl->niomux_routes; j++) {
 616                         int pin = 0;
 617
 618                         if (ctrl->iomux_routes[j].bank_num == bank->bank_num) {
 619                                 pin = ctrl->iomux_routes[j].pin;
 620                                 bank->route_mask |= BIT(pin);
 621                         }
 622                 }
 623         }
 624
 625         return ctrl;
 626 }
 627
 628 int rockchip_pinctrl_probe(struct udevice *dev)
 629 {
 630         struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
 631         struct rockchip_pin_ctrl *ctrl;
 632         struct udevice *syscon;
 633         struct regmap *regmap;
 634         int ret = 0;
 635
 636         /* get rockchip grf syscon phandle */
 637         ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf",
 638                                            &syscon);
 639         if (ret) {
 640                 debug("unable to find rockchip,grf syscon device (%d)\n", ret);
 641                 return ret;
 642         }
 643
 644         /* get grf-reg base address */
 645         regmap = syscon_get_regmap(syscon);
 646         if (!regmap) {
 647                 debug("unable to find rockchip grf regmap\n");
 648                 return -ENODEV;
 649         }
 650         priv->regmap_base = regmap;
 651
 652         /* option: get pmu-reg base address */
 653         ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pmu",
 654                                            &syscon);
 655         if (!ret) {
 656                 /* get pmugrf-reg base address */
 657                 regmap = syscon_get_regmap(syscon);
 658                 if (!regmap) {
 659                         debug("unable to find rockchip pmu regmap\n");
 660                         return -ENODEV;
 661                 }
 662                 priv->regmap_pmu = regmap;
 663         }
 664
 665         ctrl = rockchip_pinctrl_get_soc_data(dev);
 666         if (!ctrl) {
 667                 debug("driver data not available\n");
 668                 return -EINVAL;
 669         }
 670
 671         priv->ctrl = ctrl;
 672         return 0;
 673 }