1 /* SPDX-License-Identifier: GPL-2.0+ */
7 * Copyright (c) 2011 IDS GmbH, Germany
15 * High Level Configuration Options
17 #define CONFIG_FSL_ELBC
19 #define CONFIG_BOOT_RETRY_TIME 900
20 #define CONFIG_BOOT_RETRY_MIN 30
21 #define CONFIG_RESET_TO_RETRY
23 #define CONFIG_SYS_IMMR 0xF0000000
25 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
26 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
28 #define CONFIG_SYS_SICRH 0x00000000
29 #define CONFIG_SYS_SICRL (SICRL_LBC | SICRL_SPI_D)
31 #define CONFIG_HWCONFIG
33 #define CONFIG_SYS_HID0_INIT 0x000000000
34 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK |\
35 HID0_ENABLE_INSTRUCTION_CACHE |\
36 HID0_DISABLE_DYNAMIC_POWER_MANAGMENT)
38 #define CONFIG_SYS_HID2 (HID2_HBE | 0x00020000)
41 * Definitions for initial stack pointer and data area (in DCACHE )
43 #define CONFIG_SYS_INIT_RAM_LOCK
44 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000
45 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in DPRAM */
46 #define CONFIG_SYS_GBL_DATA_SIZE 0x100
47 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
48 - CONFIG_SYS_GBL_DATA_SIZE)
49 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
52 * Local Bus LCRR and LBCR regs
54 #define CONFIG_SYS_LCRR_EADC LCRR_EADC_1
55 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
56 #define CONFIG_SYS_LBC_LBCR (0x00040000 |\
57 (0xFF << LBCR_BMT_SHIFT) |\
60 #define CONFIG_SYS_LBC_MRTPR 0x20000000
63 * Internal Definitions
68 #define CONFIG_SYS_DDR_BASE 0x00000000
69 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
70 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
73 * Manually set up DDR parameters,
74 * as this board has not the SPD connected to I2C.
76 #define CONFIG_SYS_DDR_SIZE 256 /* MB */
77 #define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN |\
79 CSCONFIG_ROW_BIT_13 |\
82 #define CONFIG_SYS_DDR_CONFIG_256 (CONFIG_SYS_DDR_CONFIG | \
85 #define CONFIG_SYS_DDR_TIMING_3 (1 << 16) /* ext refrec */
86 #define CONFIG_SYS_DDR_TIMING_0 ((3 << TIMING_CFG0_RWT_SHIFT) |\
87 (3 << TIMING_CFG0_WRT_SHIFT) |\
88 (3 << TIMING_CFG0_RRT_SHIFT) |\
89 (3 << TIMING_CFG0_WWT_SHIFT) |\
90 (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) |\
91 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) |\
92 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
93 (2 << TIMING_CFG0_MRS_CYC_SHIFT))
94 #define CONFIG_SYS_DDR_TIMING_1 ((4 << TIMING_CFG1_PRETOACT_SHIFT) |\
95 (12 << TIMING_CFG1_ACTTOPRE_SHIFT) |\
96 (4 << TIMING_CFG1_ACTTORW_SHIFT) |\
97 (7 << TIMING_CFG1_CASLAT_SHIFT) |\
98 (4 << TIMING_CFG1_REFREC_SHIFT) |\
99 (4 << TIMING_CFG1_WRREC_SHIFT) |\
100 (2 << TIMING_CFG1_ACTTOACT_SHIFT) |\
101 (2 << TIMING_CFG1_WRTORD_SHIFT))
102 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) |\
103 (5 << TIMING_CFG2_CPO_SHIFT) |\
104 (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) |\
105 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) |\
106 (0 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) |\
107 (1 << TIMING_CFG2_CKE_PLS_SHIFT) |\
108 (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
110 #define CONFIG_SYS_DDR_INTERVAL ((0x800 << SDRAM_INTERVAL_REFINT_SHIFT) |\
111 (0x800 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
113 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN |\
114 SDRAM_CFG_2T_EN | SDRAM_CFG_HSE |\
116 SDRAM_CFG_SDRAM_TYPE_DDR2)
118 #define CONFIG_SYS_SDRAM_CFG2 0x00401000
119 #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) |\
120 (0x0242 << SDRAM_MODE_SD_SHIFT))
121 #define CONFIG_SYS_DDR_MODE_2 0x00000000
122 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075
123 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN |\
139 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
140 #define CONFIG_FLASH_SHOW_PROGRESS 50
142 #define CONFIG_SYS_FLASH_BASE 0xFF800000
143 #define CONFIG_SYS_FLASH_SIZE 8
145 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\
150 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
156 #define CONFIG_SYS_MAX_FLASH_BANKS 1
157 #define CONFIG_SYS_MAX_FLASH_SECT 128
159 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000
160 #define CONFIG_SYS_FLASH_WRITE_TOUT 500
165 #define CONFIG_SYS_NAND_BASE 0xE1000000
166 #define CONFIG_SYS_MAX_NAND_DEVICE 1
167 #define CONFIG_SYS_NAND_MAX_CHIPS 1
168 #define CONFIG_NAND_FSL_ELBC
169 #define CONFIG_SYS_NAND_PAGE_SIZE (2048)
170 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
171 #define NAND_CACHE_PAGES 64
173 #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_NAND_BASE) |\
174 (2<<BR_DECC_SHIFT) |\
179 #define CONFIG_SYS_OR1_PRELIM (0xFFFF8000 |\
192 #define CONFIG_SYS_MRAM_BASE 0xE2000000
193 #define CONFIG_SYS_MRAM_SIZE 0x20000 /* 128 Kb */
195 #define CONFIG_SYS_OR_TIMING_MRAM
197 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_MRAM_BASE |\
202 #define CONFIG_SYS_OR2_PRELIM 0xFFFE0C74
207 #define CONFIG_SYS_CPLD_BASE 0xE3000000
208 #define CONFIG_SYS_CPLD_SIZE 0x8000
210 #define CONFIG_SYS_OR_TIMING_MRAM
212 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CPLD_BASE |\
217 #define CONFIG_SYS_OR3_PRELIM 0xFFFF8814
222 #define CONFIG_WATCHDOG 1
223 #define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
228 #define CONFIG_SYS_I2C
229 #define CONFIG_SYS_I2C_FSL
230 #define CONFIG_SYS_FSL_I2C_SPEED 400000
231 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
232 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
233 #define CONFIG_RTC_PCF8563
234 #define CONFIG_SYS_I2C_RTC_ADDR 0x51
240 #define CONFIG_HAS_ETH0
241 #define CONFIG_TSEC1_NAME "TSEC0"
242 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
243 #define TSEC1_PHY_ADDR 0x1
244 #define TSEC1_FLAGS TSEC_GIGABIT
245 #define TSEC1_PHYIDX 0
249 #define CONFIG_HAS_ETH1
250 #define CONFIG_TSEC2_NAME "TSEC1"
251 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
252 #define TSEC2_PHY_ADDR 0x3
253 #define TSEC2_FLAGS TSEC_GIGABIT
254 #define TSEC2_PHYIDX 0
256 #define CONFIG_ETHPRIME "TSEC1"
261 #define CONFIG_SYS_NS16550_SERIAL
262 #define CONFIG_SYS_NS16550_REG_SIZE 1
264 #define CONFIG_SYS_BAUDRATE_TABLE \
265 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
266 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
267 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
268 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
270 #define CONFIG_HAS_FSL_DR_USB
271 #define CONFIG_SYS_SCCR_USBDRCM 3
274 * U-Boot environment setup
276 #define CONFIG_BOOTP_BOOTFILESIZE
279 * The reserved memory
281 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
282 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
283 #define CONFIG_SYS_MALLOC_LEN (8 * 1024 * 1024)
286 * Environment Configuration
288 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \
289 + CONFIG_SYS_MONITOR_LEN)
290 #define CONFIG_ENV_SIZE 0x20000
291 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
292 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
294 #define CONFIG_NETDEV eth1
295 #define CONFIG_HOSTNAME "ids8313"
296 #define CONFIG_ROOTPATH "/opt/eldk-4.2/ppc_6xx"
297 #define CONFIG_BOOTFILE "ids8313/uImage"
298 #define CONFIG_UBOOTPATH "ids8313/u-boot.bin"
299 #define CONFIG_FDTFILE "ids8313/ids8313.dtb"
300 #define CONFIG_LOADADDR 0x400000
301 #define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mo,eth1addr:mo"
303 /* Initial Memory map for Linux*/
304 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
307 * Miscellaneous configurable options
309 #define CONFIG_SYS_CBSIZE 1024
310 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
312 #define CONFIG_SYS_MEMTEST_START 0x00001000
313 #define CONFIG_SYS_MEMTEST_END 0x00C00000
315 #define CONFIG_SYS_LOAD_ADDR 0x100000
316 #define CONFIG_LOADS_ECHO
317 #define CONFIG_TIMESTAMP
318 #define CONFIG_PREBOOT "echo;" \
319 "echo Type \\\"run nfsboot\\\" " \
320 "to mount root filesystem over NFS;echo"
321 #define CONFIG_BOOTCOMMAND "run boot_cramfs"
322 #undef CONFIG_SYS_LOADS_BAUD_CHANGE
324 #define CONFIG_JFFS2_NAND
325 #define CONFIG_JFFS2_DEV "0"
327 /* mtdparts command line support */
329 #define CONFIG_EXTRA_ENV_SETTINGS \
330 "netdev=" __stringify(CONFIG_NETDEV) "\0" \
332 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
333 "tftpflash=tftpboot ${loadaddr} ${uboot}; " \
334 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
336 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
338 "cp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE) \
340 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
342 "cmp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE) \
345 "fdtaddr=0x780000\0" \
346 "kernel_addr=ff800000\0" \
347 "fdtfile=" __stringify(CONFIG_FDTFILE) "\0" \
348 "setbootargs=setenv bootargs " \
349 "root=${rootdev} rw console=${console}," \
350 "${baudrate} ${othbootargs}\0" \
351 "setipargs=setenv bootargs root=${rootdev} rw " \
352 "nfsroot=${serverip}:${rootpath} " \
353 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
354 "${netmask}:${hostname}:${netdev}:off " \
355 "console=${console},${baudrate} ${othbootargs}\0" \
356 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
357 "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
358 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
361 #define CONFIG_NFSBOOTCOMMAND \
362 "setenv rootdev /dev/nfs;" \
363 "run setipargs;run addmtd;" \
364 "tftp ${loadaddr} ${bootfile};" \
365 "tftp ${fdtaddr} ${fdtfile};" \
366 "fdt addr ${fdtaddr};" \
367 "bootm ${loadaddr} - ${fdtaddr}"
371 #endif /* __CONFIG_H */