drivers/mmc/socfpga_dw_mmc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2013 Altera Corporation <www.altera.com>
   4  */
   5
   6 #include <common.h>
   7 #include <asm/arch/clock_manager.h>
   8 #include <asm/arch/system_manager.h>
   9 #include <clk.h>
  10 #include <dm.h>
  11 #include <dwmmc.h>
  12 #include <errno.h>
  13 #include <fdtdec.h>
  14 #include <dm/device_compat.h>
  15 #include <linux/libfdt.h>
  16 #include <linux/err.h>
  17 #include <malloc.h>
  18 #include <reset.h>
  19
  20 DECLARE_GLOBAL_DATA_PTR;
  21
  22 struct socfpga_dwmci_plat {
  23         struct mmc_config cfg;
  24         struct mmc mmc;
  25 };
  26
  27 /* socfpga implmentation specific driver private data */
  28 struct dwmci_socfpga_priv_data {
  29         struct dwmci_host       host;
  30         unsigned int            drvsel;
  31         unsigned int            smplsel;
  32 };
  33
  34 static void socfpga_dwmci_reset(struct udevice *dev)
  35 {
  36         struct reset_ctl_bulk reset_bulk;
  37         int ret;
  38
  39         ret = reset_get_bulk(dev, &reset_bulk);
  40         if (ret) {
  41                 dev_warn(dev, "Can't get reset: %d\n", ret);
  42                 return;
  43         }
  44
  45         reset_deassert_bulk(&reset_bulk);
  46 }
  47
  48 static void socfpga_dwmci_clksel(struct dwmci_host *host)
  49 {
  50         struct dwmci_socfpga_priv_data *priv = host->priv;
  51         u32 sdmmc_mask = ((priv->smplsel & 0x7) << SYSMGR_SDMMC_SMPLSEL_SHIFT) |
  52                          ((priv->drvsel & 0x7) << SYSMGR_SDMMC_DRVSEL_SHIFT);
  53
  54         /* Disable SDMMC clock. */
  55         clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
  56                      CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
  57
  58         debug("%s: drvsel %d smplsel %d\n", __func__,
  59               priv->drvsel, priv->smplsel);
  60         writel(sdmmc_mask, socfpga_get_sysmgr_addr() + SYSMGR_SDMMC);
  61
  62         debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
  63                 readl(socfpga_get_sysmgr_addr() + SYSMGR_SDMMC));
  64
  65         /* Enable SDMMC clock */
  66         setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
  67                      CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
  68 }
  69
  70 static int socfpga_dwmmc_get_clk_rate(struct udevice *dev)
  71 {
  72         struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
  73         struct dwmci_host *host = &priv->host;
  74 #if CONFIG_IS_ENABLED(CLK)
  75         struct clk clk;
  76         int ret;
  77
  78         ret = clk_get_by_index(dev, 1, &clk);
  79         if (ret)
  80                 return ret;
  81
  82         host->bus_hz = clk_get_rate(&clk);
  83
  84         clk_free(&clk);
  85 #else
  86         /* Fixed clock divide by 4 which due to the SDMMC wrapper */
  87         host->bus_hz = cm_get_mmc_controller_clk_hz();
  88 #endif
  89         if (host->bus_hz == 0) {
  90                 printf("DWMMC: MMC clock is zero!");
  91                 return -EINVAL;
  92         }
  93
  94         return 0;
  95 }
  96
  97 static int socfpga_dwmmc_ofdata_to_platdata(struct udevice *dev)
  98 {
  99         struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
 100         struct dwmci_host *host = &priv->host;
 101         int fifo_depth;
 102
 103         fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
 104                                     "fifo-depth", 0);
 105         if (fifo_depth < 0) {
 106                 printf("DWMMC: Can't get FIFO depth\n");
 107                 return -EINVAL;
 108         }
 109
 110         host->name = dev->name;
 111         host->ioaddr = (void *)devfdt_get_addr(dev);
 112         host->buswidth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
 113                                         "bus-width", 4);
 114         host->clksel = socfpga_dwmci_clksel;
 115
 116         /*
 117          * TODO([email protected]): Remove the need for this hack.
 118          * We only have one dwmmc block on gen5 SoCFPGA.
 119          */
 120         host->dev_index = 0;
 121         host->fifoth_val = MSIZE(0x2) |
 122                 RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2);
 123         priv->drvsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
 124                                        "drvsel", 3);
 125         priv->smplsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
 126                                         "smplsel", 0);
 127         host->priv = priv;
 128
 129         return 0;
 130 }
 131
 132 static int socfpga_dwmmc_probe(struct udevice *dev)
 133 {
 134 #ifdef CONFIG_BLK
 135         struct socfpga_dwmci_plat *plat = dev_get_platdata(dev);
 136 #endif
 137         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 138         struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
 139         struct dwmci_host *host = &priv->host;
 140         int ret;
 141
 142         ret = socfpga_dwmmc_get_clk_rate(dev);
 143         if (ret)
 144                 return ret;
 145
 146         socfpga_dwmci_reset(dev);
 147
 148 #ifdef CONFIG_BLK
 149         dwmci_setup_cfg(&plat->cfg, host, host->bus_hz, 400000);
 150         host->mmc = &plat->mmc;
 151 #else
 152
 153         ret = add_dwmci(host, host->bus_hz, 400000);
 154         if (ret)
 155                 return ret;
 156 #endif
 157         host->mmc->priv = &priv->host;
 158         upriv->mmc = host->mmc;
 159         host->mmc->dev = dev;
 160
 161         return dwmci_probe(dev);
 162 }
 163
 164 static int socfpga_dwmmc_bind(struct udevice *dev)
 165 {
 166 #ifdef CONFIG_BLK
 167         struct socfpga_dwmci_plat *plat = dev_get_platdata(dev);
 168         int ret;
 169
 170         ret = dwmci_bind(dev, &plat->mmc, &plat->cfg);
 171         if (ret)
 172                 return ret;
 173 #endif
 174
 175         return 0;
 176 }
 177
 178 static const struct udevice_id socfpga_dwmmc_ids[] = {
 179         { .compatible = "altr,socfpga-dw-mshc" },
 180         { }
 181 };
 182
 183 U_BOOT_DRIVER(socfpga_dwmmc_drv) = {
 184         .name           = "socfpga_dwmmc",
 185         .id             = UCLASS_MMC,
 186         .of_match       = socfpga_dwmmc_ids,
 187         .ofdata_to_platdata = socfpga_dwmmc_ofdata_to_platdata,
 188         .ops            = &dm_dwmci_ops,
 189         .bind           = socfpga_dwmmc_bind,
 190         .probe          = socfpga_dwmmc_probe,
 191         .priv_auto_alloc_size = sizeof(struct dwmci_socfpga_priv_data),
 192         .platdata_auto_alloc_size = sizeof(struct socfpga_dwmci_plat),
 193 };