board/freescale/imx8mq_evk/spl.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2018 NXP
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <hang.h>
  10 #include <asm/io.h>
  11 #include <errno.h>
  12 #include <asm/io.h>
  13 #include <asm/arch/ddr.h>
  14 #include <asm/arch/imx8mq_pins.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/arch/clock.h>
  17 #include <asm/mach-imx/iomux-v3.h>
  18 #include <asm/mach-imx/gpio.h>
  19 #include <asm/mach-imx/mxc_i2c.h>
  20 #include <fsl_esdhc_imx.h>
  21 #include <mmc.h>
  22 #include <power/pmic.h>
  23 #include <power/pfuze100_pmic.h>
  24 #include <spl.h>
  25 #include "../common/pfuze.h"
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 extern struct dram_timing_info dram_timing_b0;
  30
  31 static void spl_dram_init(void)
  32 {
  33         /* ddr init */
  34         if ((get_cpu_rev() & 0xfff) == CHIP_REV_2_1)
  35                 ddr_init(&dram_timing);
  36         else
  37                 ddr_init(&dram_timing_b0);
  38 }
  39
  40 #define I2C_PAD_CTRL    (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
  41 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  42 static struct i2c_pads_info i2c_pad_info1 = {
  43         .scl = {
  44                 .i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,
  45                 .gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,
  46                 .gp = IMX_GPIO_NR(5, 14),
  47         },
  48         .sda = {
  49                 .i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,
  50                 .gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,
  51                 .gp = IMX_GPIO_NR(5, 15),
  52         },
  53 };
  54
  55 #define USDHC2_CD_GPIO  IMX_GPIO_NR(2, 12)
  56 #define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
  57 #define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
  58
  59 int board_mmc_getcd(struct mmc *mmc)
  60 {
  61         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  62         int ret = 0;
  63
  64         switch (cfg->esdhc_base) {
  65         case USDHC1_BASE_ADDR:
  66                 ret = 1;
  67                 break;
  68         case USDHC2_BASE_ADDR:
  69                 ret = !gpio_get_value(USDHC2_CD_GPIO);
  70                 return ret;
  71         }
  72
  73         return 1;
  74 }
  75
  76 #define USDHC_PAD_CTRL  (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
  77                          PAD_CTL_FSEL2)
  78 #define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
  79
  80 static iomux_v3_cfg_t const usdhc1_pads[] = {
  81         IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  82         IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  83         IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  84         IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  85         IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  86         IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  87         IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  88         IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  89         IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  90         IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  91         IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
  92 };
  93
  94 static iomux_v3_cfg_t const usdhc2_pads[] = {
  95         IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
  96         IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
  97         IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
  98         IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
  99         IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */
 100         IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
 101         IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
 102         IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
 103 };
 104
 105 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
 106         {USDHC1_BASE_ADDR, 0, 8},
 107         {USDHC2_BASE_ADDR, 0, 4},
 108 };
 109
 110 int board_mmc_init(bd_t *bis)
 111 {
 112         int i, ret;
 113         /*
 114          * According to the board_mmc_init() the following map is done:
 115          * (U-Boot device node)    (Physical Port)
 116          * mmc0                    USDHC1
 117          * mmc1                    USDHC2
 118          */
 119         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 120                 switch (i) {
 121                 case 0:
 122                         init_clk_usdhc(0);
 123                         usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
 124                         imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
 125                                                          ARRAY_SIZE(usdhc1_pads));
 126                         gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
 127                         gpio_direction_output(USDHC1_PWR_GPIO, 0);
 128                         udelay(500);
 129                         gpio_direction_output(USDHC1_PWR_GPIO, 1);
 130                         break;
 131                 case 1:
 132                         init_clk_usdhc(1);
 133                         usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
 134                         imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
 135                                                          ARRAY_SIZE(usdhc2_pads));
 136                         gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
 137                         gpio_direction_output(USDHC2_PWR_GPIO, 0);
 138                         udelay(500);
 139                         gpio_direction_output(USDHC2_PWR_GPIO, 1);
 140                         break;
 141                 default:
 142                         printf("Warning: you configured more USDHC controllers(%d) than supported by the board\n", i + 1);
 143                         return -EINVAL;
 144                 }
 145
 146                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 147                 if (ret)
 148                         return ret;
 149         }
 150
 151         return 0;
 152 }
 153
 154 #ifdef CONFIG_POWER
 155 #define I2C_PMIC        0
 156 int power_init_board(void)
 157 {
 158         struct pmic *p;
 159         int ret;
 160         unsigned int reg;
 161
 162         ret = power_pfuze100_init(I2C_PMIC);
 163         if (ret)
 164                 return -ENODEV;
 165
 166         p = pmic_get("PFUZE100");
 167         ret = pmic_probe(p);
 168         if (ret)
 169                 return -ENODEV;
 170
 171         pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
 172         printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
 173
 174         pmic_reg_read(p, PFUZE100_SW3AVOL, &reg);
 175         if ((reg & 0x3f) != 0x18) {
 176                 reg &= ~0x3f;
 177                 reg |= 0x18;
 178                 pmic_reg_write(p, PFUZE100_SW3AVOL, reg);
 179         }
 180
 181         ret = pfuze_mode_init(p, APS_PFM);
 182         if (ret < 0)
 183                 return ret;
 184
 185         /* set SW3A standby mode to off */
 186         pmic_reg_read(p, PFUZE100_SW3AMODE, &reg);
 187         reg &= ~0xf;
 188         reg |= APS_OFF;
 189         pmic_reg_write(p, PFUZE100_SW3AMODE, reg);
 190
 191         return 0;
 192 }
 193 #endif
 194
 195 void spl_board_init(void)
 196 {
 197         puts("Normal Boot\n");
 198 }
 199
 200 #ifdef CONFIG_SPL_LOAD_FIT
 201 int board_fit_config_name_match(const char *name)
 202 {
 203         /* Just empty function now - can't decide what to choose */
 204         debug("%s: %s\n", __func__, name);
 205
 206         return 0;
 207 }
 208 #endif
 209
 210 void board_init_f(ulong dummy)
 211 {
 212         int ret;
 213
 214         /* Clear global data */
 215         memset((void *)gd, 0, sizeof(gd_t));
 216
 217         arch_cpu_init();
 218
 219         init_uart_clk(0);
 220
 221         board_early_init_f();
 222
 223         timer_init();
 224
 225         preloader_console_init();
 226
 227         /* Clear the BSS. */
 228         memset(__bss_start, 0, __bss_end - __bss_start);
 229
 230         ret = spl_init();
 231         if (ret) {
 232                 debug("spl_init() failed: %d\n", ret);
 233                 hang();
 234         }
 235
 236         enable_tzc380();
 237
 238         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 239
 240         power_init_board();
 241
 242         /* DDR initialization */
 243         spl_dram_init();
 244
 245         board_init_r(NULL, 0);
 246 }