drivers/ram/aspeed/sdram_ast2500.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2012-2020  ASPEED Technology Inc.
   4  *
   5  * Copyright 2016 Google, Inc
   6  */
   7
   8 #include <common.h>
   9 #include <clk.h>
  10 #include <dm.h>
  11 #include <errno.h>
  12 #include <log.h>
  13 #include <ram.h>
  14 #include <regmap.h>
  15 #include <reset.h>
  16 #include <asm/io.h>
  17 #include <asm/arch/scu_ast2500.h>
  18 #include <asm/arch/sdram_ast2500.h>
  19 #include <asm/arch/wdt.h>
  20 #include <linux/err.h>
  21 #include <linux/kernel.h>
  22 #include <dt-bindings/clock/aspeed-clock.h>
  23
  24 /* These configuration parameters are taken from Aspeed SDK */
  25 #define DDR4_MR46_MODE          0x08000000
  26 #define DDR4_MR5_MODE           0x400
  27 #define DDR4_MR13_MODE          0x101
  28 #define DDR4_MR02_MODE          0x410
  29 #define DDR4_TRFC               0x45457188
  30
  31 #define PHY_CFG_SIZE            15
  32
  33 static const u32 ddr4_ac_timing[3] = {0x63604e37, 0xe97afa99, 0x00019000};
  34 static const struct {
  35         u32 index[PHY_CFG_SIZE];
  36         u32 value[PHY_CFG_SIZE];
  37 } ddr4_phy_config = {
  38         .index = {0, 1, 3, 4, 5, 56, 57, 58, 59, 60, 61, 62, 36, 49, 50},
  39         .value = {
  40                 0x42492aae, 0x09002000, 0x55e00b0b, 0x20000000, 0x24,
  41                 0x03002900, 0x0e0000a0, 0x000e001c, 0x35b8c106, 0x08080607,
  42                 0x9b000900, 0x0e400a00, 0x00100008, 0x3c183c3c, 0x00631e0e,
  43         },
  44 };
  45
  46 #define SDRAM_MAX_SIZE          (1024 * 1024 * 1024)
  47 #define SDRAM_MIN_SIZE          (128 * 1024 * 1024)
  48
  49 DECLARE_GLOBAL_DATA_PTR;
  50
  51 /*
  52  * Bandwidth configuration parameters for different SDRAM requests.
  53  * These are hardcoded settings taken from Aspeed SDK.
  54  */
  55 static const u32 ddr_max_grant_params[4] = {
  56         0x88448844, 0x24422288, 0x22222222, 0x22222222
  57 };
  58
  59 /*
  60  * These registers are not documented by Aspeed at all.
  61  * All writes and reads are taken pretty much as is from SDK.
  62  */
  63 struct ast2500_ddr_phy {
  64         u32 phy[117];
  65 };
  66
  67 struct dram_info {
  68         struct ram_info info;
  69         struct clk ddr_clk;
  70         struct ast2500_sdrammc_regs *regs;
  71         struct ast2500_scu *scu;
  72         struct ast2500_ddr_phy *phy;
  73         ulong clock_rate;
  74 };
  75
  76 static int ast2500_sdrammc_init_phy(struct ast2500_ddr_phy *phy)
  77 {
  78         writel(0, &phy->phy[2]);
  79         writel(0, &phy->phy[6]);
  80         writel(0, &phy->phy[8]);
  81         writel(0, &phy->phy[10]);
  82         writel(0, &phy->phy[12]);
  83         writel(0, &phy->phy[42]);
  84         writel(0, &phy->phy[44]);
  85
  86         writel(0x86000000, &phy->phy[16]);
  87         writel(0x00008600, &phy->phy[17]);
  88         writel(0x80000000, &phy->phy[18]);
  89         writel(0x80808080, &phy->phy[19]);
  90
  91         return 0;
  92 }
  93
  94 static void ast2500_ddr_phy_init_process(struct dram_info *info)
  95 {
  96         struct ast2500_sdrammc_regs *regs = info->regs;
  97
  98         writel(0, &regs->phy_ctrl[0]);
  99         writel(0x4040, &info->phy->phy[51]);
 100
 101         writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_INIT, &regs->phy_ctrl[0]);
 102         while ((readl(&regs->phy_ctrl[0]) & SDRAM_PHYCTRL0_INIT))
 103                 ;
 104         writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_AUTO_UPDATE,
 105                &regs->phy_ctrl[0]);
 106 }
 107
 108 static void ast2500_sdrammc_set_vref(struct dram_info *info, u32 vref)
 109 {
 110         writel(0, &info->regs->phy_ctrl[0]);
 111         writel((vref << 8) | 0x6, &info->phy->phy[48]);
 112         ast2500_ddr_phy_init_process(info);
 113 }
 114
 115 static int ast2500_ddr_cbr_test(struct dram_info *info)
 116 {
 117         struct ast2500_sdrammc_regs *regs = info->regs;
 118         int i;
 119         const u32 test_params = SDRAM_TEST_EN
 120                         | SDRAM_TEST_ERRSTOP
 121                         | SDRAM_TEST_TWO_MODES;
 122         int ret = 0;
 123
 124         writel((1 << SDRAM_REFRESH_CYCLES_SHIFT) |
 125                (0x5c << SDRAM_REFRESH_PERIOD_SHIFT), &regs->refresh_timing);
 126         writel((0xfff << SDRAM_TEST_LEN_SHIFT), &regs->test_addr);
 127         writel(0xff00ff00, &regs->test_init_val);
 128         writel(SDRAM_TEST_EN | (SDRAM_TEST_MODE_RW << SDRAM_TEST_MODE_SHIFT) |
 129                SDRAM_TEST_ERRSTOP, &regs->ecc_test_ctrl);
 130
 131         while (!(readl(&regs->ecc_test_ctrl) & SDRAM_TEST_DONE))
 132                 ;
 133
 134         if (readl(&regs->ecc_test_ctrl) & SDRAM_TEST_FAIL) {
 135                 ret = -EIO;
 136         } else {
 137                 for (i = 0; i <= SDRAM_TEST_GEN_MODE_MASK; ++i) {
 138                         writel((i << SDRAM_TEST_GEN_MODE_SHIFT) | test_params,
 139                                &regs->ecc_test_ctrl);
 140                         while (!(readl(&regs->ecc_test_ctrl) & SDRAM_TEST_DONE))
 141                                 ;
 142                         if (readl(&regs->ecc_test_ctrl) & SDRAM_TEST_FAIL) {
 143                                 ret = -EIO;
 144                                 break;
 145                         }
 146                 }
 147         }
 148
 149         writel(0, &regs->refresh_timing);
 150         writel(0, &regs->ecc_test_ctrl);
 151
 152         return ret;
 153 }
 154
 155 static int ast2500_sdrammc_ddr4_calibrate_vref(struct dram_info *info)
 156 {
 157         int i;
 158         int vref_min = 0xff;
 159         int vref_max = 0;
 160         int range_size = 0;
 161
 162         for (i = 1; i < 0x40; ++i) {
 163                 int res;
 164
 165                 ast2500_sdrammc_set_vref(info, i);
 166                 res = ast2500_ddr_cbr_test(info);
 167                 if (res < 0) {
 168                         if (range_size > 0)
 169                                 break;
 170                 } else {
 171                         ++range_size;
 172                         vref_min = min(vref_min, i);
 173                         vref_max = max(vref_max, i);
 174                 }
 175         }
 176
 177         /* Pick average setting */
 178         ast2500_sdrammc_set_vref(info, (vref_min + vref_max + 1) / 2);
 179
 180         return 0;
 181 }
 182
 183 static size_t ast2500_sdrammc_get_vga_mem_size(struct dram_info *info)
 184 {
 185         size_t vga_mem_size_base = 8 * 1024 * 1024;
 186         u32 vga_hwconf = (readl(&info->scu->hwstrap) & SCU_HWSTRAP_VGAMEM_MASK)
 187             >> SCU_HWSTRAP_VGAMEM_SHIFT;
 188
 189         return vga_mem_size_base << vga_hwconf;
 190 }
 191
 192 /*
 193  * Find out RAM size and save it in dram_info
 194  *
 195  * The procedure is taken from Aspeed SDK
 196  */
 197 static void ast2500_sdrammc_calc_size(struct dram_info *info)
 198 {
 199         /* The controller supports 128/256/512/1024 MB ram */
 200         size_t ram_size = SDRAM_MIN_SIZE;
 201         const int write_test_offset = 0x100000;
 202         u32 test_pattern = 0xdeadbeef;
 203         u32 cap_param = SDRAM_CONF_CAP_1024M;
 204         u32 refresh_timing_param = DDR4_TRFC;
 205         const u32 write_addr_base = CONFIG_SYS_SDRAM_BASE + write_test_offset;
 206
 207         for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE;
 208              ram_size >>= 1) {
 209                 writel(test_pattern, write_addr_base + (ram_size >> 1));
 210                 test_pattern = (test_pattern >> 4) | (test_pattern << 28);
 211         }
 212
 213         /* One last write to overwrite all wrapped values */
 214         writel(test_pattern, write_addr_base);
 215
 216         /* Reset the pattern and see which value was really written */
 217         test_pattern = 0xdeadbeef;
 218         for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE;
 219              ram_size >>= 1) {
 220                 if (readl(write_addr_base + (ram_size >> 1)) == test_pattern)
 221                         break;
 222
 223                 --cap_param;
 224                 refresh_timing_param >>= 8;
 225                 test_pattern = (test_pattern >> 4) | (test_pattern << 28);
 226         }
 227
 228         clrsetbits_le32(&info->regs->ac_timing[1],
 229                         (SDRAM_AC_TRFC_MASK << SDRAM_AC_TRFC_SHIFT),
 230                         ((refresh_timing_param & SDRAM_AC_TRFC_MASK)
 231                          << SDRAM_AC_TRFC_SHIFT));
 232
 233         info->info.base = CONFIG_SYS_SDRAM_BASE;
 234         info->info.size = ram_size - ast2500_sdrammc_get_vga_mem_size(info);
 235         clrsetbits_le32(&info->regs->config,
 236                         (SDRAM_CONF_CAP_MASK << SDRAM_CONF_CAP_SHIFT),
 237                         ((cap_param & SDRAM_CONF_CAP_MASK)
 238                          << SDRAM_CONF_CAP_SHIFT));
 239 }
 240
 241 static int ast2500_sdrammc_init_ddr4(struct dram_info *info)
 242 {
 243         int i;
 244         const u32 power_control = SDRAM_PCR_CKE_EN
 245             | (1 << SDRAM_PCR_CKE_DELAY_SHIFT)
 246             | (2 << SDRAM_PCR_TCKE_PW_SHIFT)
 247             | SDRAM_PCR_RESETN_DIS
 248             | SDRAM_PCR_RGAP_CTRL_EN | SDRAM_PCR_ODT_EN | SDRAM_PCR_ODT_EXT_EN;
 249         const u32 conf = (SDRAM_CONF_CAP_1024M << SDRAM_CONF_CAP_SHIFT)
 250 #ifdef CONFIG_ASPEED_DDR4_DUALX8
 251             | SDRAM_CONF_DUALX8
 252 #endif
 253             | SDRAM_CONF_SCRAMBLE | SDRAM_CONF_SCRAMBLE_PAT2 | SDRAM_CONF_DDR4;
 254         int ret;
 255
 256         writel(conf, &info->regs->config);
 257         for (i = 0; i < ARRAY_SIZE(ddr4_ac_timing); ++i)
 258                 writel(ddr4_ac_timing[i], &info->regs->ac_timing[i]);
 259
 260         writel(DDR4_MR46_MODE, &info->regs->mr46_mode_setting);
 261         writel(DDR4_MR5_MODE, &info->regs->mr5_mode_setting);
 262         writel(DDR4_MR02_MODE, &info->regs->mr02_mode_setting);
 263         writel(DDR4_MR13_MODE, &info->regs->mr13_mode_setting);
 264
 265         for (i = 0; i < PHY_CFG_SIZE; ++i) {
 266                 writel(ddr4_phy_config.value[i],
 267                        &info->phy->phy[ddr4_phy_config.index[i]]);
 268         }
 269
 270         writel(power_control, &info->regs->power_control);
 271
 272         ast2500_ddr_phy_init_process(info);
 273
 274         ret = ast2500_sdrammc_ddr4_calibrate_vref(info);
 275         if (ret < 0) {
 276                 debug("Vref calibration failed!\n");
 277                 return ret;
 278         }
 279
 280         writel((1 << SDRAM_REFRESH_CYCLES_SHIFT)
 281                | SDRAM_REFRESH_ZQCS_EN | (0x2f << SDRAM_REFRESH_PERIOD_SHIFT),
 282                &info->regs->refresh_timing);
 283
 284         setbits_le32(&info->regs->power_control,
 285                      SDRAM_PCR_AUTOPWRDN_EN | SDRAM_PCR_ODT_AUTO_ON);
 286
 287         ast2500_sdrammc_calc_size(info);
 288
 289         setbits_le32(&info->regs->config, SDRAM_CONF_CACHE_INIT_EN);
 290         while (!(readl(&info->regs->config) & SDRAM_CONF_CACHE_INIT_DONE))
 291                 ;
 292         setbits_le32(&info->regs->config, SDRAM_CONF_CACHE_EN);
 293
 294         writel(SDRAM_MISC_DDR4_TREFRESH, &info->regs->misc_control);
 295
 296         /* Enable all requests except video & display */
 297         writel(SDRAM_REQ_USB20_EHCI1
 298                | SDRAM_REQ_USB20_EHCI2
 299                | SDRAM_REQ_CPU
 300                | SDRAM_REQ_AHB2
 301                | SDRAM_REQ_AHB
 302                | SDRAM_REQ_MAC0
 303                | SDRAM_REQ_MAC1
 304                | SDRAM_REQ_PCIE
 305                | SDRAM_REQ_XDMA
 306                | SDRAM_REQ_ENCRYPTION
 307                | SDRAM_REQ_VIDEO_FLAG
 308                | SDRAM_REQ_VIDEO_LOW_PRI_WRITE
 309                | SDRAM_REQ_2D_RW
 310                | SDRAM_REQ_MEMCHECK, &info->regs->req_limit_mask);
 311
 312         return 0;
 313 }
 314
 315 static void ast2500_sdrammc_unlock(struct dram_info *info)
 316 {
 317         writel(SDRAM_UNLOCK_KEY, &info->regs->protection_key);
 318         while (!readl(&info->regs->protection_key))
 319                 ;
 320 }
 321
 322 static void ast2500_sdrammc_lock(struct dram_info *info)
 323 {
 324         writel(~SDRAM_UNLOCK_KEY, &info->regs->protection_key);
 325         while (readl(&info->regs->protection_key))
 326                 ;
 327 }
 328
 329 static int ast2500_sdrammc_probe(struct udevice *dev)
 330 {
 331         struct reset_ctl reset_ctl;
 332         struct dram_info *priv = (struct dram_info *)dev_get_priv(dev);
 333         struct ast2500_sdrammc_regs *regs = priv->regs;
 334         int i;
 335         int ret = clk_get_by_index(dev, 0, &priv->ddr_clk);
 336
 337         if (ret) {
 338                 debug("DDR:No CLK\n");
 339                 return ret;
 340         }
 341
 342         priv->scu = ast_get_scu();
 343         if (IS_ERR(priv->scu)) {
 344                 debug("%s(): can't get SCU\n", __func__);
 345                 return PTR_ERR(priv->scu);
 346         }
 347
 348         clk_set_rate(&priv->ddr_clk, priv->clock_rate);
 349         ret = reset_get_by_index(dev, 0, &reset_ctl);
 350         if (ret) {
 351                 debug("%s(): Failed to get reset signal\n", __func__);
 352                 return ret;
 353         }
 354
 355         ret = reset_assert(&reset_ctl);
 356         if (ret) {
 357                 debug("%s(): SDRAM reset failed: %u\n", __func__, ret);
 358                 return ret;
 359         }
 360
 361         ast2500_sdrammc_unlock(priv);
 362
 363         writel(SDRAM_PCR_MREQI_DIS | SDRAM_PCR_RESETN_DIS,
 364                &regs->power_control);
 365         writel(SDRAM_VIDEO_UNLOCK_KEY, &regs->gm_protection_key);
 366
 367         /* Mask all requests except CPU and AHB during PHY init */
 368         writel(~(SDRAM_REQ_CPU | SDRAM_REQ_AHB), &regs->req_limit_mask);
 369
 370         for (i = 0; i < ARRAY_SIZE(ddr_max_grant_params); ++i)
 371                 writel(ddr_max_grant_params[i], &regs->max_grant_len[i]);
 372
 373         setbits_le32(&regs->intr_ctrl, SDRAM_ICR_RESET_ALL);
 374
 375         ast2500_sdrammc_init_phy(priv->phy);
 376         if (readl(&priv->scu->hwstrap) & SCU_HWSTRAP_DDR4) {
 377                 ast2500_sdrammc_init_ddr4(priv);
 378         } else {
 379                 debug("Unsupported DRAM3\n");
 380                 return -EINVAL;
 381         }
 382
 383         clrbits_le32(&regs->intr_ctrl, SDRAM_ICR_RESET_ALL);
 384         ast2500_sdrammc_lock(priv);
 385
 386         return 0;
 387 }
 388
 389 static int ast2500_sdrammc_ofdata_to_platdata(struct udevice *dev)
 390 {
 391         struct dram_info *priv = dev_get_priv(dev);
 392         struct regmap *map;
 393         int ret;
 394
 395         ret = regmap_init_mem(dev_ofnode(dev), &map);
 396         if (ret)
 397                 return ret;
 398
 399         priv->regs = regmap_get_range(map, 0);
 400         priv->phy = regmap_get_range(map, 1);
 401
 402         priv->clock_rate = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
 403                                           "clock-frequency", 0);
 404
 405         if (!priv->clock_rate) {
 406                 debug("DDR Clock Rate not defined\n");
 407                 return -EINVAL;
 408         }
 409
 410         return 0;
 411 }
 412
 413 static int ast2500_sdrammc_get_info(struct udevice *dev, struct ram_info *info)
 414 {
 415         struct dram_info *priv = dev_get_priv(dev);
 416
 417         *info = priv->info;
 418
 419         return 0;
 420 }
 421
 422 static struct ram_ops ast2500_sdrammc_ops = {
 423         .get_info = ast2500_sdrammc_get_info,
 424 };
 425
 426 static const struct udevice_id ast2500_sdrammc_ids[] = {
 427         { .compatible = "aspeed,ast2500-sdrammc" },
 428         { }
 429 };
 430
 431 U_BOOT_DRIVER(sdrammc_ast2500) = {
 432         .name = "aspeed_ast2500_sdrammc",
 433         .id = UCLASS_RAM,
 434         .of_match = ast2500_sdrammc_ids,
 435         .ops = &ast2500_sdrammc_ops,
 436         .ofdata_to_platdata = ast2500_sdrammc_ofdata_to_platdata,
 437         .probe = ast2500_sdrammc_probe,
 438         .priv_auto_alloc_size = sizeof(struct dram_info),
 439 };