drivers/mmc/zynq_sdhci.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2013 - 2015 Xilinx, Inc.
   4  *
   5  * Xilinx Zynq SD Host Controller Interface
   6  */
   7
   8 #include <clk.h>
   9 #include <common.h>
  10 #include <dm.h>
  11 #include <fdtdec.h>
  12 #include <linux/delay.h>
  13 #include "mmc_private.h"
  14 #include <log.h>
  15 #include <dm/device_compat.h>
  16 #include <linux/err.h>
  17 #include <linux/libfdt.h>
  18 #include <malloc.h>
  19 #include <sdhci.h>
  20 #include <zynqmp_tap_delay.h>
  21
  22 #define SDHCI_ARASAN_ITAPDLY_REGISTER   0xF0F8
  23 #define SDHCI_ARASAN_OTAPDLY_REGISTER   0xF0FC
  24 #define SDHCI_ITAPDLY_CHGWIN            0x200
  25 #define SDHCI_ITAPDLY_ENABLE            0x100
  26 #define SDHCI_OTAPDLY_ENABLE            0x40
  27
  28 #define SDHCI_TUNING_LOOP_COUNT         40
  29 #define MMC_BANK2                       0x2
  30
  31 struct arasan_sdhci_clk_data {
  32         int clk_phase_in[MMC_TIMING_MMC_HS400 + 1];
  33         int clk_phase_out[MMC_TIMING_MMC_HS400 + 1];
  34 };
  35
  36 struct arasan_sdhci_plat {
  37         struct mmc_config cfg;
  38         struct mmc mmc;
  39 };
  40
  41 struct arasan_sdhci_priv {
  42         struct sdhci_host *host;
  43         struct arasan_sdhci_clk_data clk_data;
  44         u8 deviceid;
  45         u8 bank;
  46         u8 no_1p8;
  47 };
  48
  49 #if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL)
  50 /* Default settings for ZynqMP Clock Phases */
  51 const u32 zynqmp_iclk_phases[] = {0, 63, 63, 0, 63,  0,   0, 183, 54,  0, 0};
  52 const u32 zynqmp_oclk_phases[] = {0, 72, 60, 0, 60, 72, 135, 48, 72, 135, 0};
  53
  54 /* Default settings for Versal Clock Phases */
  55 const u32 versal_iclk_phases[] = {0, 132, 132, 0, 132, 0, 0, 162, 90, 0, 0};
  56 const u32 versal_oclk_phases[] = {0,  60, 48, 0, 48, 72, 90, 36, 60, 90, 0};
  57
  58 static const u8 mode2timing[] = {
  59         [MMC_LEGACY] = MMC_TIMING_LEGACY,
  60         [MMC_HS] = MMC_TIMING_MMC_HS,
  61         [SD_HS] = MMC_TIMING_SD_HS,
  62         [MMC_HS_52] = MMC_TIMING_UHS_SDR50,
  63         [MMC_DDR_52] = MMC_TIMING_UHS_DDR50,
  64         [UHS_SDR12] = MMC_TIMING_UHS_SDR12,
  65         [UHS_SDR25] = MMC_TIMING_UHS_SDR25,
  66         [UHS_SDR50] = MMC_TIMING_UHS_SDR50,
  67         [UHS_DDR50] = MMC_TIMING_UHS_DDR50,
  68         [UHS_SDR104] = MMC_TIMING_UHS_SDR104,
  69         [MMC_HS_200] = MMC_TIMING_MMC_HS200,
  70 };
  71
  72 static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u8 deviceid)
  73 {
  74         u16 clk;
  75         unsigned long timeout;
  76
  77         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
  78         clk &= ~(SDHCI_CLOCK_CARD_EN);
  79         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
  80
  81         /* Issue DLL Reset */
  82         zynqmp_dll_reset(deviceid);
  83
  84         /* Wait max 20 ms */
  85         timeout = 100;
  86         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
  87                                 & SDHCI_CLOCK_INT_STABLE)) {
  88                 if (timeout == 0) {
  89                         dev_err(mmc_dev(host->mmc),
  90                                 ": Internal clock never stabilised.\n");
  91                         return;
  92                 }
  93                 timeout--;
  94                 udelay(1000);
  95         }
  96
  97         clk |= SDHCI_CLOCK_CARD_EN;
  98         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
  99 }
 100
 101 static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
 102 {
 103         struct mmc_cmd cmd;
 104         struct mmc_data data;
 105         u32 ctrl;
 106         struct sdhci_host *host;
 107         struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev);
 108         char tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT;
 109         u8 deviceid;
 110
 111         debug("%s\n", __func__);
 112
 113         host = priv->host;
 114         deviceid = priv->deviceid;
 115
 116         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 117         ctrl |= SDHCI_CTRL_EXEC_TUNING;
 118         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
 119
 120         mdelay(1);
 121
 122         arasan_zynqmp_dll_reset(host, deviceid);
 123
 124         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
 125         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
 126
 127         do {
 128                 cmd.cmdidx = opcode;
 129                 cmd.resp_type = MMC_RSP_R1;
 130                 cmd.cmdarg = 0;
 131
 132                 data.blocksize = 64;
 133                 data.blocks = 1;
 134                 data.flags = MMC_DATA_READ;
 135
 136                 if (tuning_loop_counter-- == 0)
 137                         break;
 138
 139                 if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200 &&
 140                     mmc->bus_width == 8)
 141                         data.blocksize = 128;
 142
 143                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
 144                                                     data.blocksize),
 145                              SDHCI_BLOCK_SIZE);
 146                 sdhci_writew(host, data.blocks, SDHCI_BLOCK_COUNT);
 147                 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
 148
 149                 mmc_send_cmd(mmc, &cmd, NULL);
 150                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 151
 152                 if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK)
 153                         udelay(1);
 154
 155         } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
 156
 157         if (tuning_loop_counter < 0) {
 158                 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
 159                 sdhci_writel(host, ctrl, SDHCI_HOST_CONTROL2);
 160         }
 161
 162         if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
 163                 printf("%s:Tuning failed\n", __func__);
 164                 return -1;
 165         }
 166
 167         udelay(1);
 168         arasan_zynqmp_dll_reset(host, deviceid);
 169
 170         /* Enable only interrupts served by the SD controller */
 171         sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
 172                      SDHCI_INT_ENABLE);
 173         /* Mask all sdhci interrupt sources */
 174         sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
 175
 176         return 0;
 177 }
 178
 179 /**
 180  * sdhci_zynqmp_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
 181  *
 182  * Set the SD Output Clock Tap Delays for Output path
 183  *
 184  * @host:               Pointer to the sdhci_host structure.
 185  * @degrees:            The clock phase shift between 0 - 359.
 186  * Return: 0 on success and error value on error
 187  */
 188 static int sdhci_zynqmp_sdcardclk_set_phase(struct sdhci_host *host,
 189                                             int degrees)
 190 {
 191         struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev);
 192         struct mmc *mmc = (struct mmc *)host->mmc;
 193         u8 tap_delay, tap_max = 0;
 194         int ret;
 195         int timing = mode2timing[mmc->selected_mode];
 196
 197         /*
 198          * This is applicable for SDHCI_SPEC_300 and above
 199          * ZynqMP does not set phase for <=25MHz clock.
 200          * If degrees is zero, no need to do anything.
 201          */
 202         if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300 ||
 203             timing == MMC_TIMING_LEGACY ||
 204             timing == MMC_TIMING_UHS_SDR12 || !degrees)
 205                 return 0;
 206
 207         switch (timing) {
 208         case MMC_TIMING_MMC_HS:
 209         case MMC_TIMING_SD_HS:
 210         case MMC_TIMING_UHS_SDR25:
 211         case MMC_TIMING_UHS_DDR50:
 212         case MMC_TIMING_MMC_DDR52:
 213                 /* For 50MHz clock, 30 Taps are available */
 214                 tap_max = 30;
 215                 break;
 216         case MMC_TIMING_UHS_SDR50:
 217                 /* For 100MHz clock, 15 Taps are available */
 218                 tap_max = 15;
 219                 break;
 220         case MMC_TIMING_UHS_SDR104:
 221         case MMC_TIMING_MMC_HS200:
 222                 /* For 200MHz clock, 8 Taps are available */
 223                 tap_max = 8;
 224         default:
 225                 break;
 226         }
 227
 228         tap_delay = (degrees * tap_max) / 360;
 229
 230         arasan_zynqmp_set_tapdelay(priv->deviceid, 0, tap_delay);
 231
 232         return ret;
 233 }
 234
 235 /**
 236  * sdhci_zynqmp_sampleclk_set_phase - Set the SD Input Clock Tap Delays
 237  *
 238  * Set the SD Input Clock Tap Delays for Input path
 239  *
 240  * @host:               Pointer to the sdhci_host structure.
 241  * @degrees:            The clock phase shift between 0 - 359.
 242  * Return: 0 on success and error value on error
 243  */
 244 static int sdhci_zynqmp_sampleclk_set_phase(struct sdhci_host *host,
 245                                             int degrees)
 246 {
 247         struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev);
 248         struct mmc *mmc = (struct mmc *)host->mmc;
 249         u8 tap_delay, tap_max = 0;
 250         int ret;
 251         int timing = mode2timing[mmc->selected_mode];
 252
 253         /*
 254          * This is applicable for SDHCI_SPEC_300 and above
 255          * ZynqMP does not set phase for <=25MHz clock.
 256          * If degrees is zero, no need to do anything.
 257          */
 258         if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300 ||
 259             timing == MMC_TIMING_LEGACY ||
 260             timing == MMC_TIMING_UHS_SDR12 || !degrees)
 261                 return 0;
 262
 263         switch (timing) {
 264         case MMC_TIMING_MMC_HS:
 265         case MMC_TIMING_SD_HS:
 266         case MMC_TIMING_UHS_SDR25:
 267         case MMC_TIMING_UHS_DDR50:
 268         case MMC_TIMING_MMC_DDR52:
 269                 /* For 50MHz clock, 120 Taps are available */
 270                 tap_max = 120;
 271                 break;
 272         case MMC_TIMING_UHS_SDR50:
 273                 /* For 100MHz clock, 60 Taps are available */
 274                 tap_max = 60;
 275                 break;
 276         case MMC_TIMING_UHS_SDR104:
 277         case MMC_TIMING_MMC_HS200:
 278                 /* For 200MHz clock, 30 Taps are available */
 279                 tap_max = 30;
 280         default:
 281                 break;
 282         }
 283
 284         tap_delay = (degrees * tap_max) / 360;
 285
 286         arasan_zynqmp_set_tapdelay(priv->deviceid, tap_delay, 0);
 287
 288         return ret;
 289 }
 290
 291 /**
 292  * sdhci_versal_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
 293  *
 294  * Set the SD Output Clock Tap Delays for Output path
 295  *
 296  * @host:               Pointer to the sdhci_host structure.
 297  * @degrees             The clock phase shift between 0 - 359.
 298  * Return: 0 on success and error value on error
 299  */
 300 static int sdhci_versal_sdcardclk_set_phase(struct sdhci_host *host,
 301                                             int degrees)
 302 {
 303         struct mmc *mmc = (struct mmc *)host->mmc;
 304         u8 tap_delay, tap_max = 0;
 305         int ret;
 306         int timing = mode2timing[mmc->selected_mode];
 307
 308         /*
 309          * This is applicable for SDHCI_SPEC_300 and above
 310          * Versal does not set phase for <=25MHz clock.
 311          * If degrees is zero, no need to do anything.
 312          */
 313         if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300 ||
 314             timing == MMC_TIMING_LEGACY ||
 315             timing == MMC_TIMING_UHS_SDR12 || !degrees)
 316                 return 0;
 317
 318         switch (timing) {
 319         case MMC_TIMING_MMC_HS:
 320         case MMC_TIMING_SD_HS:
 321         case MMC_TIMING_UHS_SDR25:
 322         case MMC_TIMING_UHS_DDR50:
 323         case MMC_TIMING_MMC_DDR52:
 324                 /* For 50MHz clock, 30 Taps are available */
 325                 tap_max = 30;
 326                 break;
 327         case MMC_TIMING_UHS_SDR50:
 328                 /* For 100MHz clock, 15 Taps are available */
 329                 tap_max = 15;
 330                 break;
 331         case MMC_TIMING_UHS_SDR104:
 332         case MMC_TIMING_MMC_HS200:
 333                 /* For 200MHz clock, 8 Taps are available */
 334                 tap_max = 8;
 335         default:
 336                 break;
 337         }
 338
 339         tap_delay = (degrees * tap_max) / 360;
 340
 341         /* Set the Clock Phase */
 342         if (tap_delay) {
 343                 u32 regval;
 344
 345                 regval = sdhci_readl(host, SDHCI_ARASAN_OTAPDLY_REGISTER);
 346                 regval |= SDHCI_OTAPDLY_ENABLE;
 347                 sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
 348                 regval |= tap_delay;
 349                 sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
 350         }
 351
 352         return ret;
 353 }
 354
 355 /**
 356  * sdhci_versal_sampleclk_set_phase - Set the SD Input Clock Tap Delays
 357  *
 358  * Set the SD Input Clock Tap Delays for Input path
 359  *
 360  * @host:               Pointer to the sdhci_host structure.
 361  * @degrees             The clock phase shift between 0 - 359.
 362  * Return: 0 on success and error value on error
 363  */
 364 static int sdhci_versal_sampleclk_set_phase(struct sdhci_host *host,
 365                                             int degrees)
 366 {
 367         struct mmc *mmc = (struct mmc *)host->mmc;
 368         u8 tap_delay, tap_max = 0;
 369         int ret;
 370         int timing = mode2timing[mmc->selected_mode];
 371
 372         /*
 373          * This is applicable for SDHCI_SPEC_300 and above
 374          * Versal does not set phase for <=25MHz clock.
 375          * If degrees is zero, no need to do anything.
 376          */
 377         if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300 ||
 378             timing == MMC_TIMING_LEGACY ||
 379             timing == MMC_TIMING_UHS_SDR12 || !degrees)
 380                 return 0;
 381
 382         switch (timing) {
 383         case MMC_TIMING_MMC_HS:
 384         case MMC_TIMING_SD_HS:
 385         case MMC_TIMING_UHS_SDR25:
 386         case MMC_TIMING_UHS_DDR50:
 387         case MMC_TIMING_MMC_DDR52:
 388                 /* For 50MHz clock, 120 Taps are available */
 389                 tap_max = 120;
 390                 break;
 391         case MMC_TIMING_UHS_SDR50:
 392                 /* For 100MHz clock, 60 Taps are available */
 393                 tap_max = 60;
 394                 break;
 395         case MMC_TIMING_UHS_SDR104:
 396         case MMC_TIMING_MMC_HS200:
 397                 /* For 200MHz clock, 30 Taps are available */
 398                 tap_max = 30;
 399         default:
 400                 break;
 401         }
 402
 403         tap_delay = (degrees * tap_max) / 360;
 404
 405         /* Set the Clock Phase */
 406         if (tap_delay) {
 407                 u32 regval;
 408
 409                 regval = sdhci_readl(host, SDHCI_ARASAN_ITAPDLY_REGISTER);
 410                 regval |= SDHCI_ITAPDLY_CHGWIN;
 411                 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
 412                 regval |= SDHCI_ITAPDLY_ENABLE;
 413                 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
 414                 regval |= tap_delay;
 415                 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
 416                 regval &= ~SDHCI_ITAPDLY_CHGWIN;
 417                 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
 418         }
 419
 420         return ret;
 421 }
 422
 423 static void arasan_sdhci_set_tapdelay(struct sdhci_host *host)
 424 {
 425         struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev);
 426         struct arasan_sdhci_clk_data *clk_data = &priv->clk_data;
 427         struct mmc *mmc = (struct mmc *)host->mmc;
 428         struct udevice *dev = mmc->dev;
 429         u8 timing = mode2timing[mmc->selected_mode];
 430         u32 iclk_phase = clk_data->clk_phase_in[timing];
 431         u32 oclk_phase = clk_data->clk_phase_out[timing];
 432
 433         dev_dbg(dev, "%s, host:%s, mode:%d\n", __func__, host->name, timing);
 434
 435         if (IS_ENABLED(CONFIG_ARCH_ZYNQMP) &&
 436             device_is_compatible(dev, "xlnx,zynqmp-8.9a")) {
 437                 sdhci_zynqmp_sampleclk_set_phase(host, iclk_phase);
 438                 sdhci_zynqmp_sdcardclk_set_phase(host, oclk_phase);
 439         } else if (IS_ENABLED(CONFIG_ARCH_VERSAL) &&
 440                    device_is_compatible(dev, "xlnx,versal-8.9a")) {
 441                 sdhci_versal_sampleclk_set_phase(host, iclk_phase);
 442                 sdhci_versal_sdcardclk_set_phase(host, oclk_phase);
 443         }
 444 }
 445
 446 static void arasan_dt_read_clk_phase(struct udevice *dev, unsigned char timing,
 447                                      const char *prop)
 448 {
 449         struct arasan_sdhci_priv *priv = dev_get_priv(dev);
 450         struct arasan_sdhci_clk_data *clk_data = &priv->clk_data;
 451         u32 clk_phase[2] = {0};
 452
 453         /*
 454          * Read Tap Delay values from DT, if the DT does not contain the
 455          * Tap Values then use the pre-defined values
 456          */
 457         if (dev_read_u32_array(dev, prop, &clk_phase[0], 2)) {
 458                 dev_dbg(dev, "Using predefined clock phase for %s = %d %d\n",
 459                         prop, clk_data->clk_phase_in[timing],
 460                         clk_data->clk_phase_out[timing]);
 461                 return;
 462         }
 463
 464         /* The values read are Input and Output Clock Delays in order */
 465         clk_data->clk_phase_in[timing] = clk_phase[0];
 466         clk_data->clk_phase_out[timing] = clk_phase[1];
 467 }
 468
 469 /**
 470  * arasan_dt_parse_clk_phases - Read Tap Delay values from DT
 471  *
 472  * Called at initialization to parse the values of Tap Delays.
 473  *
 474  * @dev:                Pointer to our struct udevice.
 475  */
 476 static void arasan_dt_parse_clk_phases(struct udevice *dev)
 477 {
 478         struct arasan_sdhci_priv *priv = dev_get_priv(dev);
 479         struct arasan_sdhci_clk_data *clk_data = &priv->clk_data;
 480         int i;
 481
 482         if (IS_ENABLED(CONFIG_ARCH_ZYNQMP) &&
 483             device_is_compatible(dev, "xlnx,zynqmp-8.9a")) {
 484                 for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
 485                         clk_data->clk_phase_in[i] = zynqmp_iclk_phases[i];
 486                         clk_data->clk_phase_out[i] = zynqmp_oclk_phases[i];
 487                 }
 488
 489                 if (priv->bank == MMC_BANK2) {
 490                         clk_data->clk_phase_out[MMC_TIMING_UHS_SDR104] = 90;
 491                         clk_data->clk_phase_out[MMC_TIMING_MMC_HS200] = 90;
 492                 }
 493         }
 494
 495         if (IS_ENABLED(CONFIG_ARCH_VERSAL) &&
 496             device_is_compatible(dev, "xlnx,versal-8.9a")) {
 497                 for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
 498                         clk_data->clk_phase_in[i] = versal_iclk_phases[i];
 499                         clk_data->clk_phase_out[i] = versal_oclk_phases[i];
 500                 }
 501         }
 502
 503         arasan_dt_read_clk_phase(dev, MMC_TIMING_LEGACY,
 504                                  "clk-phase-legacy");
 505         arasan_dt_read_clk_phase(dev, MMC_TIMING_MMC_HS,
 506                                  "clk-phase-mmc-hs");
 507         arasan_dt_read_clk_phase(dev, MMC_TIMING_SD_HS,
 508                                  "clk-phase-sd-hs");
 509         arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR12,
 510                                  "clk-phase-uhs-sdr12");
 511         arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR25,
 512                                  "clk-phase-uhs-sdr25");
 513         arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR50,
 514                                  "clk-phase-uhs-sdr50");
 515         arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR104,
 516                                  "clk-phase-uhs-sdr104");
 517         arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_DDR50,
 518                                  "clk-phase-uhs-ddr50");
 519         arasan_dt_read_clk_phase(dev, MMC_TIMING_MMC_DDR52,
 520                                  "clk-phase-mmc-ddr52");
 521         arasan_dt_read_clk_phase(dev, MMC_TIMING_MMC_HS200,
 522                                  "clk-phase-mmc-hs200");
 523         arasan_dt_read_clk_phase(dev, MMC_TIMING_MMC_HS400,
 524                                  "clk-phase-mmc-hs400");
 525 }
 526
 527 static void arasan_sdhci_set_control_reg(struct sdhci_host *host)
 528 {
 529         struct mmc *mmc = (struct mmc *)host->mmc;
 530         u32 reg;
 531
 532         if (!IS_SD(mmc))
 533                 return;
 534
 535         if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
 536                 reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 537                 reg |= SDHCI_CTRL_VDD_180;
 538                 sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
 539         }
 540
 541         if (mmc->selected_mode > SD_HS &&
 542             mmc->selected_mode <= MMC_HS_200)
 543                 sdhci_set_uhs_timing(host);
 544 }
 545
 546 const struct sdhci_ops arasan_ops = {
 547         .platform_execute_tuning = &arasan_sdhci_execute_tuning,
 548         .set_delay = &arasan_sdhci_set_tapdelay,
 549         .set_control_reg = &arasan_sdhci_set_control_reg,
 550 };
 551 #endif
 552
 553 static int arasan_sdhci_probe(struct udevice *dev)
 554 {
 555         struct arasan_sdhci_plat *plat = dev_get_plat(dev);
 556         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 557         struct arasan_sdhci_priv *priv = dev_get_priv(dev);
 558         struct sdhci_host *host;
 559         struct clk clk;
 560         unsigned long clock;
 561         int ret;
 562
 563         host = priv->host;
 564
 565         ret = clk_get_by_index(dev, 0, &clk);
 566         if (ret < 0) {
 567                 dev_err(dev, "failed to get clock\n");
 568                 return ret;
 569         }
 570
 571         clock = clk_get_rate(&clk);
 572         if (IS_ERR_VALUE(clock)) {
 573                 dev_err(dev, "failed to get rate\n");
 574                 return clock;
 575         }
 576
 577         debug("%s: CLK %ld\n", __func__, clock);
 578
 579         ret = clk_enable(&clk);
 580         if (ret) {
 581                 dev_err(dev, "failed to enable clock\n");
 582                 return ret;
 583         }
 584
 585         host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
 586                        SDHCI_QUIRK_BROKEN_R1B;
 587
 588 #ifdef CONFIG_ZYNQ_HISPD_BROKEN
 589         host->quirks |= SDHCI_QUIRK_BROKEN_HISPD_MODE;
 590 #endif
 591
 592         if (priv->no_1p8)
 593                 host->quirks |= SDHCI_QUIRK_NO_1_8_V;
 594
 595         plat->cfg.f_max = CONFIG_ZYNQ_SDHCI_MAX_FREQ;
 596
 597         ret = mmc_of_parse(dev, &plat->cfg);
 598         if (ret)
 599                 return ret;
 600
 601         host->max_clk = clock;
 602
 603         host->mmc = &plat->mmc;
 604         host->mmc->dev = dev;
 605         host->mmc->priv = host;
 606
 607         ret = sdhci_setup_cfg(&plat->cfg, host, plat->cfg.f_max,
 608                               CONFIG_ZYNQ_SDHCI_MIN_FREQ);
 609         if (ret)
 610                 return ret;
 611         upriv->mmc = host->mmc;
 612
 613         return sdhci_probe(dev);
 614 }
 615
 616 static int arasan_sdhci_of_to_plat(struct udevice *dev)
 617 {
 618         struct arasan_sdhci_priv *priv = dev_get_priv(dev);
 619
 620         priv->host = calloc(1, sizeof(struct sdhci_host));
 621         if (!priv->host)
 622                 return -1;
 623
 624         priv->host->name = dev->name;
 625
 626 #if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL)
 627         priv->host->ops = &arasan_ops;
 628         arasan_dt_parse_clk_phases(dev);
 629 #endif
 630
 631         priv->host->ioaddr = (void *)dev_read_addr(dev);
 632         if (IS_ERR(priv->host->ioaddr))
 633                 return PTR_ERR(priv->host->ioaddr);
 634
 635         priv->deviceid = dev_read_u32_default(dev, "xlnx,device_id", -1);
 636         priv->bank = dev_read_u32_default(dev, "xlnx,mio-bank", 0);
 637         priv->no_1p8 = dev_read_bool(dev, "no-1-8-v");
 638
 639         return 0;
 640 }
 641
 642 static int arasan_sdhci_bind(struct udevice *dev)
 643 {
 644         struct arasan_sdhci_plat *plat = dev_get_plat(dev);
 645
 646         return sdhci_bind(dev, &plat->mmc, &plat->cfg);
 647 }
 648
 649 static const struct udevice_id arasan_sdhci_ids[] = {
 650         { .compatible = "arasan,sdhci-8.9a" },
 651         { }
 652 };
 653
 654 U_BOOT_DRIVER(arasan_sdhci_drv) = {
 655         .name           = "arasan_sdhci",
 656         .id             = UCLASS_MMC,
 657         .of_match       = arasan_sdhci_ids,
 658         .of_to_plat = arasan_sdhci_of_to_plat,
 659         .ops            = &sdhci_ops,
 660         .bind           = arasan_sdhci_bind,
 661         .probe          = arasan_sdhci_probe,
 662         .priv_auto      = sizeof(struct arasan_sdhci_priv),
 663         .plat_auto      = sizeof(struct arasan_sdhci_plat),
 664 };