drivers/video/mxsfb.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Freescale i.MX23/i.MX28 LCDIF driver
   4  *
   5  * Copyright (C) 2011-2013 Marek Vasut <[email protected]>
   6  */
   7 #include <common.h>
   8 #include <clk.h>
   9 #include <dm.h>
  10 #include <env.h>
  11 #include <asm/cache.h>
  12 #include <dm/device_compat.h>
  13 #include <linux/errno.h>
  14 #include <malloc.h>
  15 #include <video.h>
  16 #include <video_fb.h>
  17
  18 #include <asm/arch/clock.h>
  19 #include <asm/arch/imx-regs.h>
  20 #include <asm/arch/sys_proto.h>
  21 #include <asm/mach-imx/dma.h>
  22 #include <asm/io.h>
  23
  24 #include "videomodes.h"
  25
  26 #define PS2KHZ(ps)      (1000000000UL / (ps))
  27 #define HZ2PS(hz)       (1000000000UL / ((hz) / 1000))
  28
  29 #define BITS_PP         18
  30 #define BYTES_PP        4
  31
  32 struct mxs_dma_desc desc;
  33
  34 /**
  35  * mxsfb_system_setup() - Fine-tune LCDIF configuration
  36  *
  37  * This function is used to adjust the LCDIF configuration. This is usually
  38  * needed when driving the controller in System-Mode to operate an 8080 or
  39  * 6800 connected SmartLCD.
  40  */
  41 __weak void mxsfb_system_setup(void)
  42 {
  43 }
  44
  45 /*
  46  * ARIES M28EVK:
  47  * setenv videomode
  48  * video=ctfb:x:800,y:480,depth:18,mode:0,pclk:30066,
  49  *       le:0,ri:256,up:0,lo:45,hs:1,vs:1,sync:100663296,vmode:0
  50  *
  51  * Freescale mx23evk/mx28evk with a Seiko 4.3'' WVGA panel:
  52  * setenv videomode
  53  * video=ctfb:x:800,y:480,depth:24,mode:0,pclk:29851,
  54  *       le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0
  55  */
  56
  57 static void mxs_lcd_init(struct udevice *dev, u32 fb_addr,
  58                          struct display_timing *timings, int bpp)
  59 {
  60         struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
  61         const enum display_flags flags = timings->flags;
  62         uint32_t word_len = 0, bus_width = 0;
  63         uint8_t valid_data = 0;
  64         uint32_t vdctrl0;
  65
  66 #if CONFIG_IS_ENABLED(CLK)
  67         struct clk per_clk;
  68         int ret;
  69
  70         ret = clk_get_by_name(dev, "per", &per_clk);
  71         if (ret) {
  72                 dev_err(dev, "Failed to get mxs clk: %d\n", ret);
  73                 return;
  74         }
  75
  76         ret = clk_set_rate(&per_clk, timings->pixelclock.typ);
  77         if (ret < 0) {
  78                 dev_err(dev, "Failed to set mxs clk: %d\n", ret);
  79                 return;
  80         }
  81
  82         ret = clk_enable(&per_clk);
  83         if (ret < 0) {
  84                 dev_err(dev, "Failed to enable mxs clk: %d\n", ret);
  85                 return;
  86         }
  87 #else
  88         /* Kick in the LCDIF clock */
  89         mxs_set_lcdclk(MXS_LCDIF_BASE, timings->pixelclock.typ / 1000);
  90 #endif
  91
  92         /* Restart the LCDIF block */
  93         mxs_reset_block(&regs->hw_lcdif_ctrl_reg);
  94
  95         switch (bpp) {
  96         case 24:
  97                 word_len = LCDIF_CTRL_WORD_LENGTH_24BIT;
  98                 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT;
  99                 valid_data = 0x7;
 100                 break;
 101         case 18:
 102                 word_len = LCDIF_CTRL_WORD_LENGTH_24BIT;
 103                 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT;
 104                 valid_data = 0x7;
 105                 break;
 106         case 16:
 107                 word_len = LCDIF_CTRL_WORD_LENGTH_16BIT;
 108                 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT;
 109                 valid_data = 0xf;
 110                 break;
 111         case 8:
 112                 word_len = LCDIF_CTRL_WORD_LENGTH_8BIT;
 113                 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT;
 114                 valid_data = 0xf;
 115                 break;
 116         }
 117
 118         writel(bus_width | word_len | LCDIF_CTRL_DOTCLK_MODE |
 119                 LCDIF_CTRL_BYPASS_COUNT | LCDIF_CTRL_LCDIF_MASTER,
 120                 &regs->hw_lcdif_ctrl);
 121
 122         writel(valid_data << LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET,
 123                 &regs->hw_lcdif_ctrl1);
 124
 125         mxsfb_system_setup();
 126
 127         writel((timings->vactive.typ << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) |
 128                 timings->hactive.typ, &regs->hw_lcdif_transfer_count);
 129
 130         vdctrl0 = LCDIF_VDCTRL0_ENABLE_PRESENT | LCDIF_VDCTRL0_ENABLE_POL |
 131                   LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT |
 132                   LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT |
 133                   timings->vsync_len.typ;
 134
 135         if(flags & DISPLAY_FLAGS_HSYNC_HIGH)
 136                 vdctrl0 |= LCDIF_VDCTRL0_HSYNC_POL;
 137         if(flags & DISPLAY_FLAGS_VSYNC_HIGH)
 138                 vdctrl0 |= LCDIF_VDCTRL0_VSYNC_POL;
 139         if(flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
 140                 vdctrl0 |= LCDIF_VDCTRL0_DOTCLK_POL;
 141         if(flags & DISPLAY_FLAGS_DE_HIGH)
 142                 vdctrl0 |= LCDIF_VDCTRL0_ENABLE_POL;
 143
 144         writel(vdctrl0, &regs->hw_lcdif_vdctrl0);
 145         writel(timings->vback_porch.typ + timings->vfront_porch.typ +
 146                 timings->vsync_len.typ + timings->vactive.typ,
 147                 &regs->hw_lcdif_vdctrl1);
 148         writel((timings->hsync_len.typ << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET) |
 149                 (timings->hback_porch.typ + timings->hfront_porch.typ +
 150                 timings->hsync_len.typ + timings->hactive.typ),
 151                 &regs->hw_lcdif_vdctrl2);
 152         writel(((timings->hback_porch.typ + timings->hsync_len.typ) <<
 153                 LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET) |
 154                 (timings->vback_porch.typ + timings->vsync_len.typ),
 155                 &regs->hw_lcdif_vdctrl3);
 156         writel((0 << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET) | timings->hactive.typ,
 157                 &regs->hw_lcdif_vdctrl4);
 158
 159         writel(fb_addr, &regs->hw_lcdif_cur_buf);
 160         writel(fb_addr, &regs->hw_lcdif_next_buf);
 161
 162         /* Flush FIFO first */
 163         writel(LCDIF_CTRL1_FIFO_CLEAR, &regs->hw_lcdif_ctrl1_set);
 164
 165 #ifndef CONFIG_VIDEO_MXS_MODE_SYSTEM
 166         /* Sync signals ON */
 167         setbits_le32(&regs->hw_lcdif_vdctrl4, LCDIF_VDCTRL4_SYNC_SIGNALS_ON);
 168 #endif
 169
 170         /* FIFO cleared */
 171         writel(LCDIF_CTRL1_FIFO_CLEAR, &regs->hw_lcdif_ctrl1_clr);
 172
 173         /* RUN! */
 174         writel(LCDIF_CTRL_RUN, &regs->hw_lcdif_ctrl_set);
 175 }
 176
 177 static int mxs_probe_common(struct udevice *dev, struct display_timing *timings,
 178                             int bpp, u32 fb)
 179 {
 180         /* Start framebuffer */
 181         mxs_lcd_init(dev, fb, timings, bpp);
 182
 183 #ifdef CONFIG_VIDEO_MXS_MODE_SYSTEM
 184         /*
 185          * If the LCD runs in system mode, the LCD refresh has to be triggered
 186          * manually by setting the RUN bit in HW_LCDIF_CTRL register. To avoid
 187          * having to set this bit manually after every single change in the
 188          * framebuffer memory, we set up specially crafted circular DMA, which
 189          * sets the RUN bit, then waits until it gets cleared and repeats this
 190          * infinitelly. This way, we get smooth continuous updates of the LCD.
 191          */
 192         struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
 193
 194         memset(&desc, 0, sizeof(struct mxs_dma_desc));
 195         desc.address = (dma_addr_t)&desc;
 196         desc.cmd.data = MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
 197                         MXS_DMA_DESC_WAIT4END |
 198                         (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
 199         desc.cmd.pio_words[0] = readl(&regs->hw_lcdif_ctrl) | LCDIF_CTRL_RUN;
 200         desc.cmd.next = (uint32_t)&desc.cmd;
 201
 202         /* Execute the DMA chain. */
 203         mxs_dma_circ_start(MXS_DMA_CHANNEL_AHB_APBH_LCDIF, &desc);
 204 #endif
 205
 206         return 0;
 207 }
 208
 209 static int mxs_remove_common(u32 fb)
 210 {
 211         struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
 212         int timeout = 1000000;
 213
 214         if (!fb)
 215                 return -EINVAL;
 216
 217         writel(fb, &regs->hw_lcdif_cur_buf_reg);
 218         writel(fb, &regs->hw_lcdif_next_buf_reg);
 219         writel(LCDIF_CTRL1_VSYNC_EDGE_IRQ, &regs->hw_lcdif_ctrl1_clr);
 220         while (--timeout) {
 221                 if (readl(&regs->hw_lcdif_ctrl1_reg) &
 222                     LCDIF_CTRL1_VSYNC_EDGE_IRQ)
 223                         break;
 224                 udelay(1);
 225         }
 226         mxs_reset_block((struct mxs_register_32 *)&regs->hw_lcdif_ctrl_reg);
 227
 228         return 0;
 229 }
 230
 231 #ifndef CONFIG_DM_VIDEO
 232
 233 static GraphicDevice panel;
 234
 235 void lcdif_power_down(void)
 236 {
 237         mxs_remove_common(panel.frameAdrs);
 238 }
 239
 240 void *video_hw_init(void)
 241 {
 242         int bpp = -1;
 243         int ret = 0;
 244         char *penv;
 245         void *fb = NULL;
 246         struct ctfb_res_modes mode;
 247         struct display_timing timings;
 248
 249         puts("Video: ");
 250
 251         /* Suck display configuration from "videomode" variable */
 252         penv = env_get("videomode");
 253         if (!penv) {
 254                 puts("MXSFB: 'videomode' variable not set!\n");
 255                 return NULL;
 256         }
 257
 258         bpp = video_get_params(&mode, penv);
 259
 260         /* fill in Graphic device struct */
 261         sprintf(panel.modeIdent, "%dx%dx%d", mode.xres, mode.yres, bpp);
 262
 263         panel.winSizeX = mode.xres;
 264         panel.winSizeY = mode.yres;
 265         panel.plnSizeX = mode.xres;
 266         panel.plnSizeY = mode.yres;
 267
 268         switch (bpp) {
 269         case 24:
 270         case 18:
 271                 panel.gdfBytesPP = 4;
 272                 panel.gdfIndex = GDF_32BIT_X888RGB;
 273                 break;
 274         case 16:
 275                 panel.gdfBytesPP = 2;
 276                 panel.gdfIndex = GDF_16BIT_565RGB;
 277                 break;
 278         case 8:
 279                 panel.gdfBytesPP = 1;
 280                 panel.gdfIndex = GDF__8BIT_INDEX;
 281                 break;
 282         default:
 283                 printf("MXSFB: Invalid BPP specified! (bpp = %i)\n", bpp);
 284                 return NULL;
 285         }
 286
 287         panel.memSize = mode.xres * mode.yres * panel.gdfBytesPP;
 288
 289         /* Allocate framebuffer */
 290         fb = memalign(ARCH_DMA_MINALIGN,
 291                       roundup(panel.memSize, ARCH_DMA_MINALIGN));
 292         if (!fb) {
 293                 printf("MXSFB: Error allocating framebuffer!\n");
 294                 return NULL;
 295         }
 296
 297         /* Wipe framebuffer */
 298         memset(fb, 0, panel.memSize);
 299
 300         panel.frameAdrs = (u32)fb;
 301
 302         printf("%s\n", panel.modeIdent);
 303
 304         video_ctfb_mode_to_display_timing(&mode, &timings);
 305
 306         ret = mxs_probe_common(NULL, &timings, bpp, (u32)fb);
 307         if (ret)
 308                 goto dealloc_fb;
 309
 310         return (void *)&panel;
 311
 312 dealloc_fb:
 313         free(fb);
 314
 315         return NULL;
 316 }
 317 #else /* ifndef CONFIG_DM_VIDEO */
 318
 319 static int mxs_of_get_timings(struct udevice *dev,
 320                               struct display_timing *timings,
 321                               u32 *bpp)
 322 {
 323         int ret = 0;
 324         u32 display_phandle;
 325         ofnode display_node;
 326
 327         ret = ofnode_read_u32(dev_ofnode(dev), "display", &display_phandle);
 328         if (ret) {
 329                 dev_err(dev, "required display property isn't provided\n");
 330                 return -EINVAL;
 331         }
 332
 333         display_node = ofnode_get_by_phandle(display_phandle);
 334         if (!ofnode_valid(display_node)) {
 335                 dev_err(dev, "failed to find display subnode\n");
 336                 return -EINVAL;
 337         }
 338
 339         ret = ofnode_read_u32(display_node, "bits-per-pixel", bpp);
 340         if (ret) {
 341                 dev_err(dev,
 342                         "required bits-per-pixel property isn't provided\n");
 343                 return -EINVAL;
 344         }
 345
 346         ret = ofnode_decode_display_timing(display_node, 0, timings);
 347         if (ret) {
 348                 dev_err(dev, "failed to get any display timings\n");
 349                 return -EINVAL;
 350         }
 351
 352         return ret;
 353 }
 354
 355 static int mxs_video_probe(struct udevice *dev)
 356 {
 357         struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
 358         struct video_priv *uc_priv = dev_get_uclass_priv(dev);
 359
 360         struct display_timing timings;
 361         u32 bpp = 0;
 362         u32 fb_start, fb_end;
 363         int ret;
 364
 365         debug("%s() plat: base 0x%lx, size 0x%x\n",
 366                __func__, plat->base, plat->size);
 367
 368         ret = mxs_of_get_timings(dev, &timings, &bpp);
 369         if (ret)
 370                 return ret;
 371
 372         ret = mxs_probe_common(dev, &timings, bpp, plat->base);
 373         if (ret)
 374                 return ret;
 375
 376         switch (bpp) {
 377         case 32:
 378         case 24:
 379         case 18:
 380                 uc_priv->bpix = VIDEO_BPP32;
 381                 break;
 382         case 16:
 383                 uc_priv->bpix = VIDEO_BPP16;
 384                 break;
 385         case 8:
 386                 uc_priv->bpix = VIDEO_BPP8;
 387                 break;
 388         default:
 389                 dev_err(dev, "invalid bpp specified (bpp = %i)\n", bpp);
 390                 return -EINVAL;
 391         }
 392
 393         uc_priv->xsize = timings.hactive.typ;
 394         uc_priv->ysize = timings.vactive.typ;
 395
 396         /* Enable dcache for the frame buffer */
 397         fb_start = plat->base & ~(MMU_SECTION_SIZE - 1);
 398         fb_end = plat->base + plat->size;
 399         fb_end = ALIGN(fb_end, 1 << MMU_SECTION_SHIFT);
 400         mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start,
 401                                         DCACHE_WRITEBACK);
 402         video_set_flush_dcache(dev, true);
 403         gd->fb_base = plat->base;
 404
 405         return ret;
 406 }
 407
 408 static int mxs_video_bind(struct udevice *dev)
 409 {
 410         struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
 411         struct display_timing timings;
 412         u32 bpp = 0;
 413         u32 bytes_pp = 0;
 414         int ret;
 415
 416         ret = mxs_of_get_timings(dev, &timings, &bpp);
 417         if (ret)
 418                 return ret;
 419
 420         switch (bpp) {
 421         case 32:
 422         case 24:
 423         case 18:
 424                 bytes_pp = 4;
 425                 break;
 426         case 16:
 427                 bytes_pp = 2;
 428                 break;
 429         case 8:
 430                 bytes_pp = 1;
 431                 break;
 432         default:
 433                 dev_err(dev, "invalid bpp specified (bpp = %i)\n", bpp);
 434                 return -EINVAL;
 435         }
 436
 437         plat->size = timings.hactive.typ * timings.vactive.typ * bytes_pp;
 438
 439         return 0;
 440 }
 441
 442 static int mxs_video_remove(struct udevice *dev)
 443 {
 444         struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
 445
 446         mxs_remove_common(plat->base);
 447
 448         return 0;
 449 }
 450
 451 static const struct udevice_id mxs_video_ids[] = {
 452         { .compatible = "fsl,imx23-lcdif" },
 453         { .compatible = "fsl,imx28-lcdif" },
 454         { .compatible = "fsl,imx7ulp-lcdif" },
 455         { .compatible = "fsl,imxrt-lcdif" },
 456         { /* sentinel */ }
 457 };
 458
 459 U_BOOT_DRIVER(mxs_video) = {
 460         .name   = "mxs_video",
 461         .id     = UCLASS_VIDEO,
 462         .of_match = mxs_video_ids,
 463         .bind   = mxs_video_bind,
 464         .probe  = mxs_video_probe,
 465         .remove = mxs_video_remove,
 466         .flags  = DM_FLAG_PRE_RELOC | DM_FLAG_OS_PREPARE,
 467 };
 468 #endif /* ifndef CONFIG_DM_VIDEO */