board/freescale/t4qds/eth.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2012 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <command.h>
   8 #include <net.h>
   9 #include <netdev.h>
  10 #include <asm/mmu.h>
  11 #include <asm/processor.h>
  12 #include <asm/cache.h>
  13 #include <asm/immap_85xx.h>
  14 #include <asm/fsl_law.h>
  15 #include <fsl_ddr_sdram.h>
  16 #include <asm/fsl_serdes.h>
  17 #include <asm/fsl_portals.h>
  18 #include <asm/fsl_liodn.h>
  19 #include <malloc.h>
  20 #include <fm_eth.h>
  21 #include <fsl_mdio.h>
  22 #include <miiphy.h>
  23 #include <phy.h>
  24 #include <fsl_dtsec.h>
  25 #include <asm/fsl_serdes.h>
  26 #include <hwconfig.h>
  27 #include "../common/qixis.h"
  28 #include "../common/fman.h"
  29
  30 #include "t4240qds_qixis.h"
  31
  32 #define EMI_NONE        0xFFFFFFFF
  33 #define EMI1_RGMII      0
  34 #define EMI1_SLOT1      1
  35 #define EMI1_SLOT2      2
  36 #define EMI1_SLOT3      3
  37 #define EMI1_SLOT4      4
  38 #define EMI1_SLOT5      5
  39 #define EMI1_SLOT7      7
  40 #define EMI2            8
  41 /* Slot6 and Slot8 do not have EMI connections */
  42
  43 static int mdio_mux[NUM_FM_PORTS];
  44
  45 static const char *mdio_names[] = {
  46         "T4240QDS_MDIO0",
  47         "T4240QDS_MDIO1",
  48         "T4240QDS_MDIO2",
  49         "T4240QDS_MDIO3",
  50         "T4240QDS_MDIO4",
  51         "T4240QDS_MDIO5",
  52         "NULL",
  53         "T4240QDS_MDIO7",
  54         "T4240QDS_10GC",
  55 };
  56
  57 static u8 lane_to_slot_fsm1[] = {1, 1, 1, 1, 2, 2, 2, 2};
  58 static u8 lane_to_slot_fsm2[] = {3, 3, 3, 3, 4, 4, 4, 4};
  59 static u8 slot_qsgmii_phyaddr[5][4] = {
  60         {0, 0, 0, 0},/* not used, to make index match slot No. */
  61         {0, 1, 2, 3},
  62         {4, 5, 6, 7},
  63         {8, 9, 0xa, 0xb},
  64         {0xc, 0xd, 0xe, 0xf},
  65 };
  66 static u8 qsgmiiphy_fix[NUM_FM_PORTS] = {0};
  67
  68 static const char *t4240qds_mdio_name_for_muxval(u8 muxval)
  69 {
  70         return mdio_names[muxval];
  71 }
  72
  73 struct mii_dev *mii_dev_for_muxval(u8 muxval)
  74 {
  75         struct mii_dev *bus;
  76         const char *name = t4240qds_mdio_name_for_muxval(muxval);
  77
  78         if (!name) {
  79                 printf("No bus for muxval %x\n", muxval);
  80                 return NULL;
  81         }
  82
  83         bus = miiphy_get_dev_by_name(name);
  84
  85         if (!bus) {
  86                 printf("No bus by name %s\n", name);
  87                 return NULL;
  88         }
  89
  90         return bus;
  91 }
  92
  93 struct t4240qds_mdio {
  94         u8 muxval;
  95         struct mii_dev *realbus;
  96 };
  97
  98 static void t4240qds_mux_mdio(u8 muxval)
  99 {
 100         u8 brdcfg4;
 101         if ((muxval < 6) || (muxval == 7)) {
 102                 brdcfg4 = QIXIS_READ(brdcfg[4]);
 103                 brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
 104                 brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
 105                 QIXIS_WRITE(brdcfg[4], brdcfg4);
 106         }
 107 }
 108
 109 static int t4240qds_mdio_read(struct mii_dev *bus, int addr, int devad,
 110                                 int regnum)
 111 {
 112         struct t4240qds_mdio *priv = bus->priv;
 113
 114         t4240qds_mux_mdio(priv->muxval);
 115
 116         return priv->realbus->read(priv->realbus, addr, devad, regnum);
 117 }
 118
 119 static int t4240qds_mdio_write(struct mii_dev *bus, int addr, int devad,
 120                                 int regnum, u16 value)
 121 {
 122         struct t4240qds_mdio *priv = bus->priv;
 123
 124         t4240qds_mux_mdio(priv->muxval);
 125
 126         return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
 127 }
 128
 129 static int t4240qds_mdio_reset(struct mii_dev *bus)
 130 {
 131         struct t4240qds_mdio *priv = bus->priv;
 132
 133         return priv->realbus->reset(priv->realbus);
 134 }
 135
 136 static int t4240qds_mdio_init(char *realbusname, u8 muxval)
 137 {
 138         struct t4240qds_mdio *pmdio;
 139         struct mii_dev *bus = mdio_alloc();
 140
 141         if (!bus) {
 142                 printf("Failed to allocate T4240QDS MDIO bus\n");
 143                 return -1;
 144         }
 145
 146         pmdio = malloc(sizeof(*pmdio));
 147         if (!pmdio) {
 148                 printf("Failed to allocate T4240QDS private data\n");
 149                 free(bus);
 150                 return -1;
 151         }
 152
 153         bus->read = t4240qds_mdio_read;
 154         bus->write = t4240qds_mdio_write;
 155         bus->reset = t4240qds_mdio_reset;
 156         strcpy(bus->name, t4240qds_mdio_name_for_muxval(muxval));
 157
 158         pmdio->realbus = miiphy_get_dev_by_name(realbusname);
 159
 160         if (!pmdio->realbus) {
 161                 printf("No bus with name %s\n", realbusname);
 162                 free(bus);
 163                 free(pmdio);
 164                 return -1;
 165         }
 166
 167         pmdio->muxval = muxval;
 168         bus->priv = pmdio;
 169
 170         return mdio_register(bus);
 171 }
 172
 173 void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
 174                                 enum fm_port port, int offset)
 175 {
 176         int interface = fm_info_get_enet_if(port);
 177         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 178         u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
 179
 180         prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
 181
 182         if (interface == PHY_INTERFACE_MODE_SGMII ||
 183             interface == PHY_INTERFACE_MODE_QSGMII) {
 184                 switch (port) {
 185                 case FM1_DTSEC1:
 186                         if (qsgmiiphy_fix[port])
 187                                 fdt_set_phy_handle(blob, prop, pa,
 188                                                    "sgmii_phy21");
 189                         break;
 190                 case FM1_DTSEC2:
 191                         if (qsgmiiphy_fix[port])
 192                                 fdt_set_phy_handle(blob, prop, pa,
 193                                                    "sgmii_phy22");
 194                         break;
 195                 case FM1_DTSEC3:
 196                         if (qsgmiiphy_fix[port])
 197                                 fdt_set_phy_handle(blob, prop, pa,
 198                                                    "sgmii_phy23");
 199                         break;
 200                 case FM1_DTSEC4:
 201                         if (qsgmiiphy_fix[port])
 202                                 fdt_set_phy_handle(blob, prop, pa,
 203                                                    "sgmii_phy24");
 204                         break;
 205                 case FM1_DTSEC6:
 206                         if (qsgmiiphy_fix[port])
 207                                 fdt_set_phy_handle(blob, prop, pa,
 208                                                    "sgmii_phy12");
 209                         break;
 210                 case FM1_DTSEC9:
 211                         if (qsgmiiphy_fix[port])
 212                                 fdt_set_phy_handle(blob, prop, pa,
 213                                                    "sgmii_phy14");
 214                         else
 215                                 fdt_set_phy_handle(blob, prop, pa,
 216                                                    "phy_sgmii4");
 217                         break;
 218                 case FM1_DTSEC10:
 219                         if (qsgmiiphy_fix[port])
 220                                 fdt_set_phy_handle(blob, prop, pa,
 221                                                    "sgmii_phy13");
 222                         else
 223                                 fdt_set_phy_handle(blob, prop, pa,
 224                                                    "phy_sgmii3");
 225                         break;
 226                 case FM2_DTSEC1:
 227                         if (qsgmiiphy_fix[port])
 228                                 fdt_set_phy_handle(blob, prop, pa,
 229                                                    "sgmii_phy41");
 230                         break;
 231                 case FM2_DTSEC2:
 232                         if (qsgmiiphy_fix[port])
 233                                 fdt_set_phy_handle(blob, prop, pa,
 234                                                    "sgmii_phy42");
 235                         break;
 236                 case FM2_DTSEC3:
 237                         if (qsgmiiphy_fix[port])
 238                                 fdt_set_phy_handle(blob, prop, pa,
 239                                                    "sgmii_phy43");
 240                         break;
 241                 case FM2_DTSEC4:
 242                         if (qsgmiiphy_fix[port])
 243                                 fdt_set_phy_handle(blob, prop, pa,
 244                                                    "sgmii_phy44");
 245                         break;
 246                 case FM2_DTSEC6:
 247                         if (qsgmiiphy_fix[port])
 248                                 fdt_set_phy_handle(blob, prop, pa,
 249                                                    "sgmii_phy32");
 250                         break;
 251                 case FM2_DTSEC9:
 252                         if (qsgmiiphy_fix[port])
 253                                 fdt_set_phy_handle(blob, prop, pa,
 254                                                    "sgmii_phy34");
 255                         else
 256                                 fdt_set_phy_handle(blob, prop, pa,
 257                                                    "phy_sgmii12");
 258                         break;
 259                 case FM2_DTSEC10:
 260                         if (qsgmiiphy_fix[port])
 261                                 fdt_set_phy_handle(blob, prop, pa,
 262                                                    "sgmii_phy33");
 263                         else
 264                                 fdt_set_phy_handle(blob, prop, pa,
 265                                                    "phy_sgmii11");
 266                         break;
 267                 default:
 268                         break;
 269                 }
 270         } else if (interface == PHY_INTERFACE_MODE_XGMII &&
 271                   ((prtcl2 == 55) || (prtcl2 == 57))) {
 272                 /*
 273                  * if the 10G is XFI, check hwconfig to see what is the
 274                  * media type, there are two types, fiber or copper,
 275                  * fix the dtb accordingly.
 276                  */
 277                 int media_type = 0;
 278                 struct fixed_link f_link;
 279                 char lane_mode[20] = {"10GBASE-KR"};
 280                 char buf[32] = "serdes-2,";
 281                 int off;
 282
 283                 switch (port) {
 284                 case FM1_10GEC1:
 285                         if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g1")) {
 286                                 media_type = 1;
 287                                 fdt_set_phy_handle(blob, prop, pa,
 288                                                    "phy_xfi1");
 289                                 sprintf(buf, "%s%s%s", buf, "lane-a,",
 290                                         (char *)lane_mode);
 291                         }
 292                         break;
 293                 case FM1_10GEC2:
 294                         if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g2")) {
 295                                 media_type = 1;
 296                                 fdt_set_phy_handle(blob, prop, pa,
 297                                                    "phy_xfi2");
 298                                 sprintf(buf, "%s%s%s", buf, "lane-b,",
 299                                         (char *)lane_mode);
 300                         }
 301                         break;
 302                 case FM2_10GEC1:
 303                         if (hwconfig_sub("fsl_10gkr_copper", "fm2_10g1")) {
 304                                 media_type = 1;
 305                                 fdt_set_phy_handle(blob, prop, pa,
 306                                                    "phy_xfi3");
 307                                 sprintf(buf, "%s%s%s", buf, "lane-d,",
 308                                         (char *)lane_mode);
 309                         }
 310                         break;
 311                 case FM2_10GEC2:
 312                         if (hwconfig_sub("fsl_10gkr_copper", "fm2_10g2")) {
 313                                 media_type = 1;
 314                                 fdt_set_phy_handle(blob, prop, pa,
 315                                                    "phy_xfi4");
 316                                 sprintf(buf, "%s%s%s", buf, "lane-c,",
 317                                         (char *)lane_mode);
 318                         }
 319                         break;
 320                 default:
 321                         return;
 322                 }
 323
 324                 if (!media_type) {
 325                         /* fixed-link is used for XFI fiber cable */
 326                         fdt_delprop(blob, offset, "phy-handle");
 327                         f_link.phy_id = port;
 328                         f_link.duplex = 1;
 329                         f_link.link_speed = 10000;
 330                         f_link.pause = 0;
 331                         f_link.asym_pause = 0;
 332                         fdt_setprop(blob, offset, "fixed-link", &f_link,
 333                                     sizeof(f_link));
 334                 } else {
 335                         /* set property for copper cable */
 336                         off = fdt_node_offset_by_compat_reg(blob,
 337                                         "fsl,fman-memac-mdio", pa + 0x1000);
 338                         fdt_setprop_string(blob, off, "lane-instance", buf);
 339                 }
 340         }
 341 }
 342
 343 void fdt_fixup_board_enet(void *fdt)
 344 {
 345         int i;
 346         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 347         u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
 348
 349         prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
 350         for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) {
 351                 switch (fm_info_get_enet_if(i)) {
 352                 case PHY_INTERFACE_MODE_SGMII:
 353                 case PHY_INTERFACE_MODE_QSGMII:
 354                         switch (mdio_mux[i]) {
 355                         case EMI1_SLOT1:
 356                                 fdt_status_okay_by_alias(fdt, "emi1_slot1");
 357                                 break;
 358                         case EMI1_SLOT2:
 359                                 fdt_status_okay_by_alias(fdt, "emi1_slot2");
 360                                 break;
 361                         case EMI1_SLOT3:
 362                                 fdt_status_okay_by_alias(fdt, "emi1_slot3");
 363                                 break;
 364                         case EMI1_SLOT4:
 365                                 fdt_status_okay_by_alias(fdt, "emi1_slot4");
 366                                 break;
 367                         default:
 368                                 break;
 369                         }
 370                         break;
 371                 case PHY_INTERFACE_MODE_XGMII:
 372                         /* check if it's XFI interface for 10g */
 373                         if ((prtcl2 == 55) || (prtcl2 == 57)) {
 374                                 if (i == FM1_10GEC1 && hwconfig_sub(
 375                                         "fsl_10gkr_copper", "fm1_10g1"))
 376                                         fdt_status_okay_by_alias(
 377                                         fdt, "xfi_pcs_mdio1");
 378                                 if (i == FM1_10GEC2 && hwconfig_sub(
 379                                         "fsl_10gkr_copper", "fm1_10g2"))
 380                                         fdt_status_okay_by_alias(
 381                                         fdt, "xfi_pcs_mdio2");
 382                                 if (i == FM2_10GEC1 && hwconfig_sub(
 383                                         "fsl_10gkr_copper", "fm2_10g1"))
 384                                         fdt_status_okay_by_alias(
 385                                         fdt, "xfi_pcs_mdio3");
 386                                 if (i == FM2_10GEC2 && hwconfig_sub(
 387                                         "fsl_10gkr_copper", "fm2_10g2"))
 388                                         fdt_status_okay_by_alias(
 389                                         fdt, "xfi_pcs_mdio4");
 390                                 break;
 391                         }
 392                         switch (i) {
 393                         case FM1_10GEC1:
 394                                 fdt_status_okay_by_alias(fdt, "emi2_xauislot1");
 395                                 break;
 396                         case FM1_10GEC2:
 397                                 fdt_status_okay_by_alias(fdt, "emi2_xauislot2");
 398                                 break;
 399                         case FM2_10GEC1:
 400                                 fdt_status_okay_by_alias(fdt, "emi2_xauislot3");
 401                                 break;
 402                         case FM2_10GEC2:
 403                                 fdt_status_okay_by_alias(fdt, "emi2_xauislot4");
 404                                 break;
 405                         default:
 406                                 break;
 407                         }
 408                         break;
 409                 default:
 410                         break;
 411                 }
 412         }
 413 }
 414
 415 static void initialize_qsgmiiphy_fix(void)
 416 {
 417         int i;
 418         unsigned short reg;
 419
 420         for (i = 1; i <= 4; i++) {
 421                 /*
 422                  * Try to read if a SGMII card is used, we do it slot by slot.
 423                  * if a SGMII PHY address is valid on a slot, then we mark
 424                  * all ports on the slot, then fix the PHY address for the
 425                  * marked port when doing dtb fixup.
 426                  */
 427                 if (miiphy_read(mdio_names[i],
 428                                 SGMII_CARD_PORT1_PHY_ADDR, MII_PHYSID2, &reg) != 0) {
 429                         debug("Slot%d PHY ID register 2 read failed\n", i);
 430                         continue;
 431                 }
 432
 433                 debug("Slot%d MII_PHYSID2 @ 0x1c= 0x%04x\n", i, reg);
 434
 435                 if (reg == 0xFFFF) {
 436                         /* No physical device present at this address */
 437                         continue;
 438                 }
 439
 440                 switch (i) {
 441                 case 1:
 442                         qsgmiiphy_fix[FM1_DTSEC5] = 1;
 443                         qsgmiiphy_fix[FM1_DTSEC6] = 1;
 444                         qsgmiiphy_fix[FM1_DTSEC9] = 1;
 445                         qsgmiiphy_fix[FM1_DTSEC10] = 1;
 446                         slot_qsgmii_phyaddr[1][0] =  SGMII_CARD_PORT1_PHY_ADDR;
 447                         slot_qsgmii_phyaddr[1][1] =  SGMII_CARD_PORT2_PHY_ADDR;
 448                         slot_qsgmii_phyaddr[1][2] =  SGMII_CARD_PORT3_PHY_ADDR;
 449                         slot_qsgmii_phyaddr[1][3] =  SGMII_CARD_PORT4_PHY_ADDR;
 450                         break;
 451                 case 2:
 452                         qsgmiiphy_fix[FM1_DTSEC1] = 1;
 453                         qsgmiiphy_fix[FM1_DTSEC2] = 1;
 454                         qsgmiiphy_fix[FM1_DTSEC3] = 1;
 455                         qsgmiiphy_fix[FM1_DTSEC4] = 1;
 456                         slot_qsgmii_phyaddr[2][0] =  SGMII_CARD_PORT1_PHY_ADDR;
 457                         slot_qsgmii_phyaddr[2][1] =  SGMII_CARD_PORT2_PHY_ADDR;
 458                         slot_qsgmii_phyaddr[2][2] =  SGMII_CARD_PORT3_PHY_ADDR;
 459                         slot_qsgmii_phyaddr[2][3] =  SGMII_CARD_PORT4_PHY_ADDR;
 460                         break;
 461                 case 3:
 462                         qsgmiiphy_fix[FM2_DTSEC5] = 1;
 463                         qsgmiiphy_fix[FM2_DTSEC6] = 1;
 464                         qsgmiiphy_fix[FM2_DTSEC9] = 1;
 465                         qsgmiiphy_fix[FM2_DTSEC10] = 1;
 466                         slot_qsgmii_phyaddr[3][0] =  SGMII_CARD_PORT1_PHY_ADDR;
 467                         slot_qsgmii_phyaddr[3][1] =  SGMII_CARD_PORT2_PHY_ADDR;
 468                         slot_qsgmii_phyaddr[3][2] =  SGMII_CARD_PORT3_PHY_ADDR;
 469                         slot_qsgmii_phyaddr[3][3] =  SGMII_CARD_PORT4_PHY_ADDR;
 470                         break;
 471                 case 4:
 472                         qsgmiiphy_fix[FM2_DTSEC1] = 1;
 473                         qsgmiiphy_fix[FM2_DTSEC2] = 1;
 474                         qsgmiiphy_fix[FM2_DTSEC3] = 1;
 475                         qsgmiiphy_fix[FM2_DTSEC4] = 1;
 476                         slot_qsgmii_phyaddr[4][0] =  SGMII_CARD_PORT1_PHY_ADDR;
 477                         slot_qsgmii_phyaddr[4][1] =  SGMII_CARD_PORT2_PHY_ADDR;
 478                         slot_qsgmii_phyaddr[4][2] =  SGMII_CARD_PORT3_PHY_ADDR;
 479                         slot_qsgmii_phyaddr[4][3] =  SGMII_CARD_PORT4_PHY_ADDR;
 480                         break;
 481                 default:
 482                         break;
 483                 }
 484         }
 485 }
 486
 487 int board_eth_init(bd_t *bis)
 488 {
 489 #if defined(CONFIG_FMAN_ENET)
 490         int i, idx, lane, slot, interface;
 491         struct memac_mdio_info dtsec_mdio_info;
 492         struct memac_mdio_info tgec_mdio_info;
 493         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 494         u32 srds_prtcl_s1, srds_prtcl_s2;
 495
 496         srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
 497                                         FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
 498         srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
 499         srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
 500                                         FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
 501         srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
 502
 503         /* Initialize the mdio_mux array so we can recognize empty elements */
 504         for (i = 0; i < NUM_FM_PORTS; i++)
 505                 mdio_mux[i] = EMI_NONE;
 506
 507         dtsec_mdio_info.regs =
 508                 (struct memac_mdio_controller *)CONFIG_SYS_FM2_DTSEC_MDIO_ADDR;
 509
 510         dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
 511
 512         /* Register the 1G MDIO bus */
 513         fm_memac_mdio_init(bis, &dtsec_mdio_info);
 514
 515         tgec_mdio_info.regs =
 516                 (struct memac_mdio_controller *)CONFIG_SYS_FM2_TGEC_MDIO_ADDR;
 517         tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
 518
 519         /* Register the 10G MDIO bus */
 520         fm_memac_mdio_init(bis, &tgec_mdio_info);
 521
 522         /* Register the muxing front-ends to the MDIO buses */
 523         t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII);
 524         t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
 525         t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
 526         t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
 527         t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
 528         t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
 529         t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
 530         t4240qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
 531
 532         initialize_qsgmiiphy_fix();
 533
 534         switch (srds_prtcl_s1) {
 535         case 1:
 536         case 2:
 537         case 4:
 538                 /* XAUI/HiGig in Slot1 and Slot2 */
 539                 fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
 540                 fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR);
 541                 break;
 542         case 27:
 543         case 28:
 544         case 35:
 545         case 36:
 546                 /* SGMII in Slot1 and Slot2 */
 547                 fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
 548                 fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
 549                 fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
 550                 fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
 551                 fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
 552                 fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
 553                 if ((srds_prtcl_s2 != 55) && (srds_prtcl_s2 != 57)) {
 554                         fm_info_set_phy_address(FM1_DTSEC9,
 555                                                 slot_qsgmii_phyaddr[1][3]);
 556                         fm_info_set_phy_address(FM1_DTSEC10,
 557                                                 slot_qsgmii_phyaddr[1][2]);
 558                 }
 559                 break;
 560         case 37:
 561         case 38:
 562                 fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
 563                 fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
 564                 fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
 565                 fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
 566                 fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
 567                 fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
 568                 if ((srds_prtcl_s2 != 55) && (srds_prtcl_s2 != 57)) {
 569                         fm_info_set_phy_address(FM1_DTSEC9,
 570                                                 slot_qsgmii_phyaddr[1][2]);
 571                         fm_info_set_phy_address(FM1_DTSEC10,
 572                                                 slot_qsgmii_phyaddr[1][3]);
 573                 }
 574                 break;
 575         case 39:
 576         case 40:
 577         case 45:
 578         case 46:
 579         case 47:
 580         case 48:
 581                 fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
 582                 fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
 583                 if ((srds_prtcl_s2 != 55) && (srds_prtcl_s2 != 57)) {
 584                         fm_info_set_phy_address(FM1_DTSEC10,
 585                                                 slot_qsgmii_phyaddr[1][2]);
 586                         fm_info_set_phy_address(FM1_DTSEC9,
 587                                                 slot_qsgmii_phyaddr[1][3]);
 588                 }
 589                 fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
 590                 fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
 591                 fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
 592                 fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
 593                 break;
 594         default:
 595                 puts("Invalid SerDes1 protocol for T4240QDS\n");
 596                 break;
 597         }
 598
 599         for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
 600                 idx = i - FM1_DTSEC1;
 601                 interface = fm_info_get_enet_if(i);
 602                 switch (interface) {
 603                 case PHY_INTERFACE_MODE_SGMII:
 604                 case PHY_INTERFACE_MODE_QSGMII:
 605                         if (interface == PHY_INTERFACE_MODE_QSGMII) {
 606                                 if (idx <= 3)
 607                                         lane = serdes_get_first_lane(FSL_SRDS_1,
 608                                                         QSGMII_FM1_A);
 609                                 else
 610                                         lane = serdes_get_first_lane(FSL_SRDS_1,
 611                                                         QSGMII_FM1_B);
 612                                 if (lane < 0)
 613                                         break;
 614                                 slot = lane_to_slot_fsm1[lane];
 615                                 debug("FM1@DTSEC%u expects QSGMII in slot %u\n",
 616                                       idx + 1, slot);
 617                         } else {
 618                                 lane = serdes_get_first_lane(FSL_SRDS_1,
 619                                                 SGMII_FM1_DTSEC1 + idx);
 620                                 if (lane < 0)
 621                                         break;
 622                                 slot = lane_to_slot_fsm1[lane];
 623                                 debug("FM1@DTSEC%u expects SGMII in slot %u\n",
 624                                       idx + 1, slot);
 625                         }
 626                         if (QIXIS_READ(present2) & (1 << (slot - 1)))
 627                                 fm_disable_port(i);
 628                         switch (slot) {
 629                         case 1:
 630                                 mdio_mux[i] = EMI1_SLOT1;
 631                                 fm_info_set_mdio(i,
 632                                         mii_dev_for_muxval(mdio_mux[i]));
 633                                 break;
 634                         case 2:
 635                                 mdio_mux[i] = EMI1_SLOT2;
 636                                 fm_info_set_mdio(i,
 637                                         mii_dev_for_muxval(mdio_mux[i]));
 638                                 break;
 639                         };
 640                         break;
 641                 case PHY_INTERFACE_MODE_RGMII:
 642                         /* FM1 DTSEC5 routes to RGMII with EC2 */
 643                         debug("FM1@DTSEC%u is RGMII at address %u\n",
 644                                 idx + 1, 2);
 645                         if (i == FM1_DTSEC5)
 646                                 fm_info_set_phy_address(i, 2);
 647                         mdio_mux[i] = EMI1_RGMII;
 648                         fm_info_set_mdio(i,
 649                                 mii_dev_for_muxval(mdio_mux[i]));
 650                         break;
 651                 default:
 652                         break;
 653                 }
 654         }
 655
 656         for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
 657                 idx = i - FM1_10GEC1;
 658                 switch (fm_info_get_enet_if(i)) {
 659                 case PHY_INTERFACE_MODE_XGMII:
 660                         if ((srds_prtcl_s2 == 55) || (srds_prtcl_s2 == 57)) {
 661                                 /* A fake PHY address to make U-Boot happy */
 662                                 fm_info_set_phy_address(i, i);
 663                         } else {
 664                                 lane = serdes_get_first_lane(FSL_SRDS_1,
 665                                                 XAUI_FM1_MAC9 + idx);
 666                                 if (lane < 0)
 667                                         break;
 668                                 slot = lane_to_slot_fsm1[lane];
 669                                 if (QIXIS_READ(present2) & (1 << (slot - 1)))
 670                                         fm_disable_port(i);
 671                         }
 672                         mdio_mux[i] = EMI2;
 673                         fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
 674                         break;
 675                 default:
 676                         break;
 677                 }
 678         }
 679
 680 #if (CONFIG_SYS_NUM_FMAN == 2)
 681         switch (srds_prtcl_s2) {
 682         case 1:
 683         case 2:
 684         case 4:
 685                 /* XAUI/HiGig in Slot3 and Slot4 */
 686                 fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
 687                 fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC2_PHY_ADDR);
 688                 break;
 689         case 6:
 690         case 7:
 691         case 12:
 692         case 13:
 693         case 14:
 694         case 15:
 695         case 16:
 696         case 21:
 697         case 22:
 698         case 23:
 699         case 24:
 700         case 25:
 701         case 26:
 702                 /* XAUI/HiGig in Slot3, SGMII in Slot4 */
 703                 fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
 704                 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
 705                 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
 706                 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
 707                 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
 708                 break;
 709         case 27:
 710         case 28:
 711         case 35:
 712         case 36:
 713                 /* SGMII in Slot3 and Slot4 */
 714                 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
 715                 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
 716                 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
 717                 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
 718                 fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
 719                 fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
 720                 fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
 721                 fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
 722                 break;
 723         case 37:
 724         case 38:
 725                 /* QSGMII in Slot3 and Slot4 */
 726                 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
 727                 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
 728                 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
 729                 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
 730                 fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
 731                 fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
 732                 fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][2]);
 733                 fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][3]);
 734                 break;
 735         case 39:
 736         case 40:
 737         case 45:
 738         case 46:
 739         case 47:
 740         case 48:
 741                 /* SGMII in Slot3 */
 742                 fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
 743                 fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
 744                 fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
 745                 fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
 746                 /* QSGMII in Slot4 */
 747                 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
 748                 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
 749                 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
 750                 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
 751                 break;
 752         case 49:
 753         case 50:
 754         case 51:
 755         case 52:
 756         case 53:
 757         case 54:
 758                 fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
 759                 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
 760                 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
 761                 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
 762                 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
 763                 break;
 764         case 55:
 765         case 57:
 766                 /* XFI in Slot3, SGMII in Slot4 */
 767                 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
 768                 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
 769                 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
 770                 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
 771                 break;
 772         default:
 773                 puts("Invalid SerDes2 protocol for T4240QDS\n");
 774                 break;
 775         }
 776
 777         for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
 778                 idx = i - FM2_DTSEC1;
 779                 interface = fm_info_get_enet_if(i);
 780                 switch (interface) {
 781                 case PHY_INTERFACE_MODE_SGMII:
 782                 case PHY_INTERFACE_MODE_QSGMII:
 783                         if (interface == PHY_INTERFACE_MODE_QSGMII) {
 784                                 if (idx <= 3)
 785                                         lane = serdes_get_first_lane(FSL_SRDS_2,
 786                                                         QSGMII_FM2_A);
 787                                 else
 788                                         lane = serdes_get_first_lane(FSL_SRDS_2,
 789                                                         QSGMII_FM2_B);
 790                                 if (lane < 0)
 791                                         break;
 792                                 slot = lane_to_slot_fsm2[lane];
 793                                 debug("FM2@DTSEC%u expects QSGMII in slot %u\n",
 794                                       idx + 1, slot);
 795                         } else {
 796                                 lane = serdes_get_first_lane(FSL_SRDS_2,
 797                                                 SGMII_FM2_DTSEC1 + idx);
 798                                 if (lane < 0)
 799                                         break;
 800                                 slot = lane_to_slot_fsm2[lane];
 801                                 debug("FM2@DTSEC%u expects SGMII in slot %u\n",
 802                                       idx + 1, slot);
 803                         }
 804                         if (QIXIS_READ(present2) & (1 << (slot - 1)))
 805                                 fm_disable_port(i);
 806                         switch (slot) {
 807                         case 3:
 808                                 mdio_mux[i] = EMI1_SLOT3;
 809                                 fm_info_set_mdio(i,
 810                                         mii_dev_for_muxval(mdio_mux[i]));
 811                                 break;
 812                         case 4:
 813                                 mdio_mux[i] = EMI1_SLOT4;
 814                                 fm_info_set_mdio(i,
 815                                         mii_dev_for_muxval(mdio_mux[i]));
 816                                 break;
 817                         };
 818                         break;
 819                 case PHY_INTERFACE_MODE_RGMII:
 820                         /*
 821                          * If DTSEC5 is RGMII, then it's routed via via EC1 to
 822                          * the first on-board RGMII port.  If DTSEC6 is RGMII,
 823                          * then it's routed via via EC2 to the second on-board
 824                          * RGMII port.
 825                          */
 826                         debug("FM2@DTSEC%u is RGMII at address %u\n",
 827                                 idx + 1, i == FM2_DTSEC5 ? 1 : 2);
 828                         fm_info_set_phy_address(i, i == FM2_DTSEC5 ? 1 : 2);
 829                         mdio_mux[i] = EMI1_RGMII;
 830                         fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
 831                         break;
 832                 default:
 833                         break;
 834                 }
 835         }
 836
 837         for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
 838                 idx = i - FM2_10GEC1;
 839                 switch (fm_info_get_enet_if(i)) {
 840                 case PHY_INTERFACE_MODE_XGMII:
 841                         if ((srds_prtcl_s2 == 55) || (srds_prtcl_s2 == 57)) {
 842                                 /* A fake PHY address to make U-Boot happy */
 843                                 fm_info_set_phy_address(i, i);
 844                         } else {
 845                                 lane = serdes_get_first_lane(FSL_SRDS_2,
 846                                                 XAUI_FM2_MAC9 + idx);
 847                                 if (lane < 0)
 848                                         break;
 849                                 slot = lane_to_slot_fsm2[lane];
 850                                 if (QIXIS_READ(present2) & (1 << (slot - 1)))
 851                                         fm_disable_port(i);
 852                         }
 853                         mdio_mux[i] = EMI2;
 854                         fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
 855                         break;
 856                 default:
 857                         break;
 858                 }
 859         }
 860 #endif /* CONFIG_SYS_NUM_FMAN */
 861
 862         cpu_eth_init(bis);
 863 #endif /* CONFIG_FMAN_ENET */
 864
 865         return pci_eth_init(bis);
 866 }