board/freescale/ls1021atsn/ls1021atsn.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright 2016-2019 NXP Semiconductors
   3  */
   4 #include <common.h>
   5 #include <clock_legacy.h>
   6 #include <fdt_support.h>
   7 #include <init.h>
   8 #include <net.h>
   9 #include <asm/arch-ls102xa/ls102xa_soc.h>
  10 #include <asm/arch/ls102xa_devdis.h>
  11 #include <asm/arch/immap_ls102xa.h>
  12 #include <asm/arch/ls102xa_soc.h>
  13 #include <asm/arch/fsl_serdes.h>
  14 #include "../common/sleep.h"
  15 #include <fsl_validate.h>
  16 #include <fsl_immap.h>
  17 #include <fsl_csu.h>
  18 #include <netdev.h>
  19 #include <spl.h>
  20 #ifdef CONFIG_U_QE
  21 #include <fsl_qe.h>
  22 #endif
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 static void ddrmc_init(void)
  27 {
  28 #if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
  29         struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
  30         u32 temp_sdram_cfg, tmp;
  31
  32         out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
  33
  34         out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
  35         out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
  36
  37         out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
  38         out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
  39         out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
  40         out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
  41         out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
  42         out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
  43
  44 #ifdef CONFIG_DEEP_SLEEP
  45         if (is_warm_boot()) {
  46                 out_be32(&ddr->sdram_cfg_2,
  47                          DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT);
  48                 out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
  49                 out_be32(&ddr->init_ext_addr, (1 << 31));
  50
  51                 /* DRAM VRef will not be trained */
  52                 out_be32(&ddr->ddr_cdr2,
  53                          DDR_DDR_CDR2 & ~DDR_CDR2_VREF_TRAIN_EN);
  54         } else
  55 #endif
  56         {
  57                 out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
  58                 out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
  59         }
  60
  61         out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
  62         out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
  63
  64         out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
  65
  66         out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
  67
  68         out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
  69         out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
  70
  71         out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
  72
  73         out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
  74         out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
  75
  76         out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
  77
  78         /* DDR erratum A-009942 */
  79         tmp = in_be32(&ddr->debug[28]);
  80         out_be32(&ddr->debug[28], tmp | 0x0070006f);
  81
  82         udelay(1);
  83
  84 #ifdef CONFIG_DEEP_SLEEP
  85         if (is_warm_boot()) {
  86                 /* enter self-refresh */
  87                 temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
  88                 temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
  89                 out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
  90
  91                 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN | SDRAM_CFG_BI);
  92         } else
  93 #endif
  94                 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);
  95
  96         out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
  97
  98 #ifdef CONFIG_DEEP_SLEEP
  99         if (is_warm_boot()) {
 100                 /* exit self-refresh */
 101                 temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
 102                 temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
 103                 out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
 104         }
 105 #endif
 106 #endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */
 107 }
 108
 109 int dram_init(void)
 110 {
 111         ddrmc_init();
 112
 113         erratum_a008850_post();
 114
 115         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
 116
 117 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
 118         fsl_dp_resume();
 119 #endif
 120
 121         return 0;
 122 }
 123
 124 int board_eth_init(bd_t *bis)
 125 {
 126         return pci_eth_init(bis);
 127 }
 128
 129 int board_early_init_f(void)
 130 {
 131         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 132
 133 #ifdef CONFIG_TSEC_ENET
 134         /*
 135          * Clear BD & FR bits for big endian BD's and frame data (aka set
 136          * correct eTSEC endianness). This is crucial in ensuring that it does
 137          * not report Data Parity Errors in its RX/TX FIFOs when attempting to
 138          * send traffic.
 139          */
 140         clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
 141         /* EC3_GTX_CLK125 (of enet2) used for all RGMII interfaces */
 142         out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
 143 #endif
 144
 145         arch_soc_init();
 146
 147 #if defined(CONFIG_DEEP_SLEEP)
 148         if (is_warm_boot()) {
 149                 timer_init();
 150                 dram_init();
 151         }
 152 #endif
 153
 154         return 0;
 155 }
 156
 157 #ifdef CONFIG_SPL_BUILD
 158 void board_init_f(ulong dummy)
 159 {
 160         void (*second_uboot)(void);
 161
 162         /* Clear the BSS */
 163         memset(__bss_start, 0, __bss_end - __bss_start);
 164
 165         get_clocks();
 166
 167 #if defined(CONFIG_DEEP_SLEEP)
 168         if (is_warm_boot())
 169                 fsl_dp_disable_console();
 170 #endif
 171
 172         preloader_console_init();
 173
 174         dram_init();
 175
 176         /* Allow OCRAM access permission as R/W */
 177 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
 178         enable_layerscape_ns_access();
 179         enable_layerscape_ns_access();
 180 #endif
 181
 182         /*
 183          * if it is woken up from deep sleep, then jump to second
 184          * stage U-Boot and continue executing without recopying
 185          * it from SD since it has already been reserved in memory
 186          * in last boot.
 187          */
 188         if (is_warm_boot()) {
 189                 second_uboot = (void (*)(void))CONFIG_SYS_TEXT_BASE;
 190                 second_uboot();
 191         }
 192
 193         board_init_r(NULL, 0);
 194 }
 195 #endif
 196
 197 int board_init(void)
 198 {
 199 #ifndef CONFIG_SYS_FSL_NO_SERDES
 200         fsl_serdes_init();
 201 #endif
 202         ls102xa_smmu_stream_id_init();
 203
 204 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
 205         enable_layerscape_ns_access();
 206 #endif
 207
 208 #ifdef CONFIG_U_QE
 209         u_qe_init();
 210 #endif
 211
 212         return 0;
 213 }
 214
 215 #if defined(CONFIG_SPL_BUILD)
 216 void spl_board_init(void)
 217 {
 218         ls102xa_smmu_stream_id_init();
 219 }
 220 #endif
 221
 222 #ifdef CONFIG_BOARD_LATE_INIT
 223 int board_late_init(void)
 224 {
 225 #ifdef CONFIG_CHAIN_OF_TRUST
 226         fsl_setenv_chain_of_trust();
 227 #endif
 228
 229         return 0;
 230 }
 231 #endif
 232
 233 #if defined(CONFIG_MISC_INIT_R)
 234 int misc_init_r(void)
 235 {
 236 #ifdef CONFIG_FSL_DEVICE_DISABLE
 237         device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
 238 #endif
 239
 240 #ifdef CONFIG_FSL_CAAM
 241         return sec_init();
 242 #endif
 243 }
 244 #endif
 245
 246 #if defined(CONFIG_DEEP_SLEEP)
 247 void board_sleep_prepare(void)
 248 {
 249 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
 250         enable_layerscape_ns_access();
 251 #endif
 252 }
 253 #endif
 254
 255 int ft_board_setup(void *blob, bd_t *bd)
 256 {
 257         ft_cpu_setup(blob, bd);
 258
 259 #ifdef CONFIG_PCI
 260         ft_pci_setup(blob, bd);
 261 #endif
 262
 263         return 0;
 264 }