board/freescale/lx2160a/lx2160a.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2018-2020 NXP
   4  */
   5
   6 #include <common.h>
   7 #include <clock_legacy.h>
   8 #include <dm.h>
   9 #include <init.h>
  10 #include <dm/platform_data/serial_pl01x.h>
  11 #include <i2c.h>
  12 #include <malloc.h>
  13 #include <errno.h>
  14 #include <netdev.h>
  15 #include <fsl_ddr.h>
  16 #include <fsl_sec.h>
  17 #include <asm/io.h>
  18 #include <fdt_support.h>
  19 #include <linux/bitops.h>
  20 #include <linux/libfdt.h>
  21 #include <linux/delay.h>
  22 #include <fsl-mc/fsl_mc.h>
  23 #include <env_internal.h>
  24 #include <efi_loader.h>
  25 #include <asm/arch/mmu.h>
  26 #include <hwconfig.h>
  27 #include <asm/arch/clock.h>
  28 #include <asm/arch/config.h>
  29 #include <asm/arch/fsl_serdes.h>
  30 #include <asm/arch/soc.h>
  31 #include "../common/qixis.h"
  32 #include "../common/vid.h"
  33 #include <fsl_immap.h>
  34 #include <asm/arch-fsl-layerscape/fsl_icid.h>
  35
  36 #ifdef CONFIG_EMC2305
  37 #include "../common/emc2305.h"
  38 #endif
  39
  40 #ifdef CONFIG_TARGET_LX2160AQDS
  41 #define CFG_MUX_I2C_SDHC(reg, value)            ((reg & 0x3f) | value)
  42 #define SET_CFG_MUX1_SDHC1_SDHC(reg)            (reg & 0x3f)
  43 #define SET_CFG_MUX2_SDHC1_SPI(reg, value)      ((reg & 0xcf) | value)
  44 #define SET_CFG_MUX3_SDHC1_SPI(reg, value)      ((reg & 0xf8) | value)
  45 #define SET_CFG_MUX_SDHC2_DSPI(reg, value)      ((reg & 0xf8) | value)
  46 #define SET_CFG_MUX1_SDHC1_DSPI(reg, value)     ((reg & 0x3f) | value)
  47 #define SDHC1_BASE_PMUX_DSPI                    2
  48 #define SDHC2_BASE_PMUX_DSPI                    2
  49 #define IIC5_PMUX_SPI3                          3
  50 #endif /* CONFIG_TARGET_LX2160AQDS */
  51
  52 DECLARE_GLOBAL_DATA_PTR;
  53
  54 static struct pl01x_serial_platdata serial0 = {
  55 #if CONFIG_CONS_INDEX == 0
  56         .base = CONFIG_SYS_SERIAL0,
  57 #elif CONFIG_CONS_INDEX == 1
  58         .base = CONFIG_SYS_SERIAL1,
  59 #else
  60 #error "Unsupported console index value."
  61 #endif
  62         .type = TYPE_PL011,
  63 };
  64
  65 U_BOOT_DEVICE(nxp_serial0) = {
  66         .name = "serial_pl01x",
  67         .platdata = &serial0,
  68 };
  69
  70 static struct pl01x_serial_platdata serial1 = {
  71         .base = CONFIG_SYS_SERIAL1,
  72         .type = TYPE_PL011,
  73 };
  74
  75 U_BOOT_DEVICE(nxp_serial1) = {
  76         .name = "serial_pl01x",
  77         .platdata = &serial1,
  78 };
  79
  80 int select_i2c_ch_pca9547(u8 ch)
  81 {
  82         int ret;
  83
  84 #ifndef CONFIG_DM_I2C
  85         ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  86 #else
  87         struct udevice *dev;
  88
  89         ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
  90         if (!ret)
  91                 ret = dm_i2c_write(dev, 0, &ch, 1);
  92 #endif
  93         if (ret) {
  94                 puts("PCA: failed to select proper channel\n");
  95                 return ret;
  96         }
  97
  98         return 0;
  99 }
 100
 101 static void uart_get_clock(void)
 102 {
 103         serial0.clock = get_serial_clock();
 104         serial1.clock = get_serial_clock();
 105 }
 106
 107 int board_early_init_f(void)
 108 {
 109 #ifdef CONFIG_SYS_I2C_EARLY_INIT
 110         i2c_early_init_f();
 111 #endif
 112         /* get required clock for UART IP */
 113         uart_get_clock();
 114
 115 #ifdef CONFIG_EMC2305
 116         select_i2c_ch_pca9547(I2C_MUX_CH_EMC2305);
 117         emc2305_init(I2C_EMC2305_ADDR);
 118         set_fan_speed(I2C_EMC2305_PWM, I2C_EMC2305_ADDR);
 119         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 120 #endif
 121
 122         fsl_lsch3_early_init_f();
 123         return 0;
 124 }
 125
 126 #ifdef CONFIG_OF_BOARD_FIXUP
 127 int board_fix_fdt(void *fdt)
 128 {
 129         char *reg_names, *reg_name;
 130         int names_len, old_name_len, new_name_len, remaining_names_len;
 131         struct str_map {
 132                 char *old_str;
 133                 char *new_str;
 134         } reg_names_map[] = {
 135                 { "ccsr", "dbi" },
 136                 { "pf_ctrl", "ctrl" }
 137         };
 138         int off = -1, i = 0;
 139
 140         if (IS_SVR_REV(get_svr(), 1, 0))
 141                 return 0;
 142
 143         off = fdt_node_offset_by_compatible(fdt, -1, "fsl,lx2160a-pcie");
 144         while (off != -FDT_ERR_NOTFOUND) {
 145                 fdt_setprop(fdt, off, "compatible", "fsl,ls-pcie",
 146                             strlen("fsl,ls-pcie") + 1);
 147
 148                 reg_names = (char *)fdt_getprop(fdt, off, "reg-names",
 149                                                 &names_len);
 150                 if (!reg_names)
 151                         continue;
 152
 153                 reg_name = reg_names;
 154                 remaining_names_len = names_len - (reg_name - reg_names);
 155                 i = 0;
 156                 while ((i < ARRAY_SIZE(reg_names_map)) && remaining_names_len) {
 157                         old_name_len = strlen(reg_names_map[i].old_str);
 158                         new_name_len = strlen(reg_names_map[i].new_str);
 159                         if (memcmp(reg_name, reg_names_map[i].old_str,
 160                                    old_name_len) == 0) {
 161                                 /* first only leave required bytes for new_str
 162                                  * and copy rest of the string after it
 163                                  */
 164                                 memcpy(reg_name + new_name_len,
 165                                        reg_name + old_name_len,
 166                                        remaining_names_len - old_name_len);
 167                                 /* Now copy new_str */
 168                                 memcpy(reg_name, reg_names_map[i].new_str,
 169                                        new_name_len);
 170                                 names_len -= old_name_len;
 171                                 names_len += new_name_len;
 172                                 i++;
 173                         }
 174
 175                         reg_name = memchr(reg_name, '\0', remaining_names_len);
 176                         if (!reg_name)
 177                                 break;
 178
 179                         reg_name += 1;
 180
 181                         remaining_names_len = names_len -
 182                                               (reg_name - reg_names);
 183                 }
 184
 185                 fdt_setprop(fdt, off, "reg-names", reg_names, names_len);
 186                 off = fdt_node_offset_by_compatible(fdt, off,
 187                                                     "fsl,lx2160a-pcie");
 188         }
 189
 190         return 0;
 191 }
 192 #endif
 193
 194 #if defined(CONFIG_TARGET_LX2160AQDS)
 195 void esdhc_dspi_status_fixup(void *blob)
 196 {
 197         const char esdhc0_path[] = "/soc/esdhc@2140000";
 198         const char esdhc1_path[] = "/soc/esdhc@2150000";
 199         const char dspi0_path[] = "/soc/spi@2100000";
 200         const char dspi1_path[] = "/soc/spi@2110000";
 201         const char dspi2_path[] = "/soc/spi@2120000";
 202
 203         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 204         u32 sdhc1_base_pmux;
 205         u32 sdhc2_base_pmux;
 206         u32 iic5_pmux;
 207
 208         /* Check RCW field sdhc1_base_pmux to enable/disable
 209          * esdhc0/dspi0 DT node
 210          */
 211         sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
 212                 & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;
 213         sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;
 214
 215         if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {
 216                 do_fixup_by_path(blob, dspi0_path, "status", "okay",
 217                                  sizeof("okay"), 1);
 218                 do_fixup_by_path(blob, esdhc0_path, "status", "disabled",
 219                                  sizeof("disabled"), 1);
 220         } else {
 221                 do_fixup_by_path(blob, esdhc0_path, "status", "okay",
 222                                  sizeof("okay"), 1);
 223                 do_fixup_by_path(blob, dspi0_path, "status", "disabled",
 224                                  sizeof("disabled"), 1);
 225         }
 226
 227         /* Check RCW field sdhc2_base_pmux to enable/disable
 228          * esdhc1/dspi1 DT node
 229          */
 230         sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])
 231                 & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;
 232         sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;
 233
 234         if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {
 235                 do_fixup_by_path(blob, dspi1_path, "status", "okay",
 236                                  sizeof("okay"), 1);
 237                 do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
 238                                  sizeof("disabled"), 1);
 239         } else {
 240                 do_fixup_by_path(blob, esdhc1_path, "status", "okay",
 241                                  sizeof("okay"), 1);
 242                 do_fixup_by_path(blob, dspi1_path, "status", "disabled",
 243                                  sizeof("disabled"), 1);
 244         }
 245
 246         /* Check RCW field IIC5 to enable dspi2 DT node */
 247         iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
 248                 & FSL_CHASSIS3_IIC5_PMUX_MASK;
 249         iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
 250
 251         if (iic5_pmux == IIC5_PMUX_SPI3)
 252                 do_fixup_by_path(blob, dspi2_path, "status", "okay",
 253                                  sizeof("okay"), 1);
 254         else
 255                 do_fixup_by_path(blob, dspi2_path, "status", "disabled",
 256                                  sizeof("disabled"), 1);
 257 }
 258 #endif
 259
 260 int esdhc_status_fixup(void *blob, const char *compat)
 261 {
 262 #if defined(CONFIG_TARGET_LX2160AQDS)
 263         /* Enable esdhc and dspi DT nodes based on RCW fields */
 264         esdhc_dspi_status_fixup(blob);
 265 #else
 266         /* Enable both esdhc DT nodes for LX2160ARDB */
 267         do_fixup_by_compat(blob, compat, "status", "okay",
 268                            sizeof("okay"), 1);
 269 #endif
 270         return 0;
 271 }
 272
 273 #if defined(CONFIG_VID)
 274 int i2c_multiplexer_select_vid_channel(u8 channel)
 275 {
 276         return select_i2c_ch_pca9547(channel);
 277 }
 278
 279 int init_func_vid(void)
 280 {
 281         int set_vid;
 282
 283         if (IS_SVR_REV(get_svr(), 1, 0))
 284                 set_vid = adjust_vdd(800);
 285         else
 286                 set_vid = adjust_vdd(0);
 287
 288         if (set_vid < 0)
 289                 printf("core voltage not adjusted\n");
 290
 291         return 0;
 292 }
 293 #endif
 294
 295 int checkboard(void)
 296 {
 297         enum boot_src src = get_boot_src();
 298         char buf[64];
 299         u8 sw;
 300 #ifdef CONFIG_TARGET_LX2160AQDS
 301         int clock;
 302         static const char *const freq[] = {"100", "125", "156.25",
 303                                            "161.13", "322.26", "", "", "",
 304                                            "", "", "", "", "", "", "",
 305                                            "100 separate SSCG"};
 306 #endif
 307
 308         cpu_name(buf);
 309 #ifdef CONFIG_TARGET_LX2160AQDS
 310         printf("Board: %s-QDS, ", buf);
 311 #else
 312         printf("Board: %s-RDB, ", buf);
 313 #endif
 314
 315         sw = QIXIS_READ(arch);
 316         printf("Board version: %c, boot from ", (sw & 0xf) - 1 + 'A');
 317
 318         if (src == BOOT_SOURCE_SD_MMC) {
 319                 puts("SD\n");
 320         } else if (src == BOOT_SOURCE_SD_MMC2) {
 321                 puts("eMMC\n");
 322         } else {
 323                 sw = QIXIS_READ(brdcfg[0]);
 324                 sw = (sw >> QIXIS_XMAP_SHIFT) & QIXIS_XMAP_MASK;
 325                 switch (sw) {
 326                 case 0:
 327                 case 4:
 328                         puts("FlexSPI DEV#0\n");
 329                         break;
 330                 case 1:
 331                         puts("FlexSPI DEV#1\n");
 332                         break;
 333                 case 2:
 334                 case 3:
 335                         puts("FlexSPI EMU\n");
 336                         break;
 337                 default:
 338                         printf("invalid setting, xmap: %d\n", sw);
 339                         break;
 340                 }
 341         }
 342 #ifdef CONFIG_TARGET_LX2160AQDS
 343         printf("FPGA: v%d (%s), build %d",
 344                (int)QIXIS_READ(scver), qixis_read_tag(buf),
 345                (int)qixis_read_minor());
 346         /* the timestamp string contains "\n" at the end */
 347         printf(" on %s", qixis_read_time(buf));
 348
 349         puts("SERDES1 Reference : ");
 350         sw = QIXIS_READ(brdcfg[2]);
 351         clock = sw >> 4;
 352         printf("Clock1 = %sMHz ", freq[clock]);
 353         clock = sw & 0x0f;
 354         printf("Clock2 = %sMHz", freq[clock]);
 355
 356         sw = QIXIS_READ(brdcfg[3]);
 357         puts("\nSERDES2 Reference : ");
 358         clock = sw >> 4;
 359         printf("Clock1 = %sMHz ", freq[clock]);
 360         clock = sw & 0x0f;
 361         printf("Clock2 = %sMHz", freq[clock]);
 362
 363         sw = QIXIS_READ(brdcfg[12]);
 364         puts("\nSERDES3 Reference : ");
 365         clock = sw >> 4;
 366         printf("Clock1 = %sMHz Clock2 = %sMHz\n", freq[clock], freq[clock]);
 367 #else
 368         printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
 369
 370         puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\n");
 371         puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
 372         puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
 373 #endif
 374         return 0;
 375 }
 376
 377 #ifdef CONFIG_TARGET_LX2160AQDS
 378 /*
 379  * implementation of CONFIG_ESDHC_DETECT_QUIRK Macro.
 380  */
 381 u8 qixis_esdhc_detect_quirk(void)
 382 {
 383         /*
 384          * SDHC1 Card ID:
 385          * Specifies the type of card installed in the SDHC1 adapter slot.
 386          * 000= (reserved)
 387          * 001= eMMC V4.5 adapter is installed.
 388          * 010= SD/MMC 3.3V adapter is installed.
 389          * 011= eMMC V4.4 adapter is installed.
 390          * 100= eMMC V5.0 adapter is installed.
 391          * 101= MMC card/Legacy (3.3V) adapter is installed.
 392          * 110= SDCard V2/V3 adapter installed.
 393          * 111= no adapter is installed.
 394          */
 395         return ((QIXIS_READ(sdhc1) & QIXIS_SDID_MASK) !=
 396                  QIXIS_ESDHC_NO_ADAPTER);
 397 }
 398
 399 static void esdhc_adapter_card_ident(void)
 400 {
 401         u8 card_id, val;
 402
 403         val = QIXIS_READ(sdhc1);
 404         card_id = val & QIXIS_SDID_MASK;
 405
 406         switch (card_id) {
 407         case QIXIS_ESDHC_ADAPTER_TYPE_SD:
 408                 /* Power cycle to card */
 409                 val &= ~QIXIS_SDHC1_S1V3;
 410                 QIXIS_WRITE(sdhc1, val);
 411                 mdelay(1);
 412                 val |= QIXIS_SDHC1_S1V3;
 413                 QIXIS_WRITE(sdhc1, val);
 414                 /* Route to SDHC1_VS */
 415                 val = QIXIS_READ(brdcfg[11]);
 416                 val |= QIXIS_SDHC1_VS;
 417                 QIXIS_WRITE(brdcfg[11], val);
 418                 break;
 419         default:
 420                 break;
 421         }
 422 }
 423
 424 int config_board_mux(void)
 425 {
 426         u8 reg11, reg5, reg13;
 427         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 428         u32 sdhc1_base_pmux;
 429         u32 sdhc2_base_pmux;
 430         u32 iic5_pmux;
 431
 432         /* Routes {I2C2_SCL, I2C2_SDA} to SDHC1 as {SDHC1_CD_B, SDHC1_WP}.
 433          * Routes {I2C3_SCL, I2C3_SDA} to CAN transceiver as {CAN1_TX,CAN1_RX}.
 434          * Routes {I2C4_SCL, I2C4_SDA} to CAN transceiver as {CAN2_TX,CAN2_RX}.
 435          * Qixis and remote systems are isolated from the I2C1 bus.
 436          * Processor connections are still available.
 437          * SPI2 CS2_B controls EN25S64 SPI memory device.
 438          * SPI3 CS2_B controls EN25S64 SPI memory device.
 439          * EC2 connects to PHY #2 using RGMII protocol.
 440          * CLK_OUT connects to FPGA for clock measurement.
 441          */
 442
 443         reg5 = QIXIS_READ(brdcfg[5]);
 444         reg5 = CFG_MUX_I2C_SDHC(reg5, 0x40);
 445         QIXIS_WRITE(brdcfg[5], reg5);
 446
 447         /* Check RCW field sdhc1_base_pmux
 448          * esdhc0 : sdhc1_base_pmux = 0
 449          * dspi0  : sdhc1_base_pmux = 2
 450          */
 451         sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
 452                 & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;
 453         sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;
 454
 455         if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {
 456                 reg11 = QIXIS_READ(brdcfg[11]);
 457                 reg11 = SET_CFG_MUX1_SDHC1_DSPI(reg11, 0x40);
 458                 QIXIS_WRITE(brdcfg[11], reg11);
 459         } else {
 460                 /* - Routes {SDHC1_CMD, SDHC1_CLK } to SDHC1 adapter slot.
 461                  *          {SDHC1_DAT3, SDHC1_DAT2} to SDHC1 adapter slot.
 462                  *          {SDHC1_DAT1, SDHC1_DAT0} to SDHC1 adapter slot.
 463                  */
 464                 reg11 = QIXIS_READ(brdcfg[11]);
 465                 reg11 = SET_CFG_MUX1_SDHC1_SDHC(reg11);
 466                 QIXIS_WRITE(brdcfg[11], reg11);
 467         }
 468
 469         /* Check RCW field sdhc2_base_pmux
 470          * esdhc1 : sdhc2_base_pmux = 0 (default)
 471          * dspi1  : sdhc2_base_pmux = 2
 472          */
 473         sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])
 474                 & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;
 475         sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;
 476
 477         if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {
 478                 reg13 = QIXIS_READ(brdcfg[13]);
 479                 reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x01);
 480                 QIXIS_WRITE(brdcfg[13], reg13);
 481         } else {
 482                 reg13 = QIXIS_READ(brdcfg[13]);
 483                 reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x00);
 484                 QIXIS_WRITE(brdcfg[13], reg13);
 485         }
 486
 487         /* Check RCW field IIC5 to enable dspi2 DT nodei
 488          * dspi2: IIC5 = 3
 489          */
 490         iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
 491                 & FSL_CHASSIS3_IIC5_PMUX_MASK;
 492         iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
 493
 494         if (iic5_pmux == IIC5_PMUX_SPI3) {
 495                 /* - Routes {SDHC1_DAT4} to SPI3 devices as {SPI3_M_CS0_B}. */
 496                 reg11 = QIXIS_READ(brdcfg[11]);
 497                 reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x10);
 498                 QIXIS_WRITE(brdcfg[11], reg11);
 499
 500                 /* - Routes {SDHC1_DAT5, SDHC1_DAT6} nowhere.
 501                  * {SDHC1_DAT7, SDHC1_DS } to {nothing, SPI3_M0_CLK }.
 502                  * {I2C5_SCL, I2C5_SDA } to {SPI3_M0_MOSI, SPI3_M0_MISO}.
 503                  */
 504                 reg11 = QIXIS_READ(brdcfg[11]);
 505                 reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x01);
 506                 QIXIS_WRITE(brdcfg[11], reg11);
 507         } else {
 508                 /*
 509                  * If {SDHC1_DAT4} has been configured to route to SDHC1_VS,
 510                  * do not change it.
 511                  * Otherwise route {SDHC1_DAT4} to SDHC1 adapter slot.
 512                  */
 513                 reg11 = QIXIS_READ(brdcfg[11]);
 514                 if ((reg11 & 0x30) != 0x30) {
 515                         reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x00);
 516                         QIXIS_WRITE(brdcfg[11], reg11);
 517                 }
 518
 519                 /* - Routes {SDHC1_DAT5, SDHC1_DAT6} to SDHC1 adapter slot.
 520                  * {SDHC1_DAT7, SDHC1_DS } to SDHC1 adapter slot.
 521                  * {I2C5_SCL, I2C5_SDA } to SDHC1 adapter slot.
 522                  */
 523                 reg11 = QIXIS_READ(brdcfg[11]);
 524                 reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x00);
 525                 QIXIS_WRITE(brdcfg[11], reg11);
 526         }
 527
 528         return 0;
 529 }
 530
 531 int board_early_init_r(void)
 532 {
 533         esdhc_adapter_card_ident();
 534         return 0;
 535 }
 536 #elif defined(CONFIG_TARGET_LX2160ARDB)
 537 int config_board_mux(void)
 538 {
 539         u8 brdcfg;
 540
 541         brdcfg = QIXIS_READ(brdcfg[4]);
 542         /* The BRDCFG4 register controls general board configuration.
 543          *|-------------------------------------------|
 544          *|Field  | Function                          |
 545          *|-------------------------------------------|
 546          *|5      | CAN I/O Enable (net CFG_CAN_EN_B):|
 547          *|CAN_EN | 0= CAN transceivers are disabled. |
 548          *|       | 1= CAN transceivers are enabled.  |
 549          *|-------------------------------------------|
 550          */
 551         brdcfg |= BIT_MASK(5);
 552         QIXIS_WRITE(brdcfg[4], brdcfg);
 553
 554         return 0;
 555 }
 556 #else
 557 int config_board_mux(void)
 558 {
 559         return 0;
 560 }
 561 #endif
 562
 563 unsigned long get_board_sys_clk(void)
 564 {
 565 #ifdef CONFIG_TARGET_LX2160AQDS
 566         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 567
 568         switch (sysclk_conf & 0x03) {
 569         case QIXIS_SYSCLK_100:
 570                 return 100000000;
 571         case QIXIS_SYSCLK_125:
 572                 return 125000000;
 573         case QIXIS_SYSCLK_133:
 574                 return 133333333;
 575         }
 576         return 100000000;
 577 #else
 578         return 100000000;
 579 #endif
 580 }
 581
 582 unsigned long get_board_ddr_clk(void)
 583 {
 584 #ifdef CONFIG_TARGET_LX2160AQDS
 585         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 586
 587         switch ((ddrclk_conf & 0x30) >> 4) {
 588         case QIXIS_DDRCLK_100:
 589                 return 100000000;
 590         case QIXIS_DDRCLK_125:
 591                 return 125000000;
 592         case QIXIS_DDRCLK_133:
 593                 return 133333333;
 594         }
 595         return 100000000;
 596 #else
 597         return 100000000;
 598 #endif
 599 }
 600
 601 int board_init(void)
 602 {
 603 #if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
 604         u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
 605 #endif
 606 #ifdef CONFIG_ENV_IS_NOWHERE
 607         gd->env_addr = (ulong)&default_environment[0];
 608 #endif
 609
 610         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 611
 612 #if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
 613         /* invert AQR107 IRQ pins polarity */
 614         out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR107_IRQ_MASK);
 615 #endif
 616
 617 #ifdef CONFIG_FSL_CAAM
 618         sec_init();
 619 #endif
 620
 621 #if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
 622         pci_init();
 623 #endif
 624         return 0;
 625 }
 626
 627 void detail_board_ddr_info(void)
 628 {
 629         int i;
 630         u64 ddr_size = 0;
 631
 632         puts("\nDDR    ");
 633         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 634                 ddr_size += gd->bd->bi_dram[i].size;
 635         print_size(ddr_size, "");
 636         print_ddr_info(0);
 637 }
 638
 639 #ifdef CONFIG_MISC_INIT_R
 640 int misc_init_r(void)
 641 {
 642         config_board_mux();
 643
 644         return 0;
 645 }
 646 #endif
 647
 648 #ifdef CONFIG_FSL_MC_ENET
 649 extern int fdt_fixup_board_phy(void *fdt);
 650
 651 void fdt_fixup_board_enet(void *fdt)
 652 {
 653         int offset;
 654
 655         offset = fdt_path_offset(fdt, "/soc/fsl-mc");
 656
 657         if (offset < 0)
 658                 offset = fdt_path_offset(fdt, "/fsl-mc");
 659
 660         if (offset < 0) {
 661                 printf("%s: fsl-mc node not found in device tree (error %d)\n",
 662                        __func__, offset);
 663                 return;
 664         }
 665
 666         if (get_mc_boot_status() == 0 &&
 667             (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) {
 668                 fdt_status_okay(fdt, offset);
 669 #ifndef CONFIG_DM_ETH
 670                 fdt_fixup_board_phy(fdt);
 671 #endif
 672         } else {
 673                 fdt_status_fail(fdt, offset);
 674         }
 675 }
 676
 677 void board_quiesce_devices(void)
 678 {
 679         fsl_mc_ldpaa_exit(gd->bd);
 680 }
 681 #endif
 682
 683 #ifdef CONFIG_OF_BOARD_SETUP
 684 int ft_board_setup(void *blob, struct bd_info *bd)
 685 {
 686         int i;
 687         u16 mc_memory_bank = 0;
 688
 689         u64 *base;
 690         u64 *size;
 691         u64 mc_memory_base = 0;
 692         u64 mc_memory_size = 0;
 693         u16 total_memory_banks;
 694
 695         ft_cpu_setup(blob, bd);
 696
 697         fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
 698
 699         if (mc_memory_base != 0)
 700                 mc_memory_bank++;
 701
 702         total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
 703
 704         base = calloc(total_memory_banks, sizeof(u64));
 705         size = calloc(total_memory_banks, sizeof(u64));
 706
 707         /* fixup DT for the three GPP DDR banks */
 708         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 709                 base[i] = gd->bd->bi_dram[i].start;
 710                 size[i] = gd->bd->bi_dram[i].size;
 711         }
 712
 713 #ifdef CONFIG_RESV_RAM
 714         /* reduce size if reserved memory is within this bank */
 715         if (gd->arch.resv_ram >= base[0] &&
 716             gd->arch.resv_ram < base[0] + size[0])
 717                 size[0] = gd->arch.resv_ram - base[0];
 718         else if (gd->arch.resv_ram >= base[1] &&
 719                  gd->arch.resv_ram < base[1] + size[1])
 720                 size[1] = gd->arch.resv_ram - base[1];
 721         else if (gd->arch.resv_ram >= base[2] &&
 722                  gd->arch.resv_ram < base[2] + size[2])
 723                 size[2] = gd->arch.resv_ram - base[2];
 724 #endif
 725
 726         if (mc_memory_base != 0) {
 727                 for (i = 0; i <= total_memory_banks; i++) {
 728                         if (base[i] == 0 && size[i] == 0) {
 729                                 base[i] = mc_memory_base;
 730                                 size[i] = mc_memory_size;
 731                                 break;
 732                         }
 733                 }
 734         }
 735
 736         fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
 737
 738 #ifdef CONFIG_USB
 739         fsl_fdt_fixup_dr_usb(blob, bd);
 740 #endif
 741
 742 #ifdef CONFIG_FSL_MC_ENET
 743         fdt_fsl_mc_fixup_iommu_map_entry(blob);
 744         fdt_fixup_board_enet(blob);
 745 #endif
 746         fdt_fixup_icid(blob);
 747
 748         return 0;
 749 }
 750 #endif
 751
 752 void qixis_dump_switch(void)
 753 {
 754         int i, nr_of_cfgsw;
 755
 756         QIXIS_WRITE(cms[0], 0x00);
 757         nr_of_cfgsw = QIXIS_READ(cms[1]);
 758
 759         puts("DIP switch settings dump:\n");
 760         for (i = 1; i <= nr_of_cfgsw; i++) {
 761                 QIXIS_WRITE(cms[0], i);
 762                 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
 763         }
 764 }