drivers/video/s3c-fb.c

   1 /*
   2  * S3C24x0 LCD driver
   3  *
   4  * NOTE: Only 16/24 bpp operation with TFT LCD is supported.
   5  *
   6  * Copyright (C) 2014 Marek Vasut <[email protected]>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10 #include <common.h>
  11 #include <malloc.h>
  12 #include <video_fb.h>
  13
  14 #include <asm/errno.h>
  15 #include <asm/io.h>
  16 #include <asm/arch/s3c24x0_cpu.h>
  17
  18 #include "videomodes.h"
  19
  20 static GraphicDevice panel;
  21
  22 /* S3C requires the FB to be 4MiB aligned. */
  23 #define S3CFB_ALIGN                     (4 << 20)
  24
  25 #define S3CFB_LCDCON1_CLKVAL(x)         ((x) << 8)
  26 #define S3CFB_LCDCON1_PNRMODE_TFT       (0x3 << 5)
  27 #define S3CFB_LCDCON1_BPPMODE_TFT_16BPP (0xc << 1)
  28 #define S3CFB_LCDCON1_BPPMODE_TFT_24BPP (0xd << 1)
  29
  30 #define S3CFB_LCDCON2_VBPD(x)           ((x) << 24)
  31 #define S3CFB_LCDCON2_LINEVAL(x)        ((x) << 14)
  32 #define S3CFB_LCDCON2_VFPD(x)           ((x) << 6)
  33 #define S3CFB_LCDCON2_VSPW(x)           ((x) << 0)
  34
  35 #define S3CFB_LCDCON3_HBPD(x)           ((x) << 19)
  36 #define S3CFB_LCDCON3_HOZVAL(x)         ((x) << 8)
  37 #define S3CFB_LCDCON3_HFPD(x)           ((x) << 0)
  38
  39 #define S3CFB_LCDCON4_HSPW(x)           ((x) << 0)
  40
  41 #define S3CFB_LCDCON5_BPP24BL           (1 << 12)
  42 #define S3CFB_LCDCON5_FRM565            (1 << 11)
  43 #define S3CFB_LCDCON5_HWSWP             (1 << 0)
  44
  45 #define PS2KHZ(ps)                      (1000000000UL / (ps))
  46
  47 /*
  48  * Example:
  49  * setenv videomode video=ctfb:x:800,y:480,depth:16,mode:0,\
  50  *            pclk:30066,le:41,ri:89,up:45,lo:12,
  51  *            hs:1,vs:1,sync:100663296,vmode:0
  52  */
  53 static void s3c_lcd_init(GraphicDevice *panel,
  54                         struct ctfb_res_modes *mode, int bpp)
  55 {
  56         uint32_t clk_divider;
  57         struct s3c24x0_lcd *regs = s3c24x0_get_base_lcd();
  58
  59         /* Stop the controller. */
  60         clrbits_le32(&regs->lcdcon1, 1);
  61
  62         /* Calculate clock divider. */
  63         clk_divider = (get_HCLK() / PS2KHZ(mode->pixclock)) / 1000;
  64         clk_divider = DIV_ROUND_UP(clk_divider, 2);
  65         if (clk_divider)
  66                 clk_divider -= 1;
  67
  68         /* Program LCD configuration. */
  69         switch (bpp) {
  70         case 16:
  71                 writel(S3CFB_LCDCON1_BPPMODE_TFT_16BPP |
  72                        S3CFB_LCDCON1_PNRMODE_TFT |
  73                        S3CFB_LCDCON1_CLKVAL(clk_divider),
  74                        &regs->lcdcon1);
  75                 writel(S3CFB_LCDCON5_HWSWP | S3CFB_LCDCON5_FRM565,
  76                        &regs->lcdcon5);
  77                 break;
  78         case 24:
  79                 writel(S3CFB_LCDCON1_BPPMODE_TFT_24BPP |
  80                        S3CFB_LCDCON1_PNRMODE_TFT |
  81                        S3CFB_LCDCON1_CLKVAL(clk_divider),
  82                        &regs->lcdcon1);
  83                 writel(S3CFB_LCDCON5_BPP24BL, &regs->lcdcon5);
  84                 break;
  85         }
  86
  87         writel(S3CFB_LCDCON2_LINEVAL(mode->yres - 1) |
  88                S3CFB_LCDCON2_VBPD(mode->upper_margin - 1) |
  89                S3CFB_LCDCON2_VFPD(mode->lower_margin - 1) |
  90                S3CFB_LCDCON2_VSPW(mode->vsync_len - 1),
  91                &regs->lcdcon2);
  92
  93         writel(S3CFB_LCDCON3_HBPD(mode->right_margin - 1) |
  94                S3CFB_LCDCON3_HFPD(mode->left_margin - 1) |
  95                S3CFB_LCDCON3_HOZVAL(mode->xres - 1),
  96                &regs->lcdcon3);
  97
  98         writel(S3CFB_LCDCON4_HSPW(mode->hsync_len - 1),
  99                &regs->lcdcon4);
 100
 101         /* Write FB address. */
 102         writel(panel->frameAdrs >> 1, &regs->lcdsaddr1);
 103         writel((panel->frameAdrs +
 104                (mode->xres * mode->yres * panel->gdfBytesPP)) >> 1,
 105                &regs->lcdsaddr2);
 106         writel(mode->xres * bpp / 16, &regs->lcdsaddr3);
 107
 108         /* Start the controller. */
 109         setbits_le32(&regs->lcdcon1, 1);
 110 }
 111
 112 void *video_hw_init(void)
 113 {
 114         int bpp = -1;
 115         char *penv;
 116         void *fb;
 117         struct ctfb_res_modes mode;
 118
 119         puts("Video: ");
 120
 121         /* Suck display configuration from "videomode" variable */
 122         penv = getenv("videomode");
 123         if (!penv) {
 124                 puts("S3CFB: 'videomode' variable not set!\n");
 125                 return NULL;
 126         }
 127
 128         bpp = video_get_params(&mode, penv);
 129
 130         /* fill in Graphic device struct */
 131         sprintf(panel.modeIdent, "%dx%dx%d", mode.xres, mode.yres, bpp);
 132
 133         panel.winSizeX = mode.xres;
 134         panel.winSizeY = mode.yres;
 135         panel.plnSizeX = mode.xres;
 136         panel.plnSizeY = mode.yres;
 137
 138         switch (bpp) {
 139         case 24:
 140                 panel.gdfBytesPP = 4;
 141                 panel.gdfIndex = GDF_32BIT_X888RGB;
 142                 break;
 143         case 16:
 144                 panel.gdfBytesPP = 2;
 145                 panel.gdfIndex = GDF_16BIT_565RGB;
 146                 break;
 147         default:
 148                 printf("S3CFB: Invalid BPP specified! (bpp = %i)\n", bpp);
 149                 return NULL;
 150         }
 151
 152         panel.memSize = mode.xres * mode.yres * panel.gdfBytesPP;
 153
 154         /* Allocate framebuffer */
 155         fb = memalign(S3CFB_ALIGN, roundup(panel.memSize, S3CFB_ALIGN));
 156         if (!fb) {
 157                 printf("S3CFB: Error allocating framebuffer!\n");
 158                 return NULL;
 159         }
 160
 161         /* Wipe framebuffer */
 162         memset(fb, 0, panel.memSize);
 163
 164         panel.frameAdrs = (u32)fb;
 165
 166         printf("%s\n", panel.modeIdent);
 167
 168         /* Start framebuffer */
 169         s3c_lcd_init(&panel, &mode, bpp);
 170
 171         return (void *)&panel;
 172 }