board/ti/dra7xx/evm.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2013
   4  * Texas Instruments Incorporated, <www.ti.com>
   5  *
   6  * Lokesh Vutla <[email protected]>
   7  *
   8  * Based on previous work by:
   9  * Aneesh V       <[email protected]>
  10  * Steve Sakoman  <[email protected]>
  11  */
  12 #include <common.h>
  13 #include <env.h>
  14 #include <palmas.h>
  15 #include <sata.h>
  16 #include <linux/string.h>
  17 #include <asm/gpio.h>
  18 #include <usb.h>
  19 #include <linux/usb/gadget.h>
  20 #include <asm/omap_common.h>
  21 #include <asm/omap_sec_common.h>
  22 #include <asm/arch/gpio.h>
  23 #include <asm/arch/dra7xx_iodelay.h>
  24 #include <asm/emif.h>
  25 #include <asm/arch/sys_proto.h>
  26 #include <asm/arch/mmc_host_def.h>
  27 #include <asm/arch/sata.h>
  28 #include <dwc3-uboot.h>
  29 #include <dwc3-omap-uboot.h>
  30 #include <i2c.h>
  31 #include <ti-usb-phy-uboot.h>
  32 #include <miiphy.h>
  33
  34 #include "mux_data.h"
  35 #include "../common/board_detect.h"
  36
  37 #define board_is_dra76x_evm()           board_ti_is("DRA76/7x")
  38 #define board_is_dra74x_evm()           board_ti_is("5777xCPU")
  39 #define board_is_dra72x_evm()           board_ti_is("DRA72x-T")
  40 #define board_is_dra71x_evm()           board_ti_is("DRA79x,D")
  41 #define board_is_dra74x_revh_or_later() (board_is_dra74x_evm() &&       \
  42                                 (strncmp("H", board_ti_get_rev(), 1) <= 0))
  43 #define board_is_dra72x_revc_or_later() (board_is_dra72x_evm() &&       \
  44                                 (strncmp("C", board_ti_get_rev(), 1) <= 0))
  45 #define board_ti_get_emif_size()        board_ti_get_emif1_size() +     \
  46                                         board_ti_get_emif2_size()
  47
  48 #ifdef CONFIG_DRIVER_TI_CPSW
  49 #include <cpsw.h>
  50 #endif
  51
  52 DECLARE_GLOBAL_DATA_PTR;
  53
  54 /* GPIO 7_11 */
  55 #define GPIO_DDR_VTT_EN 203
  56
  57 #define SYSINFO_BOARD_NAME_MAX_LEN      37
  58
  59 /* I2C I/O Expander */
  60 #define NAND_PCF8575_ADDR       0x21
  61 #define NAND_PCF8575_I2C_BUS_NUM        0
  62
  63 const struct omap_sysinfo sysinfo = {
  64         "Board: UNKNOWN(DRA7 EVM) REV UNKNOWN\n"
  65 };
  66
  67 static const struct emif_regs emif1_ddr3_532_mhz_1cs = {
  68         .sdram_config_init              = 0x61851ab2,
  69         .sdram_config                   = 0x61851ab2,
  70         .sdram_config2                  = 0x08000000,
  71         .ref_ctrl                       = 0x000040F1,
  72         .ref_ctrl_final                 = 0x00001035,
  73         .sdram_tim1                     = 0xCCCF36B3,
  74         .sdram_tim2                     = 0x308F7FDA,
  75         .sdram_tim3                     = 0x427F88A8,
  76         .read_idle_ctrl                 = 0x00050000,
  77         .zq_config                      = 0x0007190B,
  78         .temp_alert_config              = 0x00000000,
  79         .emif_ddr_phy_ctlr_1_init       = 0x0024400B,
  80         .emif_ddr_phy_ctlr_1            = 0x0E24400B,
  81         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
  82         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
  83         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
  84         .emif_ddr_ext_phy_ctrl_4        = 0x009B009B,
  85         .emif_ddr_ext_phy_ctrl_5        = 0x009E009E,
  86         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
  87         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
  88         .emif_rd_wr_lvl_ctl             = 0x00000000,
  89         .emif_rd_wr_exec_thresh         = 0x00000305
  90 };
  91
  92 static const struct emif_regs emif2_ddr3_532_mhz_1cs = {
  93         .sdram_config_init              = 0x61851B32,
  94         .sdram_config                   = 0x61851B32,
  95         .sdram_config2                  = 0x08000000,
  96         .ref_ctrl                       = 0x000040F1,
  97         .ref_ctrl_final                 = 0x00001035,
  98         .sdram_tim1                     = 0xCCCF36B3,
  99         .sdram_tim2                     = 0x308F7FDA,
 100         .sdram_tim3                     = 0x427F88A8,
 101         .read_idle_ctrl                 = 0x00050000,
 102         .zq_config                      = 0x0007190B,
 103         .temp_alert_config              = 0x00000000,
 104         .emif_ddr_phy_ctlr_1_init       = 0x0024400B,
 105         .emif_ddr_phy_ctlr_1            = 0x0E24400B,
 106         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 107         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 108         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 109         .emif_ddr_ext_phy_ctrl_4        = 0x009B009B,
 110         .emif_ddr_ext_phy_ctrl_5        = 0x009E009E,
 111         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 112         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 113         .emif_rd_wr_lvl_ctl             = 0x00000000,
 114         .emif_rd_wr_exec_thresh         = 0x00000305
 115 };
 116
 117 static const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
 118         .sdram_config_init              = 0x61862B32,
 119         .sdram_config                   = 0x61862B32,
 120         .sdram_config2                  = 0x08000000,
 121         .ref_ctrl                       = 0x0000514C,
 122         .ref_ctrl_final                 = 0x0000144A,
 123         .sdram_tim1                     = 0xD113781C,
 124         .sdram_tim2                     = 0x30717FE3,
 125         .sdram_tim3                     = 0x409F86A8,
 126         .read_idle_ctrl                 = 0x00050000,
 127         .zq_config                      = 0x5007190B,
 128         .temp_alert_config              = 0x00000000,
 129         .emif_ddr_phy_ctlr_1_init       = 0x0024400D,
 130         .emif_ddr_phy_ctlr_1            = 0x0E24400D,
 131         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 132         .emif_ddr_ext_phy_ctrl_2        = 0x00A400A4,
 133         .emif_ddr_ext_phy_ctrl_3        = 0x00A900A9,
 134         .emif_ddr_ext_phy_ctrl_4        = 0x00B000B0,
 135         .emif_ddr_ext_phy_ctrl_5        = 0x00B000B0,
 136         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 137         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 138         .emif_rd_wr_lvl_ctl             = 0x00000000,
 139         .emif_rd_wr_exec_thresh         = 0x00000305
 140 };
 141
 142 const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es2 = {
 143         .sdram_config_init              = 0x61862BB2,
 144         .sdram_config                   = 0x61862BB2,
 145         .sdram_config2                  = 0x00000000,
 146         .ref_ctrl                       = 0x0000514D,
 147         .ref_ctrl_final                 = 0x0000144A,
 148         .sdram_tim1                     = 0xD1137824,
 149         .sdram_tim2                     = 0x30B37FE3,
 150         .sdram_tim3                     = 0x409F8AD8,
 151         .read_idle_ctrl                 = 0x00050000,
 152         .zq_config                      = 0x5007190B,
 153         .temp_alert_config              = 0x00000000,
 154         .emif_ddr_phy_ctlr_1_init       = 0x0824400E,
 155         .emif_ddr_phy_ctlr_1            = 0x0E24400E,
 156         .emif_ddr_ext_phy_ctrl_1        = 0x04040100,
 157         .emif_ddr_ext_phy_ctrl_2        = 0x006B009F,
 158         .emif_ddr_ext_phy_ctrl_3        = 0x006B00A2,
 159         .emif_ddr_ext_phy_ctrl_4        = 0x006B00A8,
 160         .emif_ddr_ext_phy_ctrl_5        = 0x006B00A8,
 161         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 162         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 163         .emif_rd_wr_lvl_ctl             = 0x00000000,
 164         .emif_rd_wr_exec_thresh         = 0x00000305
 165 };
 166
 167 const struct emif_regs emif1_ddr3_532_mhz_1cs_2G = {
 168         .sdram_config_init              = 0x61851ab2,
 169         .sdram_config                   = 0x61851ab2,
 170         .sdram_config2                  = 0x08000000,
 171         .ref_ctrl                       = 0x000040F1,
 172         .ref_ctrl_final                 = 0x00001035,
 173         .sdram_tim1                     = 0xCCCF36B3,
 174         .sdram_tim2                     = 0x30BF7FDA,
 175         .sdram_tim3                     = 0x427F8BA8,
 176         .read_idle_ctrl                 = 0x00050000,
 177         .zq_config                      = 0x0007190B,
 178         .temp_alert_config              = 0x00000000,
 179         .emif_ddr_phy_ctlr_1_init       = 0x0024400B,
 180         .emif_ddr_phy_ctlr_1            = 0x0E24400B,
 181         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 182         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 183         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 184         .emif_ddr_ext_phy_ctrl_4        = 0x009B009B,
 185         .emif_ddr_ext_phy_ctrl_5        = 0x009E009E,
 186         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 187         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 188         .emif_rd_wr_lvl_ctl             = 0x00000000,
 189         .emif_rd_wr_exec_thresh         = 0x00000305
 190 };
 191
 192 const struct emif_regs emif2_ddr3_532_mhz_1cs_2G = {
 193         .sdram_config_init              = 0x61851B32,
 194         .sdram_config                   = 0x61851B32,
 195         .sdram_config2                  = 0x08000000,
 196         .ref_ctrl                       = 0x000040F1,
 197         .ref_ctrl_final                 = 0x00001035,
 198         .sdram_tim1                     = 0xCCCF36B3,
 199         .sdram_tim2                     = 0x308F7FDA,
 200         .sdram_tim3                     = 0x427F88A8,
 201         .read_idle_ctrl                 = 0x00050000,
 202         .zq_config                      = 0x0007190B,
 203         .temp_alert_config              = 0x00000000,
 204         .emif_ddr_phy_ctlr_1_init       = 0x0024400B,
 205         .emif_ddr_phy_ctlr_1            = 0x0E24400B,
 206         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 207         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 208         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 209         .emif_ddr_ext_phy_ctrl_4        = 0x009B009B,
 210         .emif_ddr_ext_phy_ctrl_5        = 0x009E009E,
 211         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 212         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 213         .emif_rd_wr_lvl_ctl             = 0x00000000,
 214         .emif_rd_wr_exec_thresh         = 0x00000305
 215 };
 216
 217 const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra76 = {
 218         .sdram_config_init              = 0x61862B32,
 219         .sdram_config                   = 0x61862B32,
 220         .sdram_config2                  = 0x00000000,
 221         .ref_ctrl                       = 0x0000514C,
 222         .ref_ctrl_final                 = 0x0000144A,
 223         .sdram_tim1                     = 0xD113783C,
 224         .sdram_tim2                     = 0x30B47FE3,
 225         .sdram_tim3                     = 0x409F8AD8,
 226         .read_idle_ctrl                 = 0x00050000,
 227         .zq_config                      = 0x5007190B,
 228         .temp_alert_config              = 0x00000000,
 229         .emif_ddr_phy_ctlr_1_init       = 0x0824400D,
 230         .emif_ddr_phy_ctlr_1            = 0x0E24400D,
 231         .emif_ddr_ext_phy_ctrl_1        = 0x04040100,
 232         .emif_ddr_ext_phy_ctrl_2        = 0x006B009F,
 233         .emif_ddr_ext_phy_ctrl_3        = 0x006B00A2,
 234         .emif_ddr_ext_phy_ctrl_4        = 0x006B00A8,
 235         .emif_ddr_ext_phy_ctrl_5        = 0x006B00A8,
 236         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 237         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 238         .emif_rd_wr_lvl_ctl             = 0x00000000,
 239         .emif_rd_wr_exec_thresh         = 0x00000305
 240 };
 241
 242 const struct emif_regs emif_2_regs_ddr3_666_mhz_1cs_dra76 = {
 243         .sdram_config_init              = 0x61862B32,
 244         .sdram_config                   = 0x61862B32,
 245         .sdram_config2                  = 0x00000000,
 246         .ref_ctrl                       = 0x0000514C,
 247         .ref_ctrl_final                 = 0x0000144A,
 248         .sdram_tim1                     = 0xD113781C,
 249         .sdram_tim2                     = 0x30B47FE3,
 250         .sdram_tim3                     = 0x409F8AD8,
 251         .read_idle_ctrl                 = 0x00050000,
 252         .zq_config                      = 0x5007190B,
 253         .temp_alert_config              = 0x00000000,
 254         .emif_ddr_phy_ctlr_1_init       = 0x0824400D,
 255         .emif_ddr_phy_ctlr_1            = 0x0E24400D,
 256         .emif_ddr_ext_phy_ctrl_1        = 0x04040100,
 257         .emif_ddr_ext_phy_ctrl_2        = 0x006B009F,
 258         .emif_ddr_ext_phy_ctrl_3        = 0x006B00A2,
 259         .emif_ddr_ext_phy_ctrl_4        = 0x006B00A8,
 260         .emif_ddr_ext_phy_ctrl_5        = 0x006B00A8,
 261         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 262         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 263         .emif_rd_wr_lvl_ctl             = 0x00000000,
 264         .emif_rd_wr_exec_thresh         = 0x00000305
 265 };
 266
 267 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 268 {
 269         u64 ram_size;
 270
 271         ram_size = board_ti_get_emif_size();
 272
 273         switch (omap_revision()) {
 274         case DRA752_ES1_0:
 275         case DRA752_ES1_1:
 276         case DRA752_ES2_0:
 277                 switch (emif_nr) {
 278                 case 1:
 279                         if (ram_size > CONFIG_MAX_MEM_MAPPED)
 280                                 *regs = &emif1_ddr3_532_mhz_1cs_2G;
 281                         else
 282                                 *regs = &emif1_ddr3_532_mhz_1cs;
 283                         break;
 284                 case 2:
 285                         if (ram_size > CONFIG_MAX_MEM_MAPPED)
 286                                 *regs = &emif2_ddr3_532_mhz_1cs_2G;
 287                         else
 288                                 *regs = &emif2_ddr3_532_mhz_1cs;
 289                         break;
 290                 }
 291                 break;
 292         case DRA762_ABZ_ES1_0:
 293         case DRA762_ACD_ES1_0:
 294         case DRA762_ES1_0:
 295                 if (emif_nr == 1)
 296                         *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra76;
 297                 else
 298                         *regs = &emif_2_regs_ddr3_666_mhz_1cs_dra76;
 299                 break;
 300         case DRA722_ES1_0:
 301         case DRA722_ES2_0:
 302         case DRA722_ES2_1:
 303                 if (ram_size < CONFIG_MAX_MEM_MAPPED)
 304                         *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1;
 305                 else
 306                         *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es2;
 307                 break;
 308         default:
 309                 *regs = &emif1_ddr3_532_mhz_1cs;
 310         }
 311 }
 312
 313 static const struct dmm_lisa_map_regs lisa_map_dra7_1536MB = {
 314         .dmm_lisa_map_0 = 0x0,
 315         .dmm_lisa_map_1 = 0x80640300,
 316         .dmm_lisa_map_2 = 0xC0500220,
 317         .dmm_lisa_map_3 = 0xFF020100,
 318         .is_ma_present  = 0x1
 319 };
 320
 321 static const struct dmm_lisa_map_regs lisa_map_2G_x_2 = {
 322         .dmm_lisa_map_0 = 0x0,
 323         .dmm_lisa_map_1 = 0x0,
 324         .dmm_lisa_map_2 = 0x80600100,
 325         .dmm_lisa_map_3 = 0xFF020100,
 326         .is_ma_present  = 0x1
 327 };
 328
 329 const struct dmm_lisa_map_regs lisa_map_dra7_2GB = {
 330         .dmm_lisa_map_0 = 0x0,
 331         .dmm_lisa_map_1 = 0x0,
 332         .dmm_lisa_map_2 = 0x80740300,
 333         .dmm_lisa_map_3 = 0xFF020100,
 334         .is_ma_present  = 0x1
 335 };
 336
 337 /*
 338  * DRA722 EVM EMIF1 2GB CONFIGURATION
 339  * EMIF1 4 devices of 512Mb x 8 Micron
 340  */
 341 const struct dmm_lisa_map_regs lisa_map_2G_x_4 = {
 342         .dmm_lisa_map_0 = 0x0,
 343         .dmm_lisa_map_1 = 0x0,
 344         .dmm_lisa_map_2 = 0x80700100,
 345         .dmm_lisa_map_3 = 0xFF020100,
 346         .is_ma_present  = 0x1
 347 };
 348
 349 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 350 {
 351         u64 ram_size;
 352
 353         ram_size = board_ti_get_emif_size();
 354
 355         switch (omap_revision()) {
 356         case DRA762_ABZ_ES1_0:
 357         case DRA762_ACD_ES1_0:
 358         case DRA762_ES1_0:
 359         case DRA752_ES1_0:
 360         case DRA752_ES1_1:
 361         case DRA752_ES2_0:
 362                 if (ram_size > CONFIG_MAX_MEM_MAPPED)
 363                         *dmm_lisa_regs = &lisa_map_dra7_2GB;
 364                 else
 365                         *dmm_lisa_regs = &lisa_map_dra7_1536MB;
 366                 break;
 367         case DRA722_ES1_0:
 368         case DRA722_ES2_0:
 369         case DRA722_ES2_1:
 370         default:
 371                 if (ram_size < CONFIG_MAX_MEM_MAPPED)
 372                         *dmm_lisa_regs = &lisa_map_2G_x_2;
 373                 else
 374                         *dmm_lisa_regs = &lisa_map_2G_x_4;
 375                 break;
 376         }
 377 }
 378
 379 struct vcores_data dra752_volts = {
 380         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 381         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 382         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 383         .mpu.addr       = TPS659038_REG_ADDR_SMPS12,
 384         .mpu.pmic       = &tps659038,
 385         .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
 386
 387         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 388         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 389         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 390         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 391         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 392         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 393         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 394         .eve.addr       = TPS659038_REG_ADDR_SMPS45,
 395         .eve.pmic       = &tps659038,
 396         .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
 397
 398         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 399         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 400         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 401         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 402         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 403         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 404         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 405         .gpu.addr       = TPS659038_REG_ADDR_SMPS6,
 406         .gpu.pmic       = &tps659038,
 407         .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
 408
 409         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 410         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 411         .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 412         .core.addr      = TPS659038_REG_ADDR_SMPS7,
 413         .core.pmic      = &tps659038,
 414
 415         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 416         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 417         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 418         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 419         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 420         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 421         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 422         .iva.addr       = TPS659038_REG_ADDR_SMPS8,
 423         .iva.pmic       = &tps659038,
 424         .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
 425 };
 426
 427 struct vcores_data dra76x_volts = {
 428         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 429         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 430         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 431         .mpu.addr       = LP87565_REG_ADDR_BUCK01,
 432         .mpu.pmic       = &lp87565,
 433         .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
 434
 435         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 436         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 437         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 438         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 439         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 440         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 441         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 442         .eve.addr       = TPS65917_REG_ADDR_SMPS1,
 443         .eve.pmic       = &tps659038,
 444         .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
 445
 446         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 447         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 448         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 449         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 450         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 451         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 452         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 453         .gpu.addr       = LP87565_REG_ADDR_BUCK23,
 454         .gpu.pmic       = &lp87565,
 455         .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
 456
 457         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 458         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 459         .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 460         .core.addr      = TPS65917_REG_ADDR_SMPS3,
 461         .core.pmic      = &tps659038,
 462
 463         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 464         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 465         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 466         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 467         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 468         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 469         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 470         .iva.addr       = TPS65917_REG_ADDR_SMPS4,
 471         .iva.pmic       = &tps659038,
 472         .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
 473 };
 474
 475 struct vcores_data dra722_volts = {
 476         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 477         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 478         .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 479         .mpu.addr       = TPS65917_REG_ADDR_SMPS1,
 480         .mpu.pmic       = &tps659038,
 481         .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
 482
 483         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 484         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 485         .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 486         .core.addr      = TPS65917_REG_ADDR_SMPS2,
 487         .core.pmic      = &tps659038,
 488
 489         /*
 490          * The DSPEVE, GPU and IVA rails are usually grouped on DRA72x
 491          * designs and powered by TPS65917 SMPS3, as on the J6Eco EVM.
 492          */
 493         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 494         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 495         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 496         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 497         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 498         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 499         .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 500         .gpu.addr       = TPS65917_REG_ADDR_SMPS3,
 501         .gpu.pmic       = &tps659038,
 502         .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
 503
 504         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 505         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 506         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 507         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 508         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 509         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 510         .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 511         .eve.addr       = TPS65917_REG_ADDR_SMPS3,
 512         .eve.pmic       = &tps659038,
 513         .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
 514
 515         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 516         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 517         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 518         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 519         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 520         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 521         .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 522         .iva.addr       = TPS65917_REG_ADDR_SMPS3,
 523         .iva.pmic       = &tps659038,
 524         .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
 525 };
 526
 527 struct vcores_data dra718_volts = {
 528         /*
 529          * In the case of dra71x GPU MPU and CORE
 530          * are all powered up by BUCK0 of LP873X PMIC
 531          */
 532         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 533         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 534         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 535         .mpu.addr       = LP873X_REG_ADDR_BUCK0,
 536         .mpu.pmic       = &lp8733,
 537         .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
 538
 539         .core.value[OPP_NOM]            = VDD_CORE_DRA7_NOM,
 540         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 541         .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 542         .core.addr      = LP873X_REG_ADDR_BUCK0,
 543         .core.pmic      = &lp8733,
 544
 545         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 546         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 547         .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 548         .gpu.addr       = LP873X_REG_ADDR_BUCK0,
 549         .gpu.pmic       = &lp8733,
 550         .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
 551
 552         /*
 553          * The DSPEVE and IVA rails are grouped on DRA71x-evm
 554          * and are powered by BUCK1 of LP873X PMIC
 555          */
 556         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 557         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 558         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 559         .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 560         .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 561         .eve.addr       = LP873X_REG_ADDR_BUCK1,
 562         .eve.pmic       = &lp8733,
 563         .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
 564
 565         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 566         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 567         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 568         .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
 569         .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 570         .iva.addr       = LP873X_REG_ADDR_BUCK1,
 571         .iva.pmic       = &lp8733,
 572         .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
 573 };
 574
 575 int get_voltrail_opp(int rail_offset)
 576 {
 577         int opp;
 578
 579         switch (rail_offset) {
 580         case VOLT_MPU:
 581                 opp = DRA7_MPU_OPP;
 582                 /* DRA71x supports only OPP_NOM for MPU */
 583                 if (board_is_dra71x_evm())
 584                         opp = OPP_NOM;
 585                 break;
 586         case VOLT_CORE:
 587                 opp = DRA7_CORE_OPP;
 588                 /* DRA71x supports only OPP_NOM for CORE */
 589                 if (board_is_dra71x_evm())
 590                         opp = OPP_NOM;
 591                 break;
 592         case VOLT_GPU:
 593                 opp = DRA7_GPU_OPP;
 594                 /* DRA71x supports only OPP_NOM for GPU */
 595                 if (board_is_dra71x_evm())
 596                         opp = OPP_NOM;
 597                 break;
 598         case VOLT_EVE:
 599                 opp = DRA7_DSPEVE_OPP;
 600                 /*
 601                  * DRA71x does not support OPP_OD for EVE.
 602                  * If OPP_OD is selected by menuconfig, fallback
 603                  * to OPP_NOM.
 604                  */
 605                 if (board_is_dra71x_evm() && opp == OPP_OD)
 606                         opp = OPP_NOM;
 607                 break;
 608         case VOLT_IVA:
 609                 opp = DRA7_IVA_OPP;
 610                 /*
 611                  * DRA71x does not support OPP_OD for IVA.
 612                  * If OPP_OD is selected by menuconfig, fallback
 613                  * to OPP_NOM.
 614                  */
 615                 if (board_is_dra71x_evm() && opp == OPP_OD)
 616                         opp = OPP_NOM;
 617                 break;
 618         default:
 619                 opp = OPP_NOM;
 620         }
 621
 622         return opp;
 623 }
 624
 625 /**
 626  * @brief board_init
 627  *
 628  * @return 0
 629  */
 630 int board_init(void)
 631 {
 632         gpmc_init();
 633         gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
 634
 635         return 0;
 636 }
 637
 638 int dram_init_banksize(void)
 639 {
 640         u64 ram_size;
 641
 642         ram_size = board_ti_get_emif_size();
 643
 644         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 645         gd->bd->bi_dram[0].size = get_effective_memsize();
 646         if (ram_size > CONFIG_MAX_MEM_MAPPED) {
 647                 gd->bd->bi_dram[1].start = 0x200000000;
 648                 gd->bd->bi_dram[1].size = ram_size - CONFIG_MAX_MEM_MAPPED;
 649         }
 650
 651         return 0;
 652 }
 653
 654 #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
 655 static int device_okay(const char *path)
 656 {
 657         int node;
 658
 659         node = fdt_path_offset(gd->fdt_blob, path);
 660         if (node < 0)
 661                 return 0;
 662
 663         return fdtdec_get_is_enabled(gd->fdt_blob, node);
 664 }
 665 #endif
 666
 667 int board_late_init(void)
 668 {
 669 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 670         char *name = "unknown";
 671
 672         if (is_dra72x()) {
 673                 if (board_is_dra72x_revc_or_later())
 674                         name = "dra72x-revc";
 675                 else if (board_is_dra71x_evm())
 676                         name = "dra71x";
 677                 else
 678                         name = "dra72x";
 679         } else if (is_dra76x_abz()) {
 680                 name = "dra76x_abz";
 681         } else if (is_dra76x_acd()) {
 682                 name = "dra76x_acd";
 683         } else {
 684                 name = "dra7xx";
 685         }
 686
 687         set_board_info_env(name);
 688
 689         /*
 690          * Default FIT boot on HS devices. Non FIT images are not allowed
 691          * on HS devices.
 692          */
 693         if (get_device_type() == HS_DEVICE)
 694                 env_set("boot_fit", "1");
 695
 696         omap_die_id_serial();
 697         omap_set_fastboot_vars();
 698
 699         /*
 700          * Hook the LDO1 regulator to EN pin. This applies only to LP8733
 701          * Rest all regulators are hooked to EN Pin at reset.
 702          */
 703         if (board_is_dra71x_evm())
 704                 palmas_i2c_write_u8(LP873X_I2C_SLAVE_ADDR, 0x9, 0x7);
 705 #endif
 706 #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
 707         if (device_okay("/ocp/omap_dwc3_1@48880000"))
 708                 enable_usb_clocks(0);
 709         if (device_okay("/ocp/omap_dwc3_2@488c0000"))
 710                 enable_usb_clocks(1);
 711 #endif
 712         return 0;
 713 }
 714
 715 #ifdef CONFIG_SPL_BUILD
 716 void do_board_detect(void)
 717 {
 718         int rc;
 719
 720         rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
 721                                     CONFIG_EEPROM_CHIP_ADDRESS);
 722         if (rc)
 723                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 724 }
 725
 726 #else
 727
 728 void do_board_detect(void)
 729 {
 730         char *bname = NULL;
 731         int rc;
 732
 733         rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
 734                                     CONFIG_EEPROM_CHIP_ADDRESS);
 735         if (rc)
 736                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 737
 738         if (board_is_dra74x_evm()) {
 739                 bname = "DRA74x EVM";
 740         } else if (board_is_dra72x_evm()) {
 741                 bname = "DRA72x EVM";
 742         } else if (board_is_dra71x_evm()) {
 743                 bname = "DRA71x EVM";
 744         } else if (board_is_dra76x_evm()) {
 745                 bname = "DRA76x EVM";
 746         } else {
 747                 /* If EEPROM is not populated */
 748                 if (is_dra72x())
 749                         bname = "DRA72x EVM";
 750                 else
 751                         bname = "DRA74x EVM";
 752         }
 753
 754         if (bname)
 755                 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
 756                          "Board: %s REV %s\n", bname, board_ti_get_rev());
 757 }
 758 #endif  /* CONFIG_SPL_BUILD */
 759
 760 void vcores_init(void)
 761 {
 762         if (board_is_dra74x_evm()) {
 763                 *omap_vcores = &dra752_volts;
 764         } else if (board_is_dra72x_evm()) {
 765                 *omap_vcores = &dra722_volts;
 766         } else if (board_is_dra71x_evm()) {
 767                 *omap_vcores = &dra718_volts;
 768         } else if (board_is_dra76x_evm()) {
 769                 *omap_vcores = &dra76x_volts;
 770         } else {
 771                 /* If EEPROM is not populated */
 772                 if (is_dra72x())
 773                         *omap_vcores = &dra722_volts;
 774                 else
 775                         *omap_vcores = &dra752_volts;
 776         }
 777 }
 778
 779 void set_muxconf_regs(void)
 780 {
 781         do_set_mux32((*ctrl)->control_padconf_core_base,
 782                      early_padconf, ARRAY_SIZE(early_padconf));
 783 }
 784
 785 #if defined(CONFIG_NAND)
 786 static int nand_sw_detect(void)
 787 {
 788         int rc;
 789         uchar data[2];
 790         struct udevice *dev;
 791
 792         rc = i2c_get_chip_for_busnum(NAND_PCF8575_I2C_BUS_NUM,
 793                                      NAND_PCF8575_ADDR, 0, &dev);
 794         if (rc)
 795                 return -1;
 796
 797         rc = dm_i2c_read(dev, 0, (uint8_t *)&data, sizeof(data));
 798         if (rc)
 799                 return -1;
 800
 801         /* We are only interested in P10 and P11 on PCF8575 which is equal to
 802          * bits 8 and 9.
 803          */
 804         data[1] = data[1] & 0x3;
 805
 806         /* Ensure only P11 is set and P10 is cleared. This ensures only
 807          * NAND (P10) is configured and not NOR (P11) which are both low
 808          * true signals. NAND and NOR settings should not be enabled at
 809          * the same time.
 810          */
 811         if (data[1] == 0x2)
 812                 return 0;
 813
 814         return -1;
 815 }
 816 #else
 817 int nand_sw_detect(void)
 818 {
 819         return -1;
 820 }
 821 #endif
 822
 823 #ifdef CONFIG_IODELAY_RECALIBRATION
 824 void recalibrate_iodelay(void)
 825 {
 826         struct pad_conf_entry const *pads, *delta_pads = NULL;
 827         struct iodelay_cfg_entry const *iodelay;
 828         int npads, niodelays, delta_npads = 0;
 829         int ret;
 830
 831         switch (omap_revision()) {
 832         case DRA722_ES1_0:
 833         case DRA722_ES2_0:
 834         case DRA722_ES2_1:
 835                 pads = dra72x_core_padconf_array_common;
 836                 npads = ARRAY_SIZE(dra72x_core_padconf_array_common);
 837                 if (board_is_dra71x_evm()) {
 838                         pads = dra71x_core_padconf_array;
 839                         npads = ARRAY_SIZE(dra71x_core_padconf_array);
 840                         iodelay = dra71_iodelay_cfg_array;
 841                         niodelays = ARRAY_SIZE(dra71_iodelay_cfg_array);
 842                         /* If SW8 on the EVM is set to enable NAND then
 843                          * overwrite the pins used by VOUT3 with NAND.
 844                          */
 845                         if (!nand_sw_detect()) {
 846                                 delta_pads = dra71x_nand_padconf_array;
 847                                 delta_npads =
 848                                         ARRAY_SIZE(dra71x_nand_padconf_array);
 849                         } else {
 850                                 delta_pads = dra71x_vout3_padconf_array;
 851                                 delta_npads =
 852                                         ARRAY_SIZE(dra71x_vout3_padconf_array);
 853                         }
 854
 855                 } else if (board_is_dra72x_revc_or_later()) {
 856                         delta_pads = dra72x_rgmii_padconf_array_revc;
 857                         delta_npads =
 858                                 ARRAY_SIZE(dra72x_rgmii_padconf_array_revc);
 859                         iodelay = dra72_iodelay_cfg_array_revc;
 860                         niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revc);
 861                 } else {
 862                         delta_pads = dra72x_rgmii_padconf_array_revb;
 863                         delta_npads =
 864                                 ARRAY_SIZE(dra72x_rgmii_padconf_array_revb);
 865                         iodelay = dra72_iodelay_cfg_array_revb;
 866                         niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revb);
 867                 }
 868                 break;
 869         case DRA752_ES1_0:
 870         case DRA752_ES1_1:
 871                 pads = dra74x_core_padconf_array;
 872                 npads = ARRAY_SIZE(dra74x_core_padconf_array);
 873                 iodelay = dra742_es1_1_iodelay_cfg_array;
 874                 niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array);
 875                 break;
 876         case DRA762_ACD_ES1_0:
 877         case DRA762_ES1_0:
 878                 pads = dra76x_core_padconf_array;
 879                 npads = ARRAY_SIZE(dra76x_core_padconf_array);
 880                 iodelay = dra76x_es1_0_iodelay_cfg_array;
 881                 niodelays = ARRAY_SIZE(dra76x_es1_0_iodelay_cfg_array);
 882                 break;
 883         default:
 884         case DRA752_ES2_0:
 885         case DRA762_ABZ_ES1_0:
 886                 pads = dra74x_core_padconf_array;
 887                 npads = ARRAY_SIZE(dra74x_core_padconf_array);
 888                 iodelay = dra742_es2_0_iodelay_cfg_array;
 889                 niodelays = ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array);
 890                 /* Setup port1 and port2 for rgmii with 'no-id' mode */
 891                 clrset_spare_register(1, 0, RGMII2_ID_MODE_N_MASK |
 892                                       RGMII1_ID_MODE_N_MASK);
 893                 break;
 894         }
 895         /* Setup I/O isolation */
 896         ret = __recalibrate_iodelay_start();
 897         if (ret)
 898                 goto err;
 899
 900         /* Do the muxing here */
 901         do_set_mux32((*ctrl)->control_padconf_core_base, pads, npads);
 902
 903         /* Now do the weird minor deltas that should be safe */
 904         if (delta_npads)
 905                 do_set_mux32((*ctrl)->control_padconf_core_base,
 906                              delta_pads, delta_npads);
 907
 908         if (is_dra76x())
 909                 /* Set mux for MCAN instead of DCAN1 */
 910                 clrsetbits_le32((*ctrl)->control_core_control_spare_rw,
 911                                 MCAN_SEL_ALT_MASK, MCAN_SEL);
 912
 913         /* Setup IOdelay configuration */
 914         ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays);
 915 err:
 916         /* Closeup.. remove isolation */
 917         __recalibrate_iodelay_end(ret);
 918 }
 919 #endif
 920
 921 #if defined(CONFIG_MMC)
 922 int board_mmc_init(bd_t *bis)
 923 {
 924         omap_mmc_init(0, 0, 0, -1, -1);
 925         omap_mmc_init(1, 0, 0, -1, -1);
 926         return 0;
 927 }
 928
 929 void board_mmc_poweron_ldo(uint voltage)
 930 {
 931         if (board_is_dra71x_evm()) {
 932                 if (voltage == LDO_VOLT_3V0)
 933                         voltage = 0x19;
 934                 else if (voltage == LDO_VOLT_1V8)
 935                         voltage = 0xa;
 936                 lp873x_mmc1_poweron_ldo(voltage);
 937         } else if (board_is_dra76x_evm()) {
 938                 palmas_mmc1_poweron_ldo(LDO4_VOLTAGE, LDO4_CTRL, voltage);
 939         } else {
 940                 palmas_mmc1_poweron_ldo(LDO1_VOLTAGE, LDO1_CTRL, voltage);
 941         }
 942 }
 943
 944 static const struct mmc_platform_fixups dra7x_es1_1_mmc1_fixups = {
 945         .hw_rev = "rev11",
 946         .unsupported_caps = MMC_CAP(MMC_HS_200) |
 947                             MMC_CAP(UHS_SDR104),
 948         .max_freq = 96000000,
 949 };
 950
 951 static const struct mmc_platform_fixups dra7x_es1_1_mmc23_fixups = {
 952         .hw_rev = "rev11",
 953         .unsupported_caps = MMC_CAP(MMC_HS_200) |
 954                             MMC_CAP(UHS_SDR104) |
 955                             MMC_CAP(UHS_SDR50),
 956         .max_freq = 48000000,
 957 };
 958
 959 const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
 960 {
 961         switch (omap_revision()) {
 962         case DRA752_ES1_0:
 963         case DRA752_ES1_1:
 964                 if (addr == OMAP_HSMMC1_BASE)
 965                         return &dra7x_es1_1_mmc1_fixups;
 966                 else
 967                         return &dra7x_es1_1_mmc23_fixups;
 968         default:
 969                 return NULL;
 970         }
 971 }
 972 #endif
 973
 974 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
 975 int spl_start_uboot(void)
 976 {
 977         /* break into full u-boot on 'c' */
 978         if (serial_tstc() && serial_getc() == 'c')
 979                 return 1;
 980
 981 #ifdef CONFIG_SPL_ENV_SUPPORT
 982         env_init();
 983         env_load();
 984         if (env_get_yesno("boot_os") != 1)
 985                 return 1;
 986 #endif
 987
 988         return 0;
 989 }
 990 #endif
 991
 992 #ifdef CONFIG_DRIVER_TI_CPSW
 993 extern u32 *const omap_si_rev;
 994
 995 static void cpsw_control(int enabled)
 996 {
 997         /* VTP can be added here */
 998
 999         return;
1000 }
1001
1002 static struct cpsw_slave_data cpsw_slaves[] = {
1003         {
1004                 .slave_reg_ofs  = 0x208,
1005                 .sliver_reg_ofs = 0xd80,
1006                 .phy_addr       = 2,
1007         },
1008         {
1009                 .slave_reg_ofs  = 0x308,
1010                 .sliver_reg_ofs = 0xdc0,
1011                 .phy_addr       = 3,
1012         },
1013 };
1014
1015 static struct cpsw_platform_data cpsw_data = {
1016         .mdio_base              = CPSW_MDIO_BASE,
1017         .cpsw_base              = CPSW_BASE,
1018         .mdio_div               = 0xff,
1019         .channels               = 8,
1020         .cpdma_reg_ofs          = 0x800,
1021         .slaves                 = 2,
1022         .slave_data             = cpsw_slaves,
1023         .ale_reg_ofs            = 0xd00,
1024         .ale_entries            = 1024,
1025         .host_port_reg_ofs      = 0x108,
1026         .hw_stats_reg_ofs       = 0x900,
1027         .bd_ram_ofs             = 0x2000,
1028         .mac_control            = (1 << 5),
1029         .control                = cpsw_control,
1030         .host_port_num          = 0,
1031         .version                = CPSW_CTRL_VERSION_2,
1032 };
1033
1034 int board_eth_init(bd_t *bis)
1035 {
1036         int ret;
1037         uint8_t mac_addr[6];
1038         uint32_t mac_hi, mac_lo;
1039         uint32_t ctrl_val;
1040
1041         /* try reading mac address from efuse */
1042         mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
1043         mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
1044         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
1045         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
1046         mac_addr[2] = mac_hi & 0xFF;
1047         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
1048         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
1049         mac_addr[5] = mac_lo & 0xFF;
1050
1051         if (!env_get("ethaddr")) {
1052                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
1053
1054                 if (is_valid_ethaddr(mac_addr))
1055                         eth_env_set_enetaddr("ethaddr", mac_addr);
1056         }
1057
1058         mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
1059         mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
1060         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
1061         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
1062         mac_addr[2] = mac_hi & 0xFF;
1063         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
1064         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
1065         mac_addr[5] = mac_lo & 0xFF;
1066
1067         if (!env_get("eth1addr")) {
1068                 if (is_valid_ethaddr(mac_addr))
1069                         eth_env_set_enetaddr("eth1addr", mac_addr);
1070         }
1071
1072         ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
1073         ctrl_val |= 0x22;
1074         writel(ctrl_val, (*ctrl)->control_core_control_io1);
1075
1076         if (*omap_si_rev == DRA722_ES1_0)
1077                 cpsw_data.active_slave = 1;
1078
1079         if (board_is_dra72x_revc_or_later()) {
1080                 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII_ID;
1081                 cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII_ID;
1082         }
1083
1084         ret = cpsw_register(&cpsw_data);
1085         if (ret < 0)
1086                 printf("Error %d registering CPSW switch\n", ret);
1087
1088         return ret;
1089 }
1090 #endif
1091
1092 #ifdef CONFIG_BOARD_EARLY_INIT_F
1093 /* VTT regulator enable */
1094 static inline void vtt_regulator_enable(void)
1095 {
1096         if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
1097                 return;
1098
1099         /* Do not enable VTT for DRA722 or DRA76x */
1100         if (is_dra72x() || is_dra76x())
1101                 return;
1102
1103         /*
1104          * EVM Rev G and later use gpio7_11 for DDR3 termination.
1105          * This is safe enough to do on older revs.
1106          */
1107         gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
1108         gpio_direction_output(GPIO_DDR_VTT_EN, 1);
1109 }
1110
1111 int board_early_init_f(void)
1112 {
1113         vtt_regulator_enable();
1114         return 0;
1115 }
1116 #endif
1117
1118 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
1119 int ft_board_setup(void *blob, bd_t *bd)
1120 {
1121         ft_cpu_setup(blob, bd);
1122
1123         return 0;
1124 }
1125 #endif
1126
1127 #ifdef CONFIG_SPL_LOAD_FIT
1128 int board_fit_config_name_match(const char *name)
1129 {
1130         if (is_dra72x()) {
1131                 if (board_is_dra71x_evm()) {
1132                         if (!strcmp(name, "dra71-evm"))
1133                                 return 0;
1134                 }else if(board_is_dra72x_revc_or_later()) {
1135                         if (!strcmp(name, "dra72-evm-revc"))
1136                                 return 0;
1137                 } else if (!strcmp(name, "dra72-evm")) {
1138                         return 0;
1139                 }
1140         } else if (is_dra76x_acd() && !strcmp(name, "dra76-evm")) {
1141                 return 0;
1142         } else if (!is_dra72x() && !is_dra76x_acd() &&
1143                    !strcmp(name, "dra7-evm")) {
1144                 return 0;
1145         }
1146
1147         return -1;
1148 }
1149 #endif
1150
1151 #if CONFIG_IS_ENABLED(FASTBOOT) && !CONFIG_IS_ENABLED(ENV_IS_NOWHERE)
1152 int fastboot_set_reboot_flag(void)
1153 {
1154         printf("Setting reboot to fastboot flag ...\n");
1155         env_set("dofastboot", "1");
1156         env_save();
1157         return 0;
1158 }
1159 #endif
1160
1161 #ifdef CONFIG_TI_SECURE_DEVICE
1162 void board_fit_image_post_process(void **p_image, size_t *p_size)
1163 {
1164         secure_boot_verify_image(p_image, p_size);
1165 }
1166
1167 void board_tee_image_process(ulong tee_image, size_t tee_size)
1168 {
1169         secure_tee_install((u32)tee_image);
1170 }
1171
1172 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
1173 #endif