drivers/ddr/fsl/mpc85xx_ddr_gen3.c

   1 /*
   2  * Copyright 2008-2012 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * Version 2 as published by the Free Software Foundation.
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <fsl_ddr_sdram.h>
  12 #include <asm/processor.h>
  13
  14 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
  15 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
  16 #endif
  17
  18 DECLARE_GLOBAL_DATA_PTR;
  19
  20 /*
  21  * regs has the to-be-set values for DDR controller registers
  22  * ctrl_num is the DDR controller number
  23  * step: 0 goes through the initialization in one pass
  24  *       1 sets registers and returns before enabling controller
  25  *       2 resumes from step 1 and continues to initialize
  26  * Dividing the initialization to two steps to deassert DDR reset signal
  27  * to comply with JEDEC specs for RDIMMs.
  28  */
  29 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
  30                              unsigned int ctrl_num, int step)
  31 {
  32         unsigned int i, bus_width;
  33         struct ccsr_ddr __iomem *ddr;
  34         u32 temp_sdram_cfg;
  35         u32 total_gb_size_per_controller;
  36         int timeout;
  37 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
  38         int timeout_save;
  39         volatile ccsr_local_ecm_t *ecm = (void *)CONFIG_SYS_MPC85xx_ECM_ADDR;
  40         unsigned int csn_bnds_backup = 0, cs_sa, cs_ea, *csn_bnds_t;
  41         int csn = -1;
  42 #endif
  43 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
  44         u32 save1, save2;
  45 #endif
  46
  47 #ifdef CONFIG_DEEP_SLEEP
  48         const ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  49         bool sleep_flag = 0;
  50 #endif
  51
  52 #ifdef CONFIG_DEEP_SLEEP
  53         if (in_be32(&gur->scrtsr[0]) & (1 << 3))
  54                 sleep_flag = 1;
  55 #endif
  56
  57         switch (ctrl_num) {
  58         case 0:
  59                 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
  60                 break;
  61 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
  62         case 1:
  63                 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
  64                 break;
  65 #endif
  66 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
  67         case 2:
  68                 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
  69                 break;
  70 #endif
  71 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
  72         case 3:
  73                 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
  74                 break;
  75 #endif
  76         default:
  77                 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
  78                 return;
  79         }
  80
  81         if (step == 2)
  82                 goto step2;
  83
  84         if (regs->ddr_eor)
  85                 out_be32(&ddr->eor, regs->ddr_eor);
  86 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
  87         debug("Workaround for ERRATUM_DDR111_DDR134\n");
  88         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  89                 cs_sa = (regs->cs[i].bnds >> 16) & 0xfff;
  90                 cs_ea = regs->cs[i].bnds & 0xfff;
  91                 if ((cs_sa <= 0xff) && (cs_ea >= 0xff)) {
  92                         csn = i;
  93                         csn_bnds_backup = regs->cs[i].bnds;
  94                         csn_bnds_t = (unsigned int *) &regs->cs[i].bnds;
  95                         if (cs_ea > 0xeff)
  96                                 *csn_bnds_t = regs->cs[i].bnds + 0x01000000;
  97                         else
  98                                 *csn_bnds_t = regs->cs[i].bnds + 0x01000100;
  99                         debug("Found cs%d_bns (0x%08x) covering 0xff000000, "
 100                                 "change it to 0x%x\n",
 101                                 csn, csn_bnds_backup, regs->cs[i].bnds);
 102                         break;
 103                 }
 104         }
 105 #endif
 106         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 107                 if (i == 0) {
 108                         out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
 109                         out_be32(&ddr->cs0_config, regs->cs[i].config);
 110                         out_be32(&ddr->cs0_config_2, regs->cs[i].config_2);
 111
 112                 } else if (i == 1) {
 113                         out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
 114                         out_be32(&ddr->cs1_config, regs->cs[i].config);
 115                         out_be32(&ddr->cs1_config_2, regs->cs[i].config_2);
 116
 117                 } else if (i == 2) {
 118                         out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
 119                         out_be32(&ddr->cs2_config, regs->cs[i].config);
 120                         out_be32(&ddr->cs2_config_2, regs->cs[i].config_2);
 121
 122                 } else if (i == 3) {
 123                         out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
 124                         out_be32(&ddr->cs3_config, regs->cs[i].config);
 125                         out_be32(&ddr->cs3_config_2, regs->cs[i].config_2);
 126                 }
 127         }
 128
 129         out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
 130         out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
 131         out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
 132         out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
 133 #ifdef CONFIG_DEEP_SLEEP
 134         if (sleep_flag)
 135                 out_be32(&ddr->sdram_cfg_2,
 136                          regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
 137         else
 138 #endif
 139                 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
 140         out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
 141         out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
 142         out_be32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
 143         out_be32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4);
 144         out_be32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5);
 145         out_be32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6);
 146         out_be32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7);
 147         out_be32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8);
 148         out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
 149         out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
 150         out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
 151         out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
 152 #ifdef CONFIG_DEEP_SLEEP
 153         if (sleep_flag) {
 154                 out_be32(&ddr->init_addr, 0);
 155                 out_be32(&ddr->init_ext_addr, (1 << 31));
 156         } else
 157 #endif
 158         {
 159                 out_be32(&ddr->init_addr, regs->ddr_init_addr);
 160                 out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
 161         }
 162
 163         out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4);
 164         out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5);
 165         out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
 166         out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
 167 #ifndef CONFIG_SYS_FSL_DDR_EMU
 168         /*
 169          * Skip these two registers if running on emulator
 170          * because emulator doesn't have skew between bytes.
 171          */
 172
 173         if (regs->ddr_wrlvl_cntl_2)
 174                 out_be32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2);
 175         if (regs->ddr_wrlvl_cntl_3)
 176                 out_be32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3);
 177 #endif
 178
 179         out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
 180         out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
 181         out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
 182         out_be32(&ddr->ddr_cdr1, regs->ddr_cdr1);
 183         out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2);
 184         out_be32(&ddr->err_disable, regs->err_disable);
 185         out_be32(&ddr->err_int_en, regs->err_int_en);
 186         for (i = 0; i < 32; i++) {
 187                 if (regs->debug[i]) {
 188                         debug("Write to debug_%d as %08x\n", i+1, regs->debug[i]);
 189                         out_be32(&ddr->debug[i], regs->debug[i]);
 190                 }
 191         }
 192 #ifdef CONFIG_SYS_FSL_ERRATUM_A_004934
 193         out_be32(&ddr->debug[28], 0x30003000);
 194 #endif
 195
 196 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003474
 197         out_be32(&ddr->debug[12], 0x00000015);
 198         out_be32(&ddr->debug[21], 0x24000000);
 199 #endif /* CONFIG_SYS_FSL_ERRATUM_DDR_A003474 */
 200
 201         /*
 202          * For RDIMMs, JEDEC spec requires clocks to be stable before reset is
 203          * deasserted. Clocks start when any chip select is enabled and clock
 204          * control register is set. Because all DDR components are connected to
 205          * one reset signal, this needs to be done in two steps. Step 1 is to
 206          * get the clocks started. Step 2 resumes after reset signal is
 207          * deasserted.
 208          */
 209         if (step == 1) {
 210                 udelay(200);
 211                 return;
 212         }
 213
 214 step2:
 215         /* Set, but do not enable the memory */
 216         temp_sdram_cfg = regs->ddr_sdram_cfg;
 217         temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
 218         out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
 219 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
 220         debug("Workaround for ERRATUM_DDR_A003\n");
 221         if (regs->ddr_sdram_rcw_2 & 0x00f00000) {
 222                 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2 & 0xf07fffff);
 223                 out_be32(&ddr->debug[2], 0x00000400);
 224                 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl & 0x7fffffff);
 225                 out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl & 0x7fffffff);
 226                 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & 0xffffffeb);
 227                 out_be32(&ddr->mtcr, 0);
 228                 save1 = in_be32(&ddr->debug[12]);
 229                 save2 = in_be32(&ddr->debug[21]);
 230                 out_be32(&ddr->debug[12], 0x00000015);
 231                 out_be32(&ddr->debug[21], 0x24000000);
 232                 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval & 0xffff);
 233                 out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_BI | SDRAM_CFG_MEM_EN);
 234
 235                 asm volatile("sync;isync");
 236                 while (!(in_be32(&ddr->debug[1]) & 0x2))
 237                         ;
 238
 239                 switch (regs->ddr_sdram_rcw_2 & 0x00f00000) {
 240                 case 0x00000000:
 241                         out_be32(&ddr->sdram_md_cntl,
 242                                 MD_CNTL_MD_EN           |
 243                                 MD_CNTL_CS_SEL_CS0_CS1  |
 244                                 0x04000000              |
 245                                 MD_CNTL_WRCW            |
 246                                 MD_CNTL_MD_VALUE(0x02));
 247 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
 248                         if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))
 249                                 break;
 250                         while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN)
 251                                 ;
 252                         out_be32(&ddr->sdram_md_cntl,
 253                                  MD_CNTL_MD_EN          |
 254                                  MD_CNTL_CS_SEL_CS2_CS3 |
 255                                  0x04000000             |
 256                                  MD_CNTL_WRCW           |
 257                                  MD_CNTL_MD_VALUE(0x02));
 258 #endif
 259                         break;
 260                 case 0x00100000:
 261                         out_be32(&ddr->sdram_md_cntl,
 262                                 MD_CNTL_MD_EN           |
 263                                 MD_CNTL_CS_SEL_CS0_CS1  |
 264                                 0x04000000              |
 265                                 MD_CNTL_WRCW            |
 266                                 MD_CNTL_MD_VALUE(0x0a));
 267 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
 268                         if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))
 269                                 break;
 270                         while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN)
 271                                 ;
 272                         out_be32(&ddr->sdram_md_cntl,
 273                                  MD_CNTL_MD_EN          |
 274                                  MD_CNTL_CS_SEL_CS2_CS3 |
 275                                  0x04000000             |
 276                                  MD_CNTL_WRCW           |
 277                                  MD_CNTL_MD_VALUE(0x0a));
 278 #endif
 279                         break;
 280                 case 0x00200000:
 281                         out_be32(&ddr->sdram_md_cntl,
 282                                 MD_CNTL_MD_EN           |
 283                                 MD_CNTL_CS_SEL_CS0_CS1  |
 284                                 0x04000000              |
 285                                 MD_CNTL_WRCW            |
 286                                 MD_CNTL_MD_VALUE(0x12));
 287 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
 288                         if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))
 289                                 break;
 290                         while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN)
 291                                 ;
 292                         out_be32(&ddr->sdram_md_cntl,
 293                                  MD_CNTL_MD_EN          |
 294                                  MD_CNTL_CS_SEL_CS2_CS3 |
 295                                  0x04000000             |
 296                                  MD_CNTL_WRCW           |
 297                                  MD_CNTL_MD_VALUE(0x12));
 298 #endif
 299                         break;
 300                 case 0x00300000:
 301                         out_be32(&ddr->sdram_md_cntl,
 302                                 MD_CNTL_MD_EN           |
 303                                 MD_CNTL_CS_SEL_CS0_CS1  |
 304                                 0x04000000              |
 305                                 MD_CNTL_WRCW            |
 306                                 MD_CNTL_MD_VALUE(0x1a));
 307 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
 308                         if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))
 309                                 break;
 310                         while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN)
 311                                 ;
 312                         out_be32(&ddr->sdram_md_cntl,
 313                                  MD_CNTL_MD_EN          |
 314                                  MD_CNTL_CS_SEL_CS2_CS3 |
 315                                  0x04000000             |
 316                                  MD_CNTL_WRCW           |
 317                                  MD_CNTL_MD_VALUE(0x1a));
 318 #endif
 319                         break;
 320                 default:
 321                         out_be32(&ddr->sdram_md_cntl,
 322                                 MD_CNTL_MD_EN           |
 323                                 MD_CNTL_CS_SEL_CS0_CS1  |
 324                                 0x04000000              |
 325                                 MD_CNTL_WRCW            |
 326                                 MD_CNTL_MD_VALUE(0x02));
 327 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
 328                         if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))
 329                                 break;
 330                         while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN)
 331                                 ;
 332                         out_be32(&ddr->sdram_md_cntl,
 333                                  MD_CNTL_MD_EN          |
 334                                  MD_CNTL_CS_SEL_CS2_CS3 |
 335                                  0x04000000             |
 336                                  MD_CNTL_WRCW           |
 337                                  MD_CNTL_MD_VALUE(0x02));
 338 #endif
 339                         printf("Unsupported RC10\n");
 340                         break;
 341                 }
 342
 343                 while (in_be32(&ddr->sdram_md_cntl) & 0x80000000)
 344                         ;
 345                 udelay(6);
 346                 out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
 347                 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
 348                 out_be32(&ddr->debug[2], 0x0);
 349                 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
 350                 out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
 351                 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
 352                 out_be32(&ddr->debug[12], save1);
 353                 out_be32(&ddr->debug[21], save2);
 354                 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
 355
 356         }
 357 #endif
 358         /*
 359          * For 8572 DDR1 erratum - DDR controller may enter illegal state
 360          * when operatiing in 32-bit bus mode with 4-beat bursts,
 361          * This erratum does not affect DDR3 mode, only for DDR2 mode.
 362          */
 363 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_115
 364         debug("Workaround for ERRATUM_DDR_115\n");
 365         if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2)
 366             && in_be32(&ddr->sdram_cfg) & 0x80000) {
 367                 /* set DEBUG_1[31] */
 368                 setbits_be32(&ddr->debug[0], 1);
 369         }
 370 #endif
 371 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
 372         debug("Workaround for ERRATUM_DDR111_DDR134\n");
 373         /*
 374          * This is the combined workaround for DDR111 and DDR134
 375          * following the published errata for MPC8572
 376          */
 377
 378         /* 1. Set EEBACR[3] */
 379         setbits_be32(&ecm->eebacr, 0x10000000);
 380         debug("Setting EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr));
 381
 382         /* 2. Set DINIT in SDRAM_CFG_2*/
 383         setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_D_INIT);
 384         debug("Setting sdram_cfg_2[D_INIT] to 0x%08x\n",
 385                 in_be32(&ddr->sdram_cfg_2));
 386
 387         /* 3. Set DEBUG_3[21] */
 388         setbits_be32(&ddr->debug[2], 0x400);
 389         debug("Setting DEBUG_3[21] to 0x%08x\n", in_be32(&ddr->debug[2]));
 390
 391 #endif  /* part 1 of the workaound */
 392
 393         /*
 394          * 500 painful micro-seconds must elapse between
 395          * the DDR clock setup and the DDR config enable.
 396          * DDR2 need 200 us, and DDR3 need 500 us from spec,
 397          * we choose the max, that is 500 us for all of case.
 398          */
 399         udelay(500);
 400         asm volatile("sync;isync");
 401
 402 #ifdef CONFIG_DEEP_SLEEP
 403         if (sleep_flag) {
 404                 /* enter self-refresh */
 405                 setbits_be32(&ddr->sdram_cfg_2, (1 << 31));
 406                 /* do board specific memory setup */
 407                 board_mem_sleep_setup();
 408         }
 409 #endif
 410
 411         /* Let the controller go */
 412 #ifdef CONFIG_DEEP_SLEEP
 413         if (sleep_flag)
 414                 temp_sdram_cfg = (in_be32(&ddr->sdram_cfg) | SDRAM_CFG_BI);
 415         else
 416 #endif
 417                 temp_sdram_cfg = (in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI);
 418         out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
 419         asm volatile("sync;isync");
 420
 421         total_gb_size_per_controller = 0;
 422         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 423                 if (!(regs->cs[i].config & 0x80000000))
 424                         continue;
 425                 total_gb_size_per_controller += 1 << (
 426                         ((regs->cs[i].config >> 14) & 0x3) + 2 +
 427                         ((regs->cs[i].config >> 8) & 0x7) + 12 +
 428                         ((regs->cs[i].config >> 0) & 0x7) + 8 +
 429                         3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) -
 430                         26);                    /* minus 26 (count of 64M) */
 431         }
 432         if (fsl_ddr_get_intl3r() & 0x80000000)  /* 3-way interleaving */
 433                 total_gb_size_per_controller *= 3;
 434         else if (regs->cs[0].config & 0x20000000) /* 2-way interleaving */
 435                 total_gb_size_per_controller <<= 1;
 436         /*
 437          * total memory / bus width = transactions needed
 438          * transactions needed / data rate = seconds
 439          * to add plenty of buffer, double the time
 440          * For example, 2GB on 666MT/s 64-bit bus takes about 402ms
 441          * Let's wait for 800ms
 442          */
 443         bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK)
 444                         >> SDRAM_CFG_DBW_SHIFT);
 445         timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
 446                 (get_ddr_freq(0) >> 20)) << 1;
 447 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
 448         timeout_save = timeout;
 449 #endif
 450         total_gb_size_per_controller >>= 4;     /* shift down to gb size */
 451         debug("total %d GB\n", total_gb_size_per_controller);
 452         debug("Need to wait up to %d * 10ms\n", timeout);
 453
 454         /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done.  */
 455         while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
 456                 (timeout >= 0)) {
 457                 udelay(10000);          /* throttle polling rate */
 458                 timeout--;
 459         }
 460
 461         if (timeout <= 0)
 462                 printf("Waiting for D_INIT timeout. Memory may not work.\n");
 463
 464 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
 465         /* continue this workaround */
 466
 467         /* 4. Clear DEBUG3[21] */
 468         clrbits_be32(&ddr->debug[2], 0x400);
 469         debug("Clearing D3[21] to 0x%08x\n", in_be32(&ddr->debug[2]));
 470
 471         /* DDR134 workaround starts */
 472         /* A: Clear sdram_cfg_2[odt_cfg] */
 473         clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_ODT_CFG_MASK);
 474         debug("Clearing SDRAM_CFG2[ODT_CFG] to 0x%08x\n",
 475                 in_be32(&ddr->sdram_cfg_2));
 476
 477         /* B: Set DEBUG1[15] */
 478         setbits_be32(&ddr->debug[0], 0x10000);
 479         debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0]));
 480
 481         /* C: Set timing_cfg_2[cpo] to 0b11111 */
 482         setbits_be32(&ddr->timing_cfg_2, TIMING_CFG_2_CPO_MASK);
 483         debug("Setting TMING_CFG_2[CPO] to 0x%08x\n",
 484                 in_be32(&ddr->timing_cfg_2));
 485
 486         /* D: Set D6 to 0x9f9f9f9f */
 487         out_be32(&ddr->debug[5], 0x9f9f9f9f);
 488         debug("Setting D6 to 0x%08x\n", in_be32(&ddr->debug[5]));
 489
 490         /* E: Set D7 to 0x9f9f9f9f */
 491         out_be32(&ddr->debug[6], 0x9f9f9f9f);
 492         debug("Setting D7 to 0x%08x\n", in_be32(&ddr->debug[6]));
 493
 494         /* F: Set D2[20] */
 495         setbits_be32(&ddr->debug[1], 0x800);
 496         debug("Setting D2[20] to 0x%08x\n", in_be32(&ddr->debug[1]));
 497
 498         /* G: Poll on D2[20] until cleared */
 499         while (in_be32(&ddr->debug[1]) & 0x800)
 500                 udelay(10000);          /* throttle polling rate */
 501
 502         /* H: Clear D1[15] */
 503         clrbits_be32(&ddr->debug[0], 0x10000);
 504         debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0]));
 505
 506         /* I: Set sdram_cfg_2[odt_cfg] */
 507         setbits_be32(&ddr->sdram_cfg_2,
 508                 regs->ddr_sdram_cfg_2 & SDRAM_CFG2_ODT_CFG_MASK);
 509         debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2));
 510
 511         /* Continuing with the DDR111 workaround */
 512         /* 5. Set D2[21] */
 513         setbits_be32(&ddr->debug[1], 0x400);
 514         debug("Setting D2[21] to 0x%08x\n", in_be32(&ddr->debug[1]));
 515
 516         /* 6. Poll D2[21] until its cleared */
 517         while (in_be32(&ddr->debug[1]) & 0x400)
 518                 udelay(10000);          /* throttle polling rate */
 519
 520         /* 7. Wait for state machine 2nd run, roughly 400ms/GB */
 521         debug("Wait for %d * 10ms\n", timeout_save);
 522         udelay(timeout_save * 10000);
 523
 524         /* 8. Set sdram_cfg_2[dinit] if options requires */
 525         setbits_be32(&ddr->sdram_cfg_2,
 526                 regs->ddr_sdram_cfg_2 & SDRAM_CFG2_D_INIT);
 527         debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2));
 528
 529         /* 9. Poll until dinit is cleared */
 530         timeout = timeout_save;
 531         debug("Need to wait up to %d * 10ms\n", timeout);
 532         while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
 533                 (timeout >= 0)) {
 534                 udelay(10000);          /* throttle polling rate */
 535                 timeout--;
 536         }
 537
 538         if (timeout <= 0)
 539                 printf("Waiting for D_INIT timeout. Memory may not work.\n");
 540
 541         /* 10. Clear EEBACR[3] */
 542         clrbits_be32(&ecm->eebacr, 10000000);
 543         debug("Clearing EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr));
 544
 545         if (csn != -1) {
 546                 csn_bnds_t = (unsigned int *) &regs->cs[csn].bnds;
 547                 *csn_bnds_t = csn_bnds_backup;
 548                 debug("Change cs%d_bnds back to 0x%08x\n",
 549                         csn, regs->cs[csn].bnds);
 550                 setbits_be32(&ddr->sdram_cfg, 0x2);     /* MEM_HALT */
 551                 switch (csn) {
 552                 case 0:
 553                         out_be32(&ddr->cs0_bnds, regs->cs[csn].bnds);
 554                         break;
 555                 case 1:
 556                         out_be32(&ddr->cs1_bnds, regs->cs[csn].bnds);
 557                         break;
 558                 case 2:
 559                         out_be32(&ddr->cs2_bnds, regs->cs[csn].bnds);
 560                         break;
 561                 case 3:
 562                         out_be32(&ddr->cs3_bnds, regs->cs[csn].bnds);
 563                         break;
 564                 }
 565                 clrbits_be32(&ddr->sdram_cfg, 0x2);
 566         }
 567 #endif /* CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 */
 568 #ifdef CONFIG_DEEP_SLEEP
 569         if (sleep_flag)
 570                 /* exit self-refresh */
 571                 clrbits_be32(&ddr->sdram_cfg_2, (1 << 31));
 572 #endif
 573 }