dts/upstream/src/arm64/tesla/fsd.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Tesla Full Self-Driving SoC device tree source
   4  *
   5  * Copyright (c) 2017-2022 Samsung Electronics Co., Ltd.
   6  *              https://www.samsung.com
   7  * Copyright (c) 2017-2022 Tesla, Inc.
   8  *              https://www.tesla.com
   9  */
  10
  11 #include <dt-bindings/clock/fsd-clk.h>
  12 #include <dt-bindings/interrupt-controller/arm-gic.h>
  13
  14 / {
  15         compatible = "tesla,fsd";
  16         interrupt-parent = <&gic>;
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         aliases {
  21                 i2c0 = &hsi2c_0;
  22                 i2c1 = &hsi2c_1;
  23                 i2c2 = &hsi2c_2;
  24                 i2c3 = &hsi2c_3;
  25                 i2c4 = &hsi2c_4;
  26                 i2c5 = &hsi2c_5;
  27                 i2c6 = &hsi2c_6;
  28                 i2c7 = &hsi2c_7;
  29                 pinctrl0 = &pinctrl_fsys0;
  30                 pinctrl1 = &pinctrl_peric;
  31                 pinctrl2 = &pinctrl_pmu;
  32                 spi0 = &spi_0;
  33                 spi1 = &spi_1;
  34                 spi2 = &spi_2;
  35         };
  36
  37         cpus {
  38                 #address-cells = <2>;
  39                 #size-cells = <0>;
  40
  41                 cpu-map {
  42                         cluster0 {
  43                                 core0 {
  44                                         cpu = <&cpucl0_0>;
  45                                 };
  46                                 core1 {
  47                                         cpu = <&cpucl0_1>;
  48                                 };
  49                                 core2 {
  50                                         cpu = <&cpucl0_2>;
  51                                 };
  52                                 core3 {
  53                                         cpu = <&cpucl0_3>;
  54                                 };
  55                         };
  56
  57                         cluster1 {
  58                                 core0 {
  59                                         cpu = <&cpucl1_0>;
  60                                 };
  61                                 core1 {
  62                                         cpu = <&cpucl1_1>;
  63                                 };
  64                                 core2 {
  65                                         cpu = <&cpucl1_2>;
  66                                 };
  67                                 core3 {
  68                                         cpu = <&cpucl1_3>;
  69                                 };
  70                         };
  71
  72                         cluster2 {
  73                                 core0 {
  74                                         cpu = <&cpucl2_0>;
  75                                 };
  76                                 core1 {
  77                                         cpu = <&cpucl2_1>;
  78                                 };
  79                                 core2 {
  80                                         cpu = <&cpucl2_2>;
  81                                 };
  82                                 core3 {
  83                                         cpu = <&cpucl2_3>;
  84                                 };
  85                         };
  86                 };
  87
  88                 /* Cluster 0 */
  89                 cpucl0_0: cpu@0 {
  90                                 device_type = "cpu";
  91                                 compatible = "arm,cortex-a72";
  92                                 reg = <0x0 0x000>;
  93                                 enable-method = "psci";
  94                                 clock-frequency = <2400000000>;
  95                                 cpu-idle-states = <&CPU_SLEEP>;
  96                                 i-cache-size = <0xc000>;
  97                                 i-cache-line-size = <64>;
  98                                 i-cache-sets = <256>;
  99                                 d-cache-size = <0x8000>;
 100                                 d-cache-line-size = <64>;
 101                                 d-cache-sets = <256>;
 102                                 next-level-cache = <&cpucl_l2>;
 103                 };
 104
 105                 cpucl0_1: cpu@1 {
 106                                 device_type = "cpu";
 107                                 compatible = "arm,cortex-a72";
 108                                 reg = <0x0 0x001>;
 109                                 enable-method = "psci";
 110                                 clock-frequency = <2400000000>;
 111                                 cpu-idle-states = <&CPU_SLEEP>;
 112                                 i-cache-size = <0xc000>;
 113                                 i-cache-line-size = <64>;
 114                                 i-cache-sets = <256>;
 115                                 d-cache-size = <0x8000>;
 116                                 d-cache-line-size = <64>;
 117                                 d-cache-sets = <256>;
 118                                 next-level-cache = <&cpucl_l2>;
 119                 };
 120
 121                 cpucl0_2: cpu@2 {
 122                                 device_type = "cpu";
 123                                 compatible = "arm,cortex-a72";
 124                                 reg = <0x0 0x002>;
 125                                 enable-method = "psci";
 126                                 clock-frequency = <2400000000>;
 127                                 cpu-idle-states = <&CPU_SLEEP>;
 128                                 i-cache-size = <0xc000>;
 129                                 i-cache-line-size = <64>;
 130                                 i-cache-sets = <256>;
 131                                 d-cache-size = <0x8000>;
 132                                 d-cache-line-size = <64>;
 133                                 d-cache-sets = <256>;
 134                                 next-level-cache = <&cpucl_l2>;
 135                 };
 136
 137                 cpucl0_3: cpu@3 {
 138                                 device_type = "cpu";
 139                                 compatible = "arm,cortex-a72";
 140                                 reg = <0x0 0x003>;
 141                                 enable-method = "psci";
 142                                 cpu-idle-states = <&CPU_SLEEP>;
 143                                 i-cache-size = <0xc000>;
 144                                 i-cache-line-size = <64>;
 145                                 i-cache-sets = <256>;
 146                                 d-cache-size = <0x8000>;
 147                                 d-cache-line-size = <64>;
 148                                 d-cache-sets = <256>;
 149                                 next-level-cache = <&cpucl_l2>;
 150                 };
 151
 152                 /* Cluster 1 */
 153                 cpucl1_0: cpu@100 {
 154                                 device_type = "cpu";
 155                                 compatible = "arm,cortex-a72";
 156                                 reg = <0x0 0x100>;
 157                                 enable-method = "psci";
 158                                 clock-frequency = <2400000000>;
 159                                 cpu-idle-states = <&CPU_SLEEP>;
 160                                 i-cache-size = <0xc000>;
 161                                 i-cache-line-size = <64>;
 162                                 i-cache-sets = <256>;
 163                                 d-cache-size = <0x8000>;
 164                                 d-cache-line-size = <64>;
 165                                 d-cache-sets = <256>;
 166                                 next-level-cache = <&cpucl_l2>;
 167                 };
 168
 169                 cpucl1_1: cpu@101 {
 170                                 device_type = "cpu";
 171                                 compatible = "arm,cortex-a72";
 172                                 reg = <0x0 0x101>;
 173                                 enable-method = "psci";
 174                                 clock-frequency = <2400000000>;
 175                                 cpu-idle-states = <&CPU_SLEEP>;
 176                                 i-cache-size = <0xc000>;
 177                                 i-cache-line-size = <64>;
 178                                 i-cache-sets = <256>;
 179                                 d-cache-size = <0x8000>;
 180                                 d-cache-line-size = <64>;
 181                                 d-cache-sets = <256>;
 182                                 next-level-cache = <&cpucl_l2>;
 183                 };
 184
 185                 cpucl1_2: cpu@102 {
 186                                 device_type = "cpu";
 187                                 compatible = "arm,cortex-a72";
 188                                 reg = <0x0 0x102>;
 189                                 enable-method = "psci";
 190                                 clock-frequency = <2400000000>;
 191                                 cpu-idle-states = <&CPU_SLEEP>;
 192                                 i-cache-size = <0xc000>;
 193                                 i-cache-line-size = <64>;
 194                                 i-cache-sets = <256>;
 195                                 d-cache-size = <0x8000>;
 196                                 d-cache-line-size = <64>;
 197                                 d-cache-sets = <256>;
 198                                 next-level-cache = <&cpucl_l2>;
 199                 };
 200
 201                 cpucl1_3: cpu@103 {
 202                                 device_type = "cpu";
 203                                 compatible = "arm,cortex-a72";
 204                                 reg = <0x0 0x103>;
 205                                 enable-method = "psci";
 206                                 clock-frequency = <2400000000>;
 207                                 cpu-idle-states = <&CPU_SLEEP>;
 208                                 i-cache-size = <0xc000>;
 209                                 i-cache-line-size = <64>;
 210                                 i-cache-sets = <256>;
 211                                 d-cache-size = <0x8000>;
 212                                 d-cache-line-size = <64>;
 213                                 d-cache-sets = <256>;
 214                                 next-level-cache = <&cpucl_l2>;
 215                 };
 216
 217                 /* Cluster 2 */
 218                 cpucl2_0: cpu@200 {
 219                                 device_type = "cpu";
 220                                 compatible = "arm,cortex-a72";
 221                                 reg = <0x0 0x200>;
 222                                 enable-method = "psci";
 223                                 clock-frequency = <2400000000>;
 224                                 cpu-idle-states = <&CPU_SLEEP>;
 225                                 i-cache-size = <0xc000>;
 226                                 i-cache-line-size = <64>;
 227                                 i-cache-sets = <256>;
 228                                 d-cache-size = <0x8000>;
 229                                 d-cache-line-size = <64>;
 230                                 d-cache-sets = <256>;
 231                                 next-level-cache = <&cpucl_l2>;
 232                 };
 233
 234                 cpucl2_1: cpu@201 {
 235                                 device_type = "cpu";
 236                                 compatible = "arm,cortex-a72";
 237                                 reg = <0x0 0x201>;
 238                                 enable-method = "psci";
 239                                 clock-frequency = <2400000000>;
 240                                 cpu-idle-states = <&CPU_SLEEP>;
 241                                 i-cache-size = <0xc000>;
 242                                 i-cache-line-size = <64>;
 243                                 i-cache-sets = <256>;
 244                                 d-cache-size = <0x8000>;
 245                                 d-cache-line-size = <64>;
 246                                 d-cache-sets = <256>;
 247                                 next-level-cache = <&cpucl_l2>;
 248                 };
 249
 250                 cpucl2_2: cpu@202 {
 251                                 device_type = "cpu";
 252                                 compatible = "arm,cortex-a72";
 253                                 reg = <0x0 0x202>;
 254                                 enable-method = "psci";
 255                                 clock-frequency = <2400000000>;
 256                                 cpu-idle-states = <&CPU_SLEEP>;
 257                                 i-cache-size = <0xc000>;
 258                                 i-cache-line-size = <64>;
 259                                 i-cache-sets = <256>;
 260                                 d-cache-size = <0x8000>;
 261                                 d-cache-line-size = <64>;
 262                                 d-cache-sets = <256>;
 263                                 next-level-cache = <&cpucl_l2>;
 264                 };
 265
 266                 cpucl2_3: cpu@203 {
 267                                 device_type = "cpu";
 268                                 compatible = "arm,cortex-a72";
 269                                 reg = <0x0 0x203>;
 270                                 enable-method = "psci";
 271                                 clock-frequency = <2400000000>;
 272                                 cpu-idle-states = <&CPU_SLEEP>;
 273                                 i-cache-size = <0xc000>;
 274                                 i-cache-line-size = <64>;
 275                                 i-cache-sets = <256>;
 276                                 d-cache-size = <0x8000>;
 277                                 d-cache-line-size = <64>;
 278                                 d-cache-sets = <256>;
 279                                 next-level-cache = <&cpucl_l2>;
 280                 };
 281
 282                 cpucl_l2: l2-cache0 {
 283                         compatible = "cache";
 284                         cache-level = <2>;
 285                         cache-unified;
 286                         cache-size = <0x400000>;
 287                         cache-line-size = <64>;
 288                         cache-sets = <4096>;
 289                 };
 290
 291                 idle-states {
 292                         entry-method = "psci";
 293
 294                         CPU_SLEEP: cpu-sleep {
 295                                 idle-state-name = "c2";
 296                                 compatible = "arm,idle-state";
 297                                 local-timer-stop;
 298                                 arm,psci-suspend-param = <0x0010000>;
 299                                 entry-latency-us = <30>;
 300                                 exit-latency-us = <75>;
 301                                 min-residency-us = <300>;
 302                         };
 303                 };
 304         };
 305
 306         arm-pmu {
 307                 compatible = "arm,armv8-pmuv3";
 308                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
 309                              <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
 310                              <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
 311                              <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
 312                              <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
 313                              <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
 314                              <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
 315                              <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>,
 316                              <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
 317                              <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
 318                              <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
 319                              <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>;
 320                 interrupt-affinity = <&cpucl0_0>, <&cpucl0_1>, <&cpucl0_2>,
 321                                      <&cpucl0_3>, <&cpucl1_0>, <&cpucl1_1>,
 322                                      <&cpucl1_2>, <&cpucl1_3>, <&cpucl2_0>,
 323                                      <&cpucl2_1>, <&cpucl2_2>, <&cpucl2_3>;
 324         };
 325
 326         psci {
 327                 compatible = "arm,psci-1.0";
 328                 method = "smc";
 329         };
 330
 331         timer {
 332                 compatible = "arm,armv8-timer";
 333                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 334                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 335                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 336                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 337         };
 338
 339         fin_pll: clock {
 340                 compatible = "fixed-clock";
 341                 clock-output-names = "fin_pll";
 342                 #clock-cells = <0>;
 343         };
 344
 345         reserved-memory {
 346                 #address-cells = <2>;
 347                 #size-cells = <2>;
 348                 ranges;
 349
 350                 mfc_left: region@84000000 {
 351                         compatible = "shared-dma-pool";
 352                         no-map;
 353                         reg = <0 0x84000000 0 0x8000000>;
 354                 };
 355         };
 356
 357         soc: soc@0 {
 358                 compatible = "simple-bus";
 359                 #address-cells = <2>;
 360                 #size-cells = <2>;
 361                 ranges = <0x0 0x0 0x0 0x0 0x0 0x18000000>;
 362                 dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>;
 363
 364                 gic: interrupt-controller@10400000 {
 365                         compatible = "arm,gic-v3";
 366                         #interrupt-cells = <3>;
 367                         interrupt-controller;
 368                         reg = <0x0 0x10400000 0x0 0x10000>, /* GICD */
 369                               <0x0 0x10600000 0x0 0x200000>; /* GICR_RD+GICR_SGI */
 370                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 371                 };
 372
 373                 smmu_imem: iommu@10200000 {
 374                         compatible = "arm,mmu-500";
 375                         reg = <0x0 0x10200000 0x0 0x10000>;
 376                         #iommu-cells = <2>;
 377                         #global-interrupts = <7>;
 378                         interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, /* Global secure fault */
 379                                      <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */
 380                                      <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, /* Combined secure interrupt */
 381                                      <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */
 382                                      /* Performance counter interrupts */
 383                                      <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>, /* for FSYS1_0 */
 384                                      <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, /* for FSYS1_1 */
 385                                      <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, /* for IMEM_0  */
 386                                      /* Per context non-secure context interrupts, 0-3 interrupts */
 387                                      <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_0 */
 388                                      <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_1 */
 389                                      <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_2 */
 390                                      <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>; /* for CONTEXT_3 */
 391                 };
 392
 393                 smmu_isp: iommu@12100000 {
 394                         compatible = "arm,mmu-500";
 395                         reg = <0x0 0x12100000 0x0 0x10000>;
 396                         #iommu-cells = <2>;
 397                         #global-interrupts = <11>;
 398                         interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, /* Global secure fault */
 399                                      <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */
 400                                      <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, /* Combined secure interrupt */
 401                                      <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */
 402                                      /* Performance counter interrupts */
 403                                      <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_CSI   */
 404                                      <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_DP_0  */
 405                                      <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_DP_1  */
 406                                      <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_ISP_0 */
 407                                      <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_ISP_1 */
 408                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_MFC_0 */
 409                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_MFC_1 */
 410                                      /* Per context non-secure context interrupts, 0-7 interrupts */
 411                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_0 */
 412                                      <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_1 */
 413                                      <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_2 */
 414                                      <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_3 */
 415                                      <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_4 */
 416                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_5 */
 417                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_6 */
 418                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; /* for CONTEXT_7 */
 419                 };
 420
 421                 smmu_peric: iommu@14900000 {
 422                         compatible = "arm,mmu-500";
 423                         reg = <0x0 0x14900000 0x0 0x10000>;
 424                         #iommu-cells = <2>;
 425                         #global-interrupts = <5>;
 426                         interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, /* Global secure fault */
 427                                      <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */
 428                                      <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* Combined secure interrupt */
 429                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */
 430                                      /* Performance counter interrupts */
 431                                      <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, /* for PERIC */
 432                                      /* Per context non-secure context interrupts, 0-1 interrupts */
 433                                      <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_0 */
 434                                      <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; /* for CONTEXT_1 */
 435                 };
 436
 437                 smmu_fsys0: iommu@15450000 {
 438                         compatible = "arm,mmu-500";
 439                         reg = <0x0 0x15450000 0x0 0x10000>;
 440                         #iommu-cells = <2>;
 441                         #global-interrupts = <5>;
 442                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, /* Global secure fault */
 443                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */
 444                                      <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* Combined secure interrupt */
 445                                      <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */
 446                                      /* Performance counter interrupts */
 447                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, /* for FSYS0   */
 448                                      /* Per context non-secure context interrupts, 0-1 interrupts */
 449                                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_0 */
 450                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; /* for CONTEXT_1 */
 451                 };
 452
 453                 clock_imem: clock-controller@10010000 {
 454                         compatible = "tesla,fsd-clock-imem";
 455                         reg = <0x0 0x10010000 0x0 0x3000>;
 456                         #clock-cells = <1>;
 457                         clocks = <&fin_pll>,
 458                                 <&clock_cmu DOUT_CMU_IMEM_TCUCLK>,
 459                                 <&clock_cmu DOUT_CMU_IMEM_ACLK>,
 460                                 <&clock_cmu DOUT_CMU_IMEM_DMACLK>;
 461                         clock-names = "fin_pll",
 462                                 "dout_cmu_imem_tcuclk",
 463                                 "dout_cmu_imem_aclk",
 464                                 "dout_cmu_imem_dmaclk";
 465                 };
 466
 467                 clock_cmu: clock-controller@11c10000 {
 468                         compatible = "tesla,fsd-clock-cmu";
 469                         reg = <0x0 0x11c10000 0x0 0x3000>;
 470                         #clock-cells = <1>;
 471                         clocks = <&fin_pll>;
 472                         clock-names = "fin_pll";
 473                 };
 474
 475                 clock_csi: clock-controller@12610000 {
 476                         compatible = "tesla,fsd-clock-cam_csi";
 477                         reg = <0x0 0x12610000 0x0 0x3000>;
 478                         #clock-cells = <1>;
 479                         clocks = <&fin_pll>;
 480                         clock-names = "fin_pll";
 481                 };
 482
 483                 sysreg_cam: system-controller@12630000 {
 484                         compatible = "tesla,fsd-cam-sysreg", "syscon";
 485                         reg = <0x0 0x12630000 0x0 0x500>;
 486                 };
 487
 488                 clock_mfc: clock-controller@12810000 {
 489                         compatible = "tesla,fsd-clock-mfc";
 490                         reg = <0x0 0x12810000 0x0 0x3000>;
 491                         #clock-cells = <1>;
 492                         clocks = <&fin_pll>;
 493                         clock-names = "fin_pll";
 494                 };
 495
 496                 clock_peric: clock-controller@14010000 {
 497                         compatible = "tesla,fsd-clock-peric";
 498                         reg = <0x0 0x14010000 0x0 0x3000>;
 499                         #clock-cells = <1>;
 500                         clocks = <&fin_pll>,
 501                                 <&clock_cmu DOUT_CMU_PLL_SHARED0_DIV4>,
 502                                 <&clock_cmu DOUT_CMU_PERIC_SHARED1DIV36>,
 503                                 <&clock_cmu DOUT_CMU_PERIC_SHARED0DIV3_TBUCLK>,
 504                                 <&clock_cmu DOUT_CMU_PERIC_SHARED0DIV20>,
 505                                 <&clock_cmu DOUT_CMU_PERIC_SHARED1DIV4_DMACLK>;
 506                         clock-names = "fin_pll",
 507                                 "dout_cmu_pll_shared0_div4",
 508                                 "dout_cmu_peric_shared1div36",
 509                                 "dout_cmu_peric_shared0div3_tbuclk",
 510                                 "dout_cmu_peric_shared0div20",
 511                                 "dout_cmu_peric_shared1div4_dmaclk";
 512                 };
 513
 514                 sysreg_peric: system-controller@14030000 {
 515                         compatible = "tesla,fsd-peric-sysreg", "syscon";
 516                         reg = <0x0 0x14030000 0x0 0x1000>;
 517                 };
 518
 519                 clock_fsys0: clock-controller@15010000 {
 520                         compatible = "tesla,fsd-clock-fsys0";
 521                         reg = <0x0 0x15010000 0x0 0x3000>;
 522                         #clock-cells = <1>;
 523                         clocks = <&fin_pll>,
 524                                 <&clock_cmu DOUT_CMU_PLL_SHARED0_DIV6>,
 525                                 <&clock_cmu DOUT_CMU_FSYS0_SHARED1DIV4>,
 526                                 <&clock_cmu DOUT_CMU_FSYS0_SHARED0DIV4>;
 527                         clock-names = "fin_pll",
 528                                 "dout_cmu_pll_shared0_div6",
 529                                 "dout_cmu_fsys0_shared1div4",
 530                                 "dout_cmu_fsys0_shared0div4";
 531                 };
 532
 533                 sysreg_fsys0: system-controller@15030000 {
 534                         compatible = "tesla,fsd-fsys0-sysreg", "syscon";
 535                         reg = <0x0 0x15030000 0x0 0x1000>;
 536                 };
 537
 538                 clock_fsys1: clock-controller@16810000 {
 539                         compatible = "tesla,fsd-clock-fsys1";
 540                         reg = <0x0 0x16810000 0x0 0x3000>;
 541                         #clock-cells = <1>;
 542                         clocks = <&fin_pll>,
 543                                 <&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV8>,
 544                                 <&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV4>;
 545                         clock-names = "fin_pll",
 546                                 "dout_cmu_fsys1_shared0div8",
 547                                 "dout_cmu_fsys1_shared0div4";
 548                 };
 549
 550                 sysreg_fsys1: system-controller@16830000 {
 551                         compatible = "tesla,fsd-fsys1-sysreg", "syscon";
 552                         reg = <0x0 0x16830000 0x0 0x1000>;
 553                 };
 554
 555                 mdma0: dma-controller@10100000 {
 556                         compatible = "arm,pl330", "arm,primecell";
 557                         reg = <0x0 0x10100000 0x0 0x1000>;
 558                         interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
 559                         #dma-cells = <1>;
 560                         clocks = <&clock_imem IMEM_DMA0_IPCLKPORT_ACLK>;
 561                         clock-names = "apb_pclk";
 562                         iommus = <&smmu_imem 0x800 0x0>;
 563                 };
 564
 565                 mdma1: dma-controller@10110000 {
 566                         compatible = "arm,pl330", "arm,primecell";
 567                         reg = <0x0 0x10110000 0x0 0x1000>;
 568                         interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
 569                         #dma-cells = <1>;
 570                         clocks = <&clock_imem IMEM_DMA1_IPCLKPORT_ACLK>;
 571                         clock-names = "apb_pclk";
 572                         iommus = <&smmu_imem 0x801 0x0>;
 573                 };
 574
 575                 pdma0: dma-controller@14280000 {
 576                         compatible = "arm,pl330", "arm,primecell";
 577                         reg = <0x0 0x14280000 0x0 0x1000>;
 578                         interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
 579                         #dma-cells = <1>;
 580                         clocks = <&clock_peric PERIC_DMA0_IPCLKPORT_ACLK>;
 581                         clock-names = "apb_pclk";
 582                         iommus = <&smmu_peric 0x2 0x0>;
 583                 };
 584
 585                 pdma1: dma-controller@14290000 {
 586                         compatible = "arm,pl330", "arm,primecell";
 587                         reg = <0x0 0x14290000 0x0 0x1000>;
 588                         interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
 589                         #dma-cells = <1>;
 590                         clocks = <&clock_peric PERIC_DMA1_IPCLKPORT_ACLK>;
 591                         clock-names = "apb_pclk";
 592                         iommus = <&smmu_peric 0x1 0x0>;
 593                 };
 594
 595                 serial_0: serial@14180000 {
 596                         compatible = "tesla,fsd-uart", "samsung,exynos4210-uart";
 597                         reg = <0x0 0x14180000 0x0 0x100>;
 598                         interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
 599                         dmas = <&pdma1 1>, <&pdma1 0>;
 600                         dma-names = "rx", "tx";
 601                         clocks = <&clock_peric PERIC_PCLK_UART0>,
 602                                  <&clock_peric PERIC_SCLK_UART0>;
 603                         clock-names = "uart", "clk_uart_baud0";
 604                         samsung,uart-fifosize = <64>;
 605                         status = "disabled";
 606                 };
 607
 608                 serial_1: serial@14190000 {
 609                         compatible = "tesla,fsd-uart", "samsung,exynos4210-uart";
 610                         reg = <0x0 0x14190000 0x0 0x100>;
 611                         interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
 612                         dmas = <&pdma1 3>, <&pdma1 2>;
 613                         dma-names = "rx", "tx";
 614                         clocks = <&clock_peric PERIC_PCLK_UART1>,
 615                                  <&clock_peric PERIC_SCLK_UART1>;
 616                         clock-names = "uart", "clk_uart_baud0";
 617                         samsung,uart-fifosize = <64>;
 618                         status = "disabled";
 619                 };
 620
 621                 pmu_system_controller: system-controller@11400000 {
 622                         compatible = "tesla,fsd-pmu", "samsung,exynos7-pmu", "syscon";
 623                         reg = <0x0 0x11400000 0x0 0x5000>;
 624                 };
 625
 626                 watchdog_0: watchdog@100a0000 {
 627                         compatible = "tesla,fsd-wdt", "samsung,exynos7-wdt";
 628                         reg = <0x0 0x100a0000 0x0 0x100>;
 629                         interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>;
 630                         samsung,syscon-phandle = <&pmu_system_controller>;
 631                         clocks = <&fin_pll>;
 632                         clock-names = "watchdog";
 633                 };
 634
 635                 watchdog_1: watchdog@100b0000 {
 636                         compatible = "tesla,fsd-wdt", "samsung,exynos7-wdt";
 637                         reg = <0x0 0x100b0000 0x0 0x100>;
 638                         interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>;
 639                         samsung,syscon-phandle = <&pmu_system_controller>;
 640                         clocks = <&fin_pll>;
 641                         clock-names = "watchdog";
 642                 };
 643
 644                 watchdog_2: watchdog@100c0000 {
 645                         compatible = "tesla,fsd-wdt", "samsung,exynos7-wdt";
 646                         reg = <0x0 0x100c0000 0x0 0x100>;
 647                         interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
 648                         samsung,syscon-phandle = <&pmu_system_controller>;
 649                         clocks = <&fin_pll>;
 650                         clock-names = "watchdog";
 651                 };
 652
 653                 pwm_0: pwm@14100000 {
 654                         compatible = "tesla,fsd-pwm", "samsung,exynos4210-pwm";
 655                         reg = <0x0 0x14100000 0x0 0x100>;
 656                         samsung,pwm-outputs = <0>, <1>, <2>, <3>;
 657                         #pwm-cells = <3>;
 658                         clocks = <&clock_peric PERIC_PWM0_IPCLKPORT_I_PCLK_S0>;
 659                         clock-names = "timers";
 660                         status = "disabled";
 661                 };
 662
 663                 pwm_1: pwm@14110000 {
 664                         compatible = "tesla,fsd-pwm", "samsung,exynos4210-pwm";
 665                         reg = <0x0 0x14110000 0x0 0x100>;
 666                         samsung,pwm-outputs = <0>, <1>, <2>, <3>;
 667                         #pwm-cells = <3>;
 668                         clocks = <&clock_peric PERIC_PWM1_IPCLKPORT_I_PCLK_S0>;
 669                         clock-names = "timers";
 670                         status = "disabled";
 671                 };
 672
 673                 hsi2c_0: i2c@14200000 {
 674                         compatible = "tesla,fsd-hsi2c", "samsung,exynos7-hsi2c";
 675                         reg = <0x0 0x14200000 0x0 0x1000>;
 676                         interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
 677                         #address-cells = <1>;
 678                         #size-cells = <0>;
 679                         pinctrl-names = "default";
 680                         pinctrl-0 = <&hs_i2c0_bus>;
 681                         clocks = <&clock_peric PERIC_PCLK_HSI2C0>;
 682                         clock-names = "hsi2c";
 683                         status = "disabled";
 684                 };
 685
 686                 hsi2c_1: i2c@14210000 {
 687                         compatible = "tesla,fsd-hsi2c", "samsung,exynos7-hsi2c";
 688                         reg = <0x0 0x14210000 0x0 0x1000>;
 689                         interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 690                         #address-cells = <1>;
 691                         #size-cells = <0>;
 692                         pinctrl-names = "default";
 693                         pinctrl-0 = <&hs_i2c1_bus>;
 694                         clocks = <&clock_peric PERIC_PCLK_HSI2C1>;
 695                         clock-names = "hsi2c";
 696                         status = "disabled";
 697                 };
 698
 699                 hsi2c_2: i2c@14220000 {
 700                         compatible = "tesla,fsd-hsi2c", "samsung,exynos7-hsi2c";
 701                         reg = <0x0 0x14220000 0x0 0x1000>;
 702                         interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
 703                         #address-cells = <1>;
 704                         #size-cells = <0>;
 705                         pinctrl-names = "default";
 706                         pinctrl-0 = <&hs_i2c2_bus>;
 707                         clocks = <&clock_peric PERIC_PCLK_HSI2C2>;
 708                         clock-names = "hsi2c";
 709                         status = "disabled";
 710                 };
 711
 712                 hsi2c_3: i2c@14230000 {
 713                         compatible = "tesla,fsd-hsi2c", "samsung,exynos7-hsi2c";
 714                         reg = <0x0 0x14230000 0x0 0x1000>;
 715                         interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
 716                         #address-cells = <1>;
 717                         #size-cells = <0>;
 718                         pinctrl-names = "default";
 719                         pinctrl-0 = <&hs_i2c3_bus>;
 720                         clocks = <&clock_peric PERIC_PCLK_HSI2C3>;
 721                         clock-names = "hsi2c";
 722                         status = "disabled";
 723                 };
 724
 725                 hsi2c_4: i2c@14240000 {
 726                         compatible = "tesla,fsd-hsi2c", "samsung,exynos7-hsi2c";
 727                         reg = <0x0 0x14240000 0x0 0x1000>;
 728                         interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 729                         #address-cells = <1>;
 730                         #size-cells = <0>;
 731                         pinctrl-names = "default";
 732                         pinctrl-0 = <&hs_i2c4_bus>;
 733                         clocks = <&clock_peric PERIC_PCLK_HSI2C4>;
 734                         clock-names = "hsi2c";
 735                         status = "disabled";
 736                 };
 737
 738                 hsi2c_5: i2c@14250000 {
 739                         compatible = "tesla,fsd-hsi2c", "samsung,exynos7-hsi2c";
 740                         reg = <0x0 0x14250000 0x0 0x1000>;
 741                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 742                         #address-cells = <1>;
 743                         #size-cells = <0>;
 744                         pinctrl-names = "default";
 745                         pinctrl-0 = <&hs_i2c5_bus>;
 746                         clocks = <&clock_peric PERIC_PCLK_HSI2C5>;
 747                         clock-names = "hsi2c";
 748                         status = "disabled";
 749                 };
 750
 751                 hsi2c_6: i2c@14260000 {
 752                         compatible = "tesla,fsd-hsi2c", "samsung,exynos7-hsi2c";
 753                         reg = <0x0 0x14260000 0x0 0x1000>;
 754                         interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 755                         #address-cells = <1>;
 756                         #size-cells = <0>;
 757                         pinctrl-names = "default";
 758                         pinctrl-0 = <&hs_i2c6_bus>;
 759                         clocks = <&clock_peric PERIC_PCLK_HSI2C6>;
 760                         clock-names = "hsi2c";
 761                         status = "disabled";
 762                 };
 763
 764                 hsi2c_7: i2c@14270000 {
 765                         compatible = "tesla,fsd-hsi2c", "samsung,exynos7-hsi2c";
 766                         reg = <0x0 0x14270000 0x0 0x1000>;
 767                         interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 768                         #address-cells = <1>;
 769                         #size-cells = <0>;
 770                         pinctrl-names = "default";
 771                         pinctrl-0 = <&hs_i2c7_bus>;
 772                         clocks = <&clock_peric PERIC_PCLK_HSI2C7>;
 773                         clock-names = "hsi2c";
 774                         status = "disabled";
 775                 };
 776
 777                 i2s_0: i2s@140e0000 {
 778                         compatible = "tesla,fsd-i2s";
 779                         reg = <0x0 0x140e0000 0x0 0x100>;
 780                         interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
 781                         dmas = <&pdma1 14>, <&pdma1 13>, <&pdma1 12>;
 782                         dma-names = "tx", "rx", "tx-sec";
 783                         #clock-cells = <1>;
 784                         clocks = <&clock_peric PERIC_PCLK_TDM0>,
 785                                  <&clock_peric PERIC_HCLK_TDM0>,
 786                                  <&clock_peric PERIC_HCLK_TDM0>;
 787                         clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
 788                         pinctrl-names = "default";
 789                         pinctrl-0 = <&i2s0_bus>;
 790                         #sound-dai-cells = <1>;
 791                         status = "disabled";
 792                 };
 793
 794                 i2s_1: i2s@140f0000 {
 795                         compatible = "tesla,fsd-i2s";
 796                         reg = <0x0 0x140f0000 0x0 0x100>;
 797                         interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
 798                         dmas = <&pdma1 17>, <&pdma1 16>, <&pdma1 15>;
 799                         dma-names = "tx", "rx", "tx-sec";
 800                         #clock-cells = <1>;
 801                         clocks = <&clock_peric PERIC_PCLK_TDM1>,
 802                                  <&clock_peric PERIC_HCLK_TDM1>,
 803                                  <&clock_peric PERIC_HCLK_TDM1>;
 804                         clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
 805                         pinctrl-names = "default";
 806                         pinctrl-0 = <&i2s1_bus>;
 807                         #sound-dai-cells = <1>;
 808                         status = "disabled";
 809                 };
 810
 811                 pinctrl_pmu: pinctrl@114f0000 {
 812                         compatible = "tesla,fsd-pinctrl";
 813                         reg = <0x0 0x114f0000 0x0 0x1000>;
 814                 };
 815
 816                 pinctrl_peric: pinctrl@141f0000 {
 817                         compatible = "tesla,fsd-pinctrl";
 818                         reg = <0x0 0x141f0000 0x0 0x1000>;
 819                         interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
 820                 };
 821
 822                 pinctrl_fsys0: pinctrl@15020000 {
 823                         compatible = "tesla,fsd-pinctrl";
 824                         reg = <0x0 0x15020000 0x0 0x1000>;
 825                         interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 826                 };
 827
 828                 m_can0: can@14088000 {
 829                         compatible = "bosch,m_can";
 830                         reg = <0x0 0x14088000 0x0 0x0200>,
 831                               <0x0 0x14080000 0x0 0x8000>;
 832                         reg-names = "m_can", "message_ram";
 833                         interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
 834                                      <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
 835                         interrupt-names = "int0", "int1";
 836                         pinctrl-names = "default";
 837                         pinctrl-0 = <&m_can0_bus>;
 838                         clocks = <&clock_peric PERIC_MCAN0_IPCLKPORT_PCLK>,
 839                                  <&clock_peric PERIC_MCAN0_IPCLKPORT_CCLK>;
 840                         clock-names = "hclk", "cclk";
 841                         bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
 842                         status = "disabled";
 843                 };
 844
 845                 m_can1: can@14098000 {
 846                         compatible = "bosch,m_can";
 847                         reg = <0x0 0x14098000 0x0 0x0200>,
 848                               <0x0 0x14090000 0x0 0x8000>;
 849                         reg-names = "m_can", "message_ram";
 850                         interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
 851                                      <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
 852                         interrupt-names = "int0", "int1";
 853                         pinctrl-names = "default";
 854                         pinctrl-0 = <&m_can1_bus>;
 855                         clocks = <&clock_peric PERIC_MCAN1_IPCLKPORT_PCLK>,
 856                                  <&clock_peric PERIC_MCAN1_IPCLKPORT_CCLK>;
 857                         clock-names = "hclk", "cclk";
 858                         bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
 859                         status = "disabled";
 860                 };
 861
 862                 m_can2: can@140a8000 {
 863                         compatible = "bosch,m_can";
 864                         reg = <0x0 0x140a8000 0x0 0x0200>,
 865                               <0x0 0x140a0000 0x0 0x8000>;
 866                         reg-names = "m_can", "message_ram";
 867                         interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
 868                                      <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
 869                         interrupt-names = "int0", "int1";
 870                         pinctrl-names = "default";
 871                         pinctrl-0 = <&m_can2_bus>;
 872                         clocks = <&clock_peric PERIC_MCAN2_IPCLKPORT_PCLK>,
 873                                  <&clock_peric PERIC_MCAN2_IPCLKPORT_CCLK>;
 874                         clock-names = "hclk", "cclk";
 875                         bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
 876                         status = "disabled";
 877                 };
 878
 879                 m_can3: can@140b8000 {
 880                         compatible = "bosch,m_can";
 881                         reg = <0x0 0x140b8000 0x0 0x0200>,
 882                               <0x0 0x140b0000 0x0 0x8000>;
 883                         reg-names = "m_can", "message_ram";
 884                         interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
 885                                      <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
 886                         interrupt-names = "int0", "int1";
 887                         pinctrl-names = "default";
 888                         pinctrl-0 = <&m_can3_bus>;
 889                         clocks = <&clock_peric PERIC_MCAN3_IPCLKPORT_PCLK>,
 890                                  <&clock_peric PERIC_MCAN3_IPCLKPORT_CCLK>;
 891                         clock-names = "hclk", "cclk";
 892                         bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
 893                         status = "disabled";
 894                 };
 895
 896                 spi_0: spi@14140000 {
 897                         compatible = "tesla,fsd-spi";
 898                         reg = <0x0 0x14140000 0x0 0x100>;
 899                         interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
 900                         dmas = <&pdma1 4>, <&pdma1 5>;
 901                         dma-names = "tx", "rx";
 902                         #address-cells = <1>;
 903                         #size-cells = <0>;
 904                         clocks = <&clock_peric PERIC_PCLK_SPI0>,
 905                                 <&clock_peric PERIC_SCLK_SPI0>;
 906                         clock-names = "spi", "spi_busclk0";
 907                         samsung,spi-src-clk = <0>;
 908                         pinctrl-names = "default";
 909                         pinctrl-0 = <&spi0_bus>;
 910                         num-cs = <1>;
 911                         status = "disabled";
 912                 };
 913
 914                 spi_1: spi@14150000 {
 915                         compatible = "tesla,fsd-spi";
 916                         reg = <0x0 0x14150000 0x0 0x100>;
 917                         interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
 918                         dmas = <&pdma1 6>, <&pdma1 7>;
 919                         dma-names = "tx", "rx";
 920                         #address-cells = <1>;
 921                         #size-cells = <0>;
 922                         clocks = <&clock_peric PERIC_PCLK_SPI1>,
 923                                 <&clock_peric PERIC_SCLK_SPI1>;
 924                         clock-names = "spi", "spi_busclk0";
 925                         samsung,spi-src-clk = <0>;
 926                         pinctrl-names = "default";
 927                         pinctrl-0 = <&spi1_bus>;
 928                         num-cs = <1>;
 929                         status = "disabled";
 930                 };
 931
 932                 spi_2: spi@14160000 {
 933                         compatible = "tesla,fsd-spi";
 934                         reg = <0x0 0x14160000 0x0 0x100>;
 935                         interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
 936                         dmas = <&pdma1 8>, <&pdma1 9>;
 937                         dma-names = "tx", "rx";
 938                         #address-cells = <1>;
 939                         #size-cells = <0>;
 940                         clocks = <&clock_peric PERIC_PCLK_SPI2>,
 941                                 <&clock_peric PERIC_SCLK_SPI2>;
 942                         clock-names = "spi", "spi_busclk0";
 943                         samsung,spi-src-clk = <0>;
 944                         pinctrl-names = "default";
 945                         pinctrl-0 = <&spi2_bus>;
 946                         num-cs = <1>;
 947                         status = "disabled";
 948                 };
 949
 950                 timer@10040000 {
 951                         compatible = "tesla,fsd-mct", "samsung,exynos4210-mct";
 952                         reg = <0x0 0x10040000 0x0 0x800>;
 953                         interrupts = <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
 954                                 <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
 955                                 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
 956                                 <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
 957                                 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
 958                                 <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
 959                                 <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
 960                                 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
 961                                 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
 962                                 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
 963                                 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
 964                                 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
 965                                 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
 966                                 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
 967                                 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
 968                                 <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>;
 969                         clocks = <&fin_pll>, <&clock_imem IMEM_MCT_PCLK>;
 970                         clock-names = "fin_pll", "mct";
 971                 };
 972
 973                 mfc: mfc@12880000 {
 974                         compatible = "tesla,fsd-mfc";
 975                         reg = <0x0 0x12880000 0x0 0x10000>;
 976                         interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
 977                         clock-names = "mfc";
 978                         clocks = <&clock_mfc MFC_MFC_IPCLKPORT_ACLK>;
 979                         memory-region = <&mfc_left>;
 980                 };
 981
 982                 ufs: ufs@15120000 {
 983                         compatible = "tesla,fsd-ufs";
 984                         reg = <0x0 0x15120000 0x0 0x200>,  /* 0: HCI standard */
 985                               <0x0 0x15121100 0x0 0x200>,  /* 1: Vendor specified */
 986                               <0x0 0x15110000 0x0 0x8000>,  /* 2: UNIPRO */
 987                               <0x0 0x15130000 0x0 0x100>;  /* 3: UFS protector */
 988                         reg-names = "hci", "vs_hci", "unipro", "ufsp";
 989                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 990                         clocks = <&clock_fsys0 UFS0_TOP0_HCLK_BUS>,
 991                                  <&clock_fsys0 UFS0_TOP0_CLK_UNIPRO>;
 992                         clock-names = "core_clk", "sclk_unipro_main";
 993                         freq-table-hz = <0 0>, <0 0>;
 994                         pinctrl-names = "default";
 995                         pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
 996                         phys = <&ufs_phy>;
 997                         phy-names = "ufs-phy";
 998                         status = "disabled";
 999                 };
1000
1001                 ufs_phy: ufs-phy@15124000 {
1002                         compatible = "tesla,fsd-ufs-phy";
1003                         reg = <0x0 0x15124000 0x0 0x800>;
1004                         reg-names = "phy-pma";
1005                         samsung,pmu-syscon = <&pmu_system_controller>;
1006                         #phy-cells = <0>;
1007                         clocks = <&clock_fsys0 UFS0_MPHY_REFCLK_IXTAL26>;
1008                         clock-names = "ref_clk";
1009                 };
1010         };
1011 };
1012
1013 #include "fsd-pinctrl.dtsi"