1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2015 Freescale Semiconductor, Inc.
9 #include <asm/arch/clock.h>
10 #include <asm/arch/fsl_serdes.h>
11 #include <asm/arch/soc.h>
12 #include <fdt_support.h>
18 #include <fsl_esdhc.h>
25 #include <asm/arch/ppa.h>
27 DECLARE_GLOBAL_DATA_PTR;
29 int board_early_init_f(void)
31 fsl_lsch2_early_init_f();
36 #ifndef CONFIG_SPL_BUILD
40 static const char *freq[2] = {"100.00MHZ", "156.25MHZ"};
41 #ifndef CONFIG_SD_BOOT
42 u8 cfg_rcw_src1, cfg_rcw_src2;
47 printf("Board: LS1043ARDB, boot from ");
52 cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1);
53 cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2);
54 cpld_rev_bit(&cfg_rcw_src1);
55 cfg_rcw_src = cfg_rcw_src1;
56 cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2;
58 if (cfg_rcw_src == 0x25)
59 printf("vBank %d\n", CPLD_READ(vbank));
60 else if (cfg_rcw_src == 0x106)
63 printf("Invalid setting of SW4\n");
66 printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver),
67 CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver));
69 puts("SERDES Reference Clocks:\n");
70 sd1refclk_sel = CPLD_READ(sd1refclk_sel);
71 printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]);
78 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
80 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
85 init_final_memctl_regs();
88 #ifdef CONFIG_SECURE_BOOT
89 /* In case of Secure Boot, the IBR configures the SMMU
90 * to allow only Secure transactions.
91 * SMMU must be reset in bypass mode.
92 * Set the ClientPD bit and Clear the USFCFG Bit
95 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
96 out_le32(SMMU_SCR0, val);
97 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
98 out_le32(SMMU_NSCR0, val);
101 #ifdef CONFIG_FSL_CAAM
105 #ifdef CONFIG_FSL_LS_PPA
112 /* invert AQR105 IRQ pins polarity */
113 out_be32(&scfg->intpcr, AQR105_IRQ_MASK);
118 int config_board_mux(void)
120 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
123 if (hwconfig("qe-hdlc")) {
124 out_be32(&scfg->rcwpmuxcr0,
125 (in_be32(&scfg->rcwpmuxcr0) & ~0xff00) | 0x6600);
126 printf("Assign to qe-hdlc clk, rcwpmuxcr0=%x\n",
127 in_be32(&scfg->rcwpmuxcr0));
129 #ifdef CONFIG_HAS_FSL_XHCI_USB
130 out_be32(&scfg->rcwpmuxcr0, 0x3333);
131 out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
132 usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
133 SCFG_USBPWRFAULT_USB3_SHIFT) |
134 (SCFG_USBPWRFAULT_DEDICATED <<
135 SCFG_USBPWRFAULT_USB2_SHIFT) |
136 (SCFG_USBPWRFAULT_SHARED <<
137 SCFG_USBPWRFAULT_USB1_SHIFT);
138 out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
144 #if defined(CONFIG_MISC_INIT_R)
145 int misc_init_r(void)
152 void fdt_del_qe(void *blob)
156 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
158 fdt_del_node(blob, nodeoff);
162 int ft_board_setup(void *blob, bd_t *bd)
164 u64 base[CONFIG_NR_DRAM_BANKS];
165 u64 size[CONFIG_NR_DRAM_BANKS];
167 /* fixup DT for the two DDR banks */
168 base[0] = gd->bd->bi_dram[0].start;
169 size[0] = gd->bd->bi_dram[0].size;
170 base[1] = gd->bd->bi_dram[1].start;
171 size[1] = gd->bd->bi_dram[1].size;
173 fdt_fixup_memory_banks(blob, base, size, 2);
174 ft_cpu_setup(blob, bd);
176 #ifdef CONFIG_SYS_DPAA_FMAN
177 fdt_fixup_fman_ethernet(blob);
181 * qe-hdlc and usb multi-use the pins,
182 * when set hwconfig to qe-hdlc, delete usb node.
184 if (hwconfig("qe-hdlc"))
185 #ifdef CONFIG_HAS_FSL_XHCI_USB
186 fdt_del_node_and_alias(blob, "usb1");
189 * qe just support qe-uart and qe-hdlc,
190 * if qe-uart and qe-hdlc are not set in hwconfig,
193 if (!hwconfig("qe-uart") && !hwconfig("qe-hdlc"))
199 u8 flash_read8(void *addr)
201 return __raw_readb(addr + 1);
204 void flash_write16(u16 val, void *addr)
206 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
208 __raw_writew(shftval, addr);
211 u16 flash_read16(void *addr)
213 u16 val = __raw_readw(addr);
215 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);