board/cavium/thunderx/thunderx.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /**
   3  * (C) Copyright 2014, Cavium Inc.
   4 **/
   5
   6 #include <common.h>
   7 #include <dm.h>
   8 #include <malloc.h>
   9 #include <errno.h>
  10 #include <linux/compiler.h>
  11
  12 #include <cavium/atf.h>
  13 #include <asm/armv8/mmu.h>
  14
  15 #if !CONFIG_IS_ENABLED(OF_CONTROL)
  16 #include <dm/platform_data/serial_pl01x.h>
  17
  18 static const struct pl01x_serial_platdata serial0 = {
  19         .base = CONFIG_SYS_SERIAL0,
  20         .type = TYPE_PL011,
  21         .clock = 0,
  22         .skip_init = true,
  23 };
  24
  25 U_BOOT_DEVICE(thunderx_serial0) = {
  26         .name = "serial_pl01x",
  27         .platdata = &serial0,
  28 };
  29
  30 static const struct pl01x_serial_platdata serial1 = {
  31         .base = CONFIG_SYS_SERIAL1,
  32         .type = TYPE_PL011,
  33         .clock = 0,
  34         .skip_init = true,
  35 };
  36
  37 U_BOOT_DEVICE(thunderx_serial1) = {
  38         .name = "serial_pl01x",
  39         .platdata = &serial1,
  40 };
  41 #endif
  42
  43 DECLARE_GLOBAL_DATA_PTR;
  44
  45 static struct mm_region thunderx_mem_map[] = {
  46         {
  47                 .virt = 0x000000000000UL,
  48                 .phys = 0x000000000000UL,
  49                 .size = 0x40000000000UL,
  50                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE,
  51         }, {
  52                 .virt = 0x800000000000UL,
  53                 .phys = 0x800000000000UL,
  54                 .size = 0x40000000000UL,
  55                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  56                          PTE_BLOCK_NON_SHARE,
  57         }, {
  58                 .virt = 0x840000000000UL,
  59                 .phys = 0x840000000000UL,
  60                 .size = 0x40000000000UL,
  61                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  62                          PTE_BLOCK_NON_SHARE,
  63         }, {
  64                 /* List terminator */
  65                 0,
  66         }
  67 };
  68
  69 struct mm_region *mem_map = thunderx_mem_map;
  70
  71 int board_init(void)
  72 {
  73         return 0;
  74 }
  75
  76 int timer_init(void)
  77 {
  78         return 0;
  79 }
  80
  81 int dram_init(void)
  82 {
  83         ssize_t node_count = atf_node_count();
  84         ssize_t dram_size;
  85         int node;
  86
  87         printf("Initializing\nNodes in system: %zd\n", node_count);
  88
  89         gd->ram_size = 0;
  90
  91         for (node = 0; node < node_count; node++) {
  92                 dram_size = atf_dram_size(node);
  93                 printf("Node %d: %zd MBytes of DRAM\n", node, dram_size >> 20);
  94                 gd->ram_size += dram_size;
  95         }
  96
  97         gd->ram_size -= MEM_BASE;
  98
  99         *(unsigned long *)CPU_RELEASE_ADDR = 0;
 100
 101         puts("DRAM size:");
 102
 103         return 0;
 104 }
 105
 106 /*
 107  * Board specific reset that is system reset.
 108  */
 109 void reset_cpu(ulong addr)
 110 {
 111 }
 112
 113 /*
 114  * Board specific ethernet initialization routine.
 115  */
 116 int board_eth_init(bd_t *bis)
 117 {
 118         int rc = 0;
 119
 120         return rc;
 121 }
 122
 123 #ifdef CONFIG_PCI
 124 void pci_init_board(void)
 125 {
 126         printf("DEBUG: PCI Init TODO *****\n");
 127 }
 128 #endif