include/configs/M5208EVBE.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Configuation settings for the Freescale MCF5208EVBe.
   4  *
   5  * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
   6  * TsiChung Liew ([email protected])
   7  */
   8
   9 #ifndef _M5208EVBE_H
  10 #define _M5208EVBE_H
  11
  12 /*
  13  * High Level Configuration Options
  14  * (easy to change)
  15  */
  16 #define CONFIG_SYS_UART_PORT            (0)
  17
  18 #define CONFIG_WATCHDOG_TIMEOUT         5000
  19
  20 #ifdef CONFIG_MCFFEC
  21 #       define CONFIG_SYS_DISCOVER_PHY
  22 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  23 #       ifndef CONFIG_SYS_DISCOVER_PHY
  24 #               define FECDUPLEX        FULL
  25 #               define FECSPEED         _100BASET
  26 #       endif                   /* CONFIG_SYS_DISCOVER_PHY */
  27 #endif
  28
  29 /* I2C */
  30
  31 #ifdef CONFIG_MCFFEC
  32 #       define CONFIG_IPADDR    192.162.1.2
  33 #       define CONFIG_NETMASK   255.255.255.0
  34 #       define CONFIG_SERVERIP  192.162.1.1
  35 #       define CONFIG_GATEWAYIP 192.162.1.1
  36 #endif                          /* CONFIG_MCFFEC */
  37
  38 #define CONFIG_HOSTNAME         "M5208EVBe"
  39 #define CONFIG_EXTRA_ENV_SETTINGS               \
  40         "netdev=eth0\0"                         \
  41         "loadaddr=40010000\0"                   \
  42         "u-boot=u-boot.bin\0"                   \
  43         "load=tftp ${loadaddr) ${u-boot}\0"     \
  44         "upd=run load; run prog\0"              \
  45         "prog=prot off 0 3ffff;"                \
  46         "era 0 3ffff;"                          \
  47         "cp.b ${loadaddr} 0 ${filesize};"       \
  48         "save\0"                                \
  49         ""
  50
  51 #define CONFIG_PRAM             512     /* 512 KB */
  52
  53 #define CONFIG_SYS_CLK          166666666       /* CPU Core Clock */
  54 #define CONFIG_SYS_PLL_ODR      0x36
  55 #define CONFIG_SYS_PLL_FDR      0x7D
  56
  57 #define CONFIG_SYS_MBAR         0xFC000000
  58
  59 /*
  60  * Low Level Configuration Settings
  61  * (address mappings, register initial values, etc.)
  62  * You should know what you are doing if you make changes here.
  63  */
  64 /* Definitions for initial stack pointer and data area (in DPRAM) */
  65 #define CONFIG_SYS_INIT_RAM_ADDR        0x80000000
  66 #define CONFIG_SYS_INIT_RAM_SIZE                0x4000  /* Size of used area in internal SRAM */
  67 #define CONFIG_SYS_INIT_RAM_CTRL        0x221
  68 #define CONFIG_SYS_GBL_DATA_OFFSET      ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
  69 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
  70
  71 /*
  72  * Start addresses for the final memory configuration
  73  * (Set up by the startup code)
  74  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  75  */
  76 #define CONFIG_SYS_SDRAM_BASE           0x40000000
  77 #define CONFIG_SYS_SDRAM_SIZE           32      /* SDRAM size in MB */
  78 #define CONFIG_SYS_SDRAM_CFG1           0x43711630
  79 #define CONFIG_SYS_SDRAM_CFG2           0x56670000
  80 #define CONFIG_SYS_SDRAM_CTRL           0xE1002000
  81 #define CONFIG_SYS_SDRAM_EMOD           0x80010000
  82 #define CONFIG_SYS_SDRAM_MODE           0x00CD0000
  83
  84 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
  85
  86 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
  87
  88 /*
  89  * For booting Linux, the board info and command line data
  90  * have to be in the first 8 MB of memory, since this is
  91  * the maximum mapped by the Linux kernel during initialization ??
  92  */
  93 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
  94 #define CONFIG_SYS_BOOTM_LEN            (CONFIG_SYS_SDRAM_SIZE << 20)
  95
  96 /* FLASH organization */
  97 #ifdef CONFIG_SYS_FLASH_CFI
  98 #       define CONFIG_SYS_FLASH_SIZE            0x800000        /* Max size that the board might have */
  99 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_16BIT
 100 #       define CONFIG_SYS_MAX_FLASH_SECT        254     /* max number of sectors on one chip */
 101 #endif
 102
 103 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
 104
 105 /*
 106  * Configuration for environment
 107  * Environment is embedded in u-boot in the second sector of the flash
 108  */
 109
 110 #define LDS_BOARD_TEXT \
 111         . = DEFINED(env_offset) ? env_offset : .; \
 112         env/embedded.o(.text*);
 113
 114 /* Cache Configuration */
 115
 116 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 117                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 118 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 119                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 120 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINV | CF_CACR_INVI)
 121 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 122                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 123                                          CF_ACR_EN | CF_ACR_SM_ALL)
 124 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_CINV | \
 125                                          CF_CACR_DISD | CF_CACR_INVI | \
 126                                          CF_CACR_CEIB | CF_CACR_DCM | \
 127                                          CF_CACR_EUSP)
 128
 129 /* Chipselect bank definitions */
 130 /*
 131  * CS0 - NOR Flash
 132  * CS1 - Available
 133  * CS2 - Available
 134  * CS3 - Available
 135  * CS4 - Available
 136  * CS5 - Available
 137  */
 138 #define CONFIG_SYS_CS0_BASE             0
 139 #define CONFIG_SYS_CS0_MASK             0x007F0001
 140 #define CONFIG_SYS_CS0_CTRL             0x00001FA0
 141
 142 #endif                          /* _M5208EVBE_H */