1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2012 Altera Corporation <www.altera.com>
5 #ifndef __CONFIG_SOCFPGA_COMMON_H__
6 #define __CONFIG_SOCFPGA_COMMON_H__
8 #include <linux/stringify.h>
11 * High level configuration
15 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
18 * Memory configurations
20 #define PHYS_SDRAM_1 0x0
21 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
22 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
23 #define CONFIG_SYS_INIT_RAM_SIZE SOCFPGA_PHYS_OCRAM_SIZE
24 #define CONFIG_SPL_PAD_TO 0x10000
25 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
26 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000
27 #define CONFIG_SPL_PAD_TO 0x40000
28 /* SPL memory allocation configuration, this is for FAT implementation */
29 #ifndef CONFIG_SYS_SPL_MALLOC_SIZE
30 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x10000
32 #define CONFIG_SYS_INIT_RAM_SIZE (SOCFPGA_PHYS_OCRAM_SIZE - \
33 CONFIG_SYS_SPL_MALLOC_SIZE)
34 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_ADDR + \
35 CONFIG_SYS_INIT_RAM_SIZE)
39 * Some boards (e.g. socfpga_sr1500) use 8 bytes at the end of the internal
40 * SRAM as bootcounter storage. Make sure to not put the stack directly
41 * at this address to not overwrite the bootcounter by checking, if the
42 * bootcounter address is located in the internal SRAM.
44 #if ((CONFIG_SYS_BOOTCOUNT_ADDR > CONFIG_SYS_INIT_RAM_ADDR) && \
45 (CONFIG_SYS_BOOTCOUNT_ADDR < (CONFIG_SYS_INIT_RAM_ADDR + \
46 CONFIG_SYS_INIT_RAM_SIZE)))
47 #define CONFIG_SPL_STACK CONFIG_SYS_BOOTCOUNT_ADDR
49 #define CONFIG_SPL_STACK \
50 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
54 * U-Boot stack setup: if SPL post-reloc uses DDR stack, use it in pre-reloc
55 * phase of U-Boot, too. This prevents overwriting SPL data if stack/heap usage
56 * in U-Boot pre-reloc is higher than in SPL.
58 #if defined(CONFIG_SPL_STACK_R_ADDR) && CONFIG_SPL_STACK_R_ADDR
59 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK_R_ADDR
61 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK
64 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
67 * U-Boot general configurations
69 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
70 /* Print buffer size */
71 #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
72 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
73 /* Boot argument buffer size */
78 #define CONFIG_SYS_L2_PL310
79 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
82 * Ethernet on SoC (EMAC)
85 #define CONFIG_DW_ALTDESCRIPTOR
91 #ifdef CONFIG_CMD_FPGA
92 #define CONFIG_FPGA_COUNT 1
99 #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
100 #define CONFIG_SYS_TIMER_COUNTS_DOWN
101 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
102 #ifndef CONFIG_SYS_TIMER_RATE
103 #define CONFIG_SYS_TIMER_RATE 25000000
110 #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
111 #define CONFIG_DW_WDT_CLOCK_KHZ 25000
116 #ifdef CONFIG_CMD_MMC
118 /* using smaller max blk cnt to avoid flooding the limited stack we have */
119 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */
125 #ifdef CONFIG_NAND_DENALI
126 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
127 #define CONFIG_SYS_MAX_NAND_DEVICE 1
128 #define CONFIG_SYS_NAND_ONFI_DETECTION
129 #define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS
130 #define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS
136 /* QSPI reference clock */
138 unsigned int cm_get_qspi_controller_clk_hz(void);
139 #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz()
147 * USB Gadget (DFU, UMS)
149 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
150 #define DFU_DEFAULT_POLL_TIMEOUT 300
153 #define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525
154 #define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5
161 /* Environment for SDMMC boot */
163 /* Environment for QSPI boot */
168 * SRAM Memory layout for gen 5:
170 * 0xFFFF_0000 ...... Start of SRAM
171 * 0xFFFF_xxxx ...... Top of stack (grows down)
172 * 0xFFFF_yyyy ...... Global Data
173 * 0xFFFF_zzzz ...... Malloc area
174 * 0xFFFF_FFFF ...... End of SRAM
176 * SRAM Memory layout for Arria 10:
177 * 0xFFE0_0000 ...... Start of SRAM (bottom)
178 * 0xFFEx_xxxx ...... Top of stack (grows down to bottom)
179 * 0xFFEy_yyyy ...... Global Data
180 * 0xFFEz_zzzz ...... Malloc area (grows up to top)
181 * 0xFFE3_FFFF ...... End of SRAM (top)
183 #ifndef CONFIG_SPL_TEXT_BASE
184 #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE
187 /* SPL SDMMC boot support */
188 #ifdef CONFIG_SPL_MMC_SUPPORT
189 #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
190 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
193 #ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
194 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1
198 /* SPL QSPI boot support */
200 /* SPL NAND boot support */
201 #ifdef CONFIG_SPL_NAND_SUPPORT
202 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
203 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
204 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
205 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x100000
209 /* Extra Environment */
210 #ifndef CONFIG_SPL_BUILD
212 #ifdef CONFIG_CMD_DHCP
213 #define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na)
215 #define BOOT_TARGET_DEVICES_DHCP(func)
218 #if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP)
219 #define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
221 #define BOOT_TARGET_DEVICES_PXE(func)
224 #ifdef CONFIG_CMD_MMC
225 #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
227 #define BOOT_TARGET_DEVICES_MMC(func)
230 #define BOOT_TARGET_DEVICES(func) \
231 BOOT_TARGET_DEVICES_MMC(func) \
232 BOOT_TARGET_DEVICES_PXE(func) \
233 BOOT_TARGET_DEVICES_DHCP(func)
235 #include <config_distro_bootcmd.h>
237 #ifndef CONFIG_EXTRA_ENV_SETTINGS
238 #define CONFIG_EXTRA_ENV_SETTINGS \
239 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
240 "bootm_size=0xa000000\0" \
241 "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \
242 "fdt_addr_r=0x02000000\0" \
243 "scriptaddr=0x02100000\0" \
244 "pxefile_addr_r=0x02200000\0" \
245 "ramdisk_addr_r=0x02300000\0" \
246 "socfpga_legacy_reset_compat=1\0" \
252 #endif /* __CONFIG_SOCFPGA_COMMON_H__ */