drivers/mmc/am654_sdhci.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
   4  *
   5  * Texas Instruments' K3 SD Host Controller Interface
   6  */
   7
   8 #include <clk.h>
   9 #include <common.h>
  10 #include <dm.h>
  11 #include <malloc.h>
  12 #include <power-domain.h>
  13 #include <regmap.h>
  14 #include <sdhci.h>
  15
  16 /* CTL_CFG Registers */
  17 #define CTL_CFG_2               0x14
  18
  19 #define SLOTTYPE_MASK           GENMASK(31, 30)
  20 #define SLOTTYPE_EMBEDDED       BIT(30)
  21
  22 /* PHY Registers */
  23 #define PHY_CTRL1       0x100
  24 #define PHY_CTRL2       0x104
  25 #define PHY_CTRL3       0x108
  26 #define PHY_CTRL4       0x10C
  27 #define PHY_CTRL5       0x110
  28 #define PHY_CTRL6       0x114
  29 #define PHY_STAT1       0x130
  30 #define PHY_STAT2       0x134
  31
  32 #define IOMUX_ENABLE_SHIFT      31
  33 #define IOMUX_ENABLE_MASK       BIT(IOMUX_ENABLE_SHIFT)
  34 #define OTAPDLYENA_SHIFT        20
  35 #define OTAPDLYENA_MASK         BIT(OTAPDLYENA_SHIFT)
  36 #define OTAPDLYSEL_SHIFT        12
  37 #define OTAPDLYSEL_MASK         GENMASK(15, 12)
  38 #define STRBSEL_SHIFT           24
  39 #define STRBSEL_MASK            GENMASK(27, 24)
  40 #define SEL50_SHIFT             8
  41 #define SEL50_MASK              BIT(SEL50_SHIFT)
  42 #define SEL100_SHIFT            9
  43 #define SEL100_MASK             BIT(SEL100_SHIFT)
  44 #define DLL_TRIM_ICP_SHIFT      4
  45 #define DLL_TRIM_ICP_MASK       GENMASK(7, 4)
  46 #define DR_TY_SHIFT             20
  47 #define DR_TY_MASK              GENMASK(22, 20)
  48 #define ENDLL_SHIFT             1
  49 #define ENDLL_MASK              BIT(ENDLL_SHIFT)
  50 #define DLLRDY_SHIFT            0
  51 #define DLLRDY_MASK             BIT(DLLRDY_SHIFT)
  52 #define PDB_SHIFT               0
  53 #define PDB_MASK                BIT(PDB_SHIFT)
  54 #define CALDONE_SHIFT           1
  55 #define CALDONE_MASK            BIT(CALDONE_SHIFT)
  56 #define RETRIM_SHIFT            17
  57 #define RETRIM_MASK             BIT(RETRIM_SHIFT)
  58
  59 #define DRIVER_STRENGTH_50_OHM  0x0
  60 #define DRIVER_STRENGTH_33_OHM  0x1
  61 #define DRIVER_STRENGTH_66_OHM  0x2
  62 #define DRIVER_STRENGTH_100_OHM 0x3
  63 #define DRIVER_STRENGTH_40_OHM  0x4
  64
  65 #define AM654_SDHCI_MIN_FREQ    400000
  66
  67 struct am654_sdhci_plat {
  68         struct mmc_config cfg;
  69         struct mmc mmc;
  70         struct regmap *base;
  71         bool non_removable;
  72         u32 otap_del_sel;
  73         u32 trm_icp;
  74         u32 drv_strength;
  75         u32 flags;
  76 #define DLL_PRESENT     (1 << 0)
  77         bool dll_on;
  78 };
  79
  80 static void am654_sdhci_set_control_reg(struct sdhci_host *host)
  81 {
  82         struct mmc *mmc = (struct mmc *)host->mmc;
  83         u32 reg;
  84
  85         if (IS_SD(host->mmc) &&
  86             mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
  87                 reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
  88                 reg |= SDHCI_CTRL_VDD_180;
  89                 sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
  90         }
  91
  92         sdhci_set_uhs_timing(host);
  93 }
  94
  95 static int am654_sdhci_set_ios_post(struct sdhci_host *host)
  96 {
  97         struct udevice *dev = host->mmc->dev;
  98         struct am654_sdhci_plat *plat = dev_get_platdata(dev);
  99         unsigned int speed = host->mmc->clock;
 100         int sel50, sel100;
 101         u32 mask, val;
 102         int ret;
 103
 104         /* Reset SD Clock Enable */
 105         val = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
 106         val &= ~SDHCI_CLOCK_CARD_EN;
 107         sdhci_writew(host, val, SDHCI_CLOCK_CONTROL);
 108
 109         /* power off phy */
 110         if (plat->dll_on) {
 111                 regmap_update_bits(plat->base, PHY_CTRL1, ENDLL_MASK, 0);
 112
 113                 plat->dll_on = false;
 114         }
 115
 116         /* restart clock */
 117         sdhci_set_clock(host->mmc, speed);
 118
 119         /* switch phy back on */
 120         if (speed > AM654_SDHCI_MIN_FREQ) {
 121                 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
 122                 val = (1 << OTAPDLYENA_SHIFT) |
 123                       (plat->otap_del_sel << OTAPDLYSEL_SHIFT);
 124                 regmap_update_bits(plat->base, PHY_CTRL4, mask, val);
 125                 switch (speed) {
 126                 case 200000000:
 127                         sel50 = 0;
 128                         sel100 = 0;
 129                         break;
 130                 case 100000000:
 131                         sel50 = 0;
 132                         sel100 = 1;
 133                         break;
 134                 default:
 135                         sel50 = 1;
 136                         sel100 = 0;
 137                 }
 138
 139                 /* Configure PHY DLL frequency */
 140                 mask = SEL50_MASK | SEL100_MASK;
 141                 val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT);
 142                 regmap_update_bits(plat->base, PHY_CTRL5, mask, val);
 143
 144                 /* Enable DLL */
 145                 regmap_update_bits(plat->base, PHY_CTRL1, ENDLL_MASK,
 146                                    0x1 << ENDLL_SHIFT);
 147                 /*
 148                  * Poll for DLL ready. Use a one second timeout.
 149                  * Works in all experiments done so far
 150                  */
 151                 ret = regmap_read_poll_timeout(plat->base, PHY_STAT1, val,
 152                                          val & DLLRDY_MASK, 1000, 1000000);
 153                 if (ret)
 154                         return ret;
 155
 156                 plat->dll_on = true;
 157         }
 158
 159         return 0;
 160 }
 161
 162 const struct sdhci_ops am654_sdhci_ops = {
 163         .set_ios_post           = &am654_sdhci_set_ios_post,
 164         .set_control_reg        = &am654_sdhci_set_control_reg,
 165 };
 166
 167 const struct sdhci_ops j721e_4bit_sdhci_ops = {
 168         .set_control_reg        = &am654_sdhci_set_control_reg,
 169 };
 170
 171 int am654_sdhci_init(struct am654_sdhci_plat *plat)
 172 {
 173         u32 ctl_cfg_2 = 0;
 174         u32 mask, val;
 175         int ret;
 176
 177         /* Reset OTAP to default value */
 178         mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
 179         regmap_update_bits(plat->base, PHY_CTRL4, mask, 0x0);
 180
 181         if (plat->flags & DLL_PRESENT) {
 182                 regmap_read(plat->base, PHY_STAT1, &val);
 183                 if (~val & CALDONE_MASK) {
 184                         /* Calibrate IO lines */
 185                         regmap_update_bits(plat->base, PHY_CTRL1, PDB_MASK,
 186                                            PDB_MASK);
 187                         ret = regmap_read_poll_timeout(plat->base, PHY_STAT1,
 188                                                        val, val & CALDONE_MASK,
 189                                                        1, 20);
 190                         if (ret)
 191                                 return ret;
 192                 }
 193
 194                 /* Configure DLL TRIM */
 195                 mask = DLL_TRIM_ICP_MASK;
 196                 val = plat->trm_icp << DLL_TRIM_ICP_SHIFT;
 197
 198                 /* Configure DLL driver strength */
 199                 mask |= DR_TY_MASK;
 200                 val |= plat->drv_strength << DR_TY_SHIFT;
 201                 regmap_update_bits(plat->base, PHY_CTRL1, mask, val);
 202         }
 203
 204         /* Enable pins by setting IO mux to 0 */
 205         regmap_update_bits(plat->base, PHY_CTRL1, IOMUX_ENABLE_MASK, 0);
 206
 207         /* Set slot type based on SD or eMMC */
 208         if (plat->non_removable)
 209                 ctl_cfg_2 = SLOTTYPE_EMBEDDED;
 210
 211         regmap_update_bits(plat->base, CTL_CFG_2, SLOTTYPE_MASK, ctl_cfg_2);
 212
 213         return 0;
 214 }
 215
 216 static int am654_sdhci_probe(struct udevice *dev)
 217 {
 218         struct am654_sdhci_plat *plat = dev_get_platdata(dev);
 219         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 220         struct sdhci_host *host = dev_get_priv(dev);
 221         struct mmc_config *cfg = &plat->cfg;
 222         struct power_domain sdhci_pwrdmn;
 223         struct clk clk;
 224         unsigned long clock;
 225         int ret;
 226
 227         ret = power_domain_get_by_index(dev, &sdhci_pwrdmn, 0);
 228         if (!ret) {
 229                 ret = power_domain_on(&sdhci_pwrdmn);
 230                 if (ret) {
 231                         dev_err(dev, "Power domain on failed (%d)\n", ret);
 232                         return ret;
 233                 }
 234         } else if (ret != -ENOENT && ret != -ENODEV && ret != -ENOSYS) {
 235                 dev_err(dev, "failed to get power domain (%d)\n", ret);
 236                 return ret;
 237         }
 238
 239         ret = clk_get_by_index(dev, 0, &clk);
 240         if (ret) {
 241                 dev_err(dev, "failed to get clock\n");
 242                 return ret;
 243         }
 244
 245         clock = clk_get_rate(&clk);
 246         if (IS_ERR_VALUE(clock)) {
 247                 dev_err(dev, "failed to get rate\n");
 248                 return clock;
 249         }
 250
 251         host->max_clk = clock;
 252         host->mmc = &plat->mmc;
 253         host->mmc->dev = dev;
 254         ret = sdhci_setup_cfg(cfg, host, cfg->f_max,
 255                               AM654_SDHCI_MIN_FREQ);
 256         if (ret)
 257                 return ret;
 258         host->ops = (struct sdhci_ops *)dev_get_driver_data(dev);
 259         host->mmc->priv = host;
 260         upriv->mmc = host->mmc;
 261
 262         regmap_init_mem_index(dev_ofnode(dev), &plat->base, 1);
 263
 264         am654_sdhci_init(plat);
 265
 266         return sdhci_probe(dev);
 267 }
 268
 269 static int am654_sdhci_ofdata_to_platdata(struct udevice *dev)
 270 {
 271         struct am654_sdhci_plat *plat = dev_get_platdata(dev);
 272         struct sdhci_host *host = dev_get_priv(dev);
 273         struct mmc_config *cfg = &plat->cfg;
 274         u32 drv_strength;
 275         int ret;
 276
 277         host->name = dev->name;
 278         host->ioaddr = (void *)dev_read_addr(dev);
 279         plat->non_removable = dev_read_bool(dev, "non-removable");
 280
 281         if (device_is_compatible(dev, "ti,am654-sdhci-5.1") ||
 282             device_is_compatible(dev, "ti,j721e-sdhci-8bit"))
 283                 plat->flags |= DLL_PRESENT;
 284
 285         ret = dev_read_u32(dev, "ti,otap-del-sel", &plat->otap_del_sel);
 286         if (ret)
 287                 return ret;
 288
 289         if (plat->flags & DLL_PRESENT) {
 290                 ret = dev_read_u32(dev, "ti,trm-icp", &plat->trm_icp);
 291                 if (ret)
 292                         return ret;
 293
 294                 ret = dev_read_u32(dev, "ti,driver-strength-ohm",
 295                                    &drv_strength);
 296                 if (ret)
 297                         return ret;
 298
 299                 switch (drv_strength) {
 300                 case 50:
 301                         plat->drv_strength = DRIVER_STRENGTH_50_OHM;
 302                         break;
 303                 case 33:
 304                         plat->drv_strength = DRIVER_STRENGTH_33_OHM;
 305                         break;
 306                 case 66:
 307                         plat->drv_strength = DRIVER_STRENGTH_66_OHM;
 308                         break;
 309                 case 100:
 310                         plat->drv_strength = DRIVER_STRENGTH_100_OHM;
 311                         break;
 312                 case 40:
 313                         plat->drv_strength = DRIVER_STRENGTH_40_OHM;
 314                         break;
 315                 default:
 316                         dev_err(dev, "Invalid driver strength\n");
 317                         return -EINVAL;
 318                 }
 319         }
 320
 321         ret = mmc_of_parse(dev, cfg);
 322         if (ret)
 323                 return ret;
 324
 325         return 0;
 326 }
 327
 328 static int am654_sdhci_bind(struct udevice *dev)
 329 {
 330         struct am654_sdhci_plat *plat = dev_get_platdata(dev);
 331
 332         return sdhci_bind(dev, &plat->mmc, &plat->cfg);
 333 }
 334
 335 static const struct udevice_id am654_sdhci_ids[] = {
 336         {
 337                 .compatible = "ti,am654-sdhci-5.1",
 338                 .data = (ulong)&am654_sdhci_ops,
 339         },
 340         {
 341                 .compatible = "ti,j721e-sdhci-8bit",
 342                 .data = (ulong)&am654_sdhci_ops,
 343         },
 344         {
 345                 .compatible = "ti,j721e-sdhci-4bit",
 346                 .data = (ulong)&j721e_4bit_sdhci_ops,
 347         },
 348         { }
 349 };
 350
 351 U_BOOT_DRIVER(am654_sdhci_drv) = {
 352         .name           = "am654_sdhci",
 353         .id             = UCLASS_MMC,
 354         .of_match       = am654_sdhci_ids,
 355         .ofdata_to_platdata = am654_sdhci_ofdata_to_platdata,
 356         .ops            = &sdhci_ops,
 357         .bind           = am654_sdhci_bind,
 358         .probe          = am654_sdhci_probe,
 359         .priv_auto_alloc_size = sizeof(struct sdhci_host),
 360         .platdata_auto_alloc_size = sizeof(struct am654_sdhci_plat),
 361 };