drivers/spi/spi-sunxi.c

   1 /*
   2  * (C) Copyright 2017 Whitebox Systems / Northend Systems B.V.
   3  * S.J.R. van Schaik <[email protected]>
   4  * M.B.W. Wajer <[email protected]>
   5  *
   6  * (C) Copyright 2017 Olimex Ltd..
   7  * Stefan Mavrodiev <[email protected]>
   8  *
   9  * Based on linux spi driver. Original copyright follows:
  10  * linux/drivers/spi/spi-sun4i.c
  11  *
  12  * Copyright (C) 2012 - 2014 Allwinner Tech
  13  * Pan Nan <[email protected]>
  14  *
  15  * Copyright (C) 2014 Maxime Ripard
  16  * Maxime Ripard <[email protected]>
  17  *
  18  * SPDX-License-Identifier:     GPL-2.0+
  19  */
  20
  21 #include <common.h>
  22 #include <clk.h>
  23 #include <dm.h>
  24 #include <log.h>
  25 #include <spi.h>
  26 #include <errno.h>
  27 #include <fdt_support.h>
  28 #include <reset.h>
  29 #include <wait_bit.h>
  30 #include <asm/global_data.h>
  31 #include <dm/device_compat.h>
  32 #include <linux/bitops.h>
  33
  34 #include <asm/bitops.h>
  35 #include <asm/io.h>
  36
  37 #include <linux/iopoll.h>
  38
  39 DECLARE_GLOBAL_DATA_PTR;
  40
  41 /* sun4i spi registers */
  42 #define SUN4I_RXDATA_REG                0x00
  43 #define SUN4I_TXDATA_REG                0x04
  44 #define SUN4I_CTL_REG                   0x08
  45 #define SUN4I_CLK_CTL_REG               0x1c
  46 #define SUN4I_BURST_CNT_REG             0x20
  47 #define SUN4I_XMIT_CNT_REG              0x24
  48 #define SUN4I_FIFO_STA_REG              0x28
  49
  50 /* sun6i spi registers */
  51 #define SUN6I_GBL_CTL_REG               0x04
  52 #define SUN6I_TFR_CTL_REG               0x08
  53 #define SUN6I_FIFO_CTL_REG              0x18
  54 #define SUN6I_FIFO_STA_REG              0x1c
  55 #define SUN6I_CLK_CTL_REG               0x24
  56 #define SUN6I_BURST_CNT_REG             0x30
  57 #define SUN6I_XMIT_CNT_REG              0x34
  58 #define SUN6I_BURST_CTL_REG             0x38
  59 #define SUN6I_TXDATA_REG                0x200
  60 #define SUN6I_RXDATA_REG                0x300
  61
  62 /* sun spi bits */
  63 #define SUN4I_CTL_ENABLE                BIT(0)
  64 #define SUN4I_CTL_MASTER                BIT(1)
  65 #define SUN4I_CLK_CTL_CDR2_MASK         0xff
  66 #define SUN4I_CLK_CTL_CDR2(div)         ((div) & SUN4I_CLK_CTL_CDR2_MASK)
  67 #define SUN4I_CLK_CTL_CDR1_MASK         0xf
  68 #define SUN4I_CLK_CTL_CDR1(div)         (((div) & SUN4I_CLK_CTL_CDR1_MASK) << 8)
  69 #define SUN4I_CLK_CTL_DRS               BIT(12)
  70 #define SUN4I_MAX_XFER_SIZE             0xffffff
  71 #define SUN4I_BURST_CNT(cnt)            ((cnt) & SUN4I_MAX_XFER_SIZE)
  72 #define SUN4I_XMIT_CNT(cnt)             ((cnt) & SUN4I_MAX_XFER_SIZE)
  73 #define SUN4I_FIFO_STA_RF_CNT_BITS      0
  74
  75 #ifdef CONFIG_MACH_SUNIV
  76 /* the AHB clock, which we programmed to be 1/3 of PLL_PERIPH@600MHz */
  77 #define SUNXI_INPUT_CLOCK               200000000       /* 200 MHz */
  78 #define SUN4I_SPI_MAX_RATE              (SUNXI_INPUT_CLOCK / 2)
  79 #else
  80 /* the SPI mod clock, defaulting to be 1/1 of the HOSC@24MHz */
  81 #define SUNXI_INPUT_CLOCK               24000000        /* 24 MHz */
  82 #define SUN4I_SPI_MAX_RATE              SUNXI_INPUT_CLOCK
  83 #endif
  84 #define SUN4I_SPI_MIN_RATE              3000
  85 #define SUN4I_SPI_DEFAULT_RATE          1000000
  86 #define SUN4I_SPI_TIMEOUT_MS            1000
  87
  88 #define SPI_REG(priv, reg)              ((priv)->base + \
  89                                         (priv)->variant->regs[reg])
  90 #define SPI_BIT(priv, bit)              ((priv)->variant->bits[bit])
  91 #define SPI_CS(priv, cs)                (((cs) << SPI_BIT(priv, SPI_TCR_CS_SEL)) & \
  92                                         SPI_BIT(priv, SPI_TCR_CS_MASK))
  93
  94 /* sun spi register set */
  95 enum sun4i_spi_regs {
  96         SPI_GCR,
  97         SPI_TCR,
  98         SPI_FCR,
  99         SPI_FSR,
 100         SPI_CCR,
 101         SPI_BC,
 102         SPI_TC,
 103         SPI_BCTL,
 104         SPI_TXD,
 105         SPI_RXD,
 106 };
 107
 108 /* sun spi register bits */
 109 enum sun4i_spi_bits {
 110         SPI_GCR_TP,
 111         SPI_GCR_SRST,
 112         SPI_TCR_CPHA,
 113         SPI_TCR_CPOL,
 114         SPI_TCR_CS_ACTIVE_LOW,
 115         SPI_TCR_CS_SEL,
 116         SPI_TCR_CS_MASK,
 117         SPI_TCR_XCH,
 118         SPI_TCR_CS_MANUAL,
 119         SPI_TCR_CS_LEVEL,
 120         SPI_FCR_TF_RST,
 121         SPI_FCR_RF_RST,
 122         SPI_FSR_RF_CNT_MASK,
 123 };
 124
 125 struct sun4i_spi_variant {
 126         const unsigned long *regs;
 127         const u32 *bits;
 128         u32 fifo_depth;
 129         bool has_soft_reset;
 130         bool has_burst_ctl;
 131 };
 132
 133 struct sun4i_spi_plat {
 134         struct sun4i_spi_variant *variant;
 135         u32 base;
 136         u32 max_hz;
 137 };
 138
 139 struct sun4i_spi_priv {
 140         struct sun4i_spi_variant *variant;
 141         struct clk clk_ahb, clk_mod;
 142         struct reset_ctl reset;
 143         u32 base;
 144         u32 freq;
 145         u32 mode;
 146
 147         const u8 *tx_buf;
 148         u8 *rx_buf;
 149 };
 150
 151 static inline void sun4i_spi_drain_fifo(struct sun4i_spi_priv *priv, int len)
 152 {
 153         u8 byte;
 154
 155         while (len--) {
 156                 byte = readb(SPI_REG(priv, SPI_RXD));
 157                 if (priv->rx_buf)
 158                         *priv->rx_buf++ = byte;
 159         }
 160 }
 161
 162 static inline void sun4i_spi_fill_fifo(struct sun4i_spi_priv *priv, int len)
 163 {
 164         u8 byte;
 165
 166         while (len--) {
 167                 byte = priv->tx_buf ? *priv->tx_buf++ : 0;
 168                 writeb(byte, SPI_REG(priv, SPI_TXD));
 169         }
 170 }
 171
 172 static void sun4i_spi_set_cs(struct udevice *bus, u8 cs, bool enable)
 173 {
 174         struct sun4i_spi_priv *priv = dev_get_priv(bus);
 175         u32 reg;
 176
 177         reg = readl(SPI_REG(priv, SPI_TCR));
 178
 179         reg &= ~SPI_BIT(priv, SPI_TCR_CS_MASK);
 180         reg |= SPI_CS(priv, cs);
 181
 182         if (enable)
 183                 reg &= ~SPI_BIT(priv, SPI_TCR_CS_LEVEL);
 184         else
 185                 reg |= SPI_BIT(priv, SPI_TCR_CS_LEVEL);
 186
 187         writel(reg, SPI_REG(priv, SPI_TCR));
 188 }
 189
 190 static inline int sun4i_spi_set_clock(struct udevice *dev, bool enable)
 191 {
 192         struct sun4i_spi_priv *priv = dev_get_priv(dev);
 193         int ret;
 194
 195         if (!enable) {
 196                 clk_disable(&priv->clk_ahb);
 197                 clk_disable(&priv->clk_mod);
 198                 if (reset_valid(&priv->reset))
 199                         reset_assert(&priv->reset);
 200                 return 0;
 201         }
 202
 203         ret = clk_enable(&priv->clk_ahb);
 204         if (ret) {
 205                 dev_err(dev, "failed to enable ahb clock (ret=%d)\n", ret);
 206                 return ret;
 207         }
 208
 209         ret = clk_enable(&priv->clk_mod);
 210         if (ret) {
 211                 dev_err(dev, "failed to enable mod clock (ret=%d)\n", ret);
 212                 goto err_ahb;
 213         }
 214
 215         if (reset_valid(&priv->reset)) {
 216                 ret = reset_deassert(&priv->reset);
 217                 if (ret) {
 218                         dev_err(dev, "failed to deassert reset\n");
 219                         goto err_mod;
 220                 }
 221         }
 222
 223         return 0;
 224
 225 err_mod:
 226         clk_disable(&priv->clk_mod);
 227 err_ahb:
 228         clk_disable(&priv->clk_ahb);
 229         return ret;
 230 }
 231
 232 static void sun4i_spi_set_speed_mode(struct udevice *dev)
 233 {
 234         struct sun4i_spi_priv *priv = dev_get_priv(dev);
 235         unsigned int div;
 236         u32 reg;
 237
 238         /*
 239          * Setup clock divider.
 240          *
 241          * We have two choices there. Either we can use the clock
 242          * divide rate 1, which is calculated thanks to this formula:
 243          * SPI_CLK = MOD_CLK / (2 ^ (cdr + 1))
 244          * Or we can use CDR2, which is calculated with the formula:
 245          * SPI_CLK = MOD_CLK / (2 * (cdr + 1))
 246          * Whether we use the former or the latter is set through the
 247          * DRS bit.
 248          *
 249          * First try CDR2, and if we can't reach the expected
 250          * frequency, fall back to CDR1.
 251          */
 252
 253         div = DIV_ROUND_UP(SUNXI_INPUT_CLOCK, priv->freq);
 254         reg = readl(SPI_REG(priv, SPI_CCR));
 255
 256         if ((div / 2) <= (SUN4I_CLK_CTL_CDR2_MASK + 1)) {
 257                 div /= 2;
 258                 if (div > 0)
 259                         div--;
 260
 261                 reg &= ~(SUN4I_CLK_CTL_CDR2_MASK | SUN4I_CLK_CTL_DRS);
 262                 reg |= SUN4I_CLK_CTL_CDR2(div) | SUN4I_CLK_CTL_DRS;
 263         } else {
 264                 div = fls(div - 1);
 265                 /* The F1C100s encodes the divider as 2^(n+1) */
 266                 if (IS_ENABLED(CONFIG_MACH_SUNIV))
 267                         div--;
 268                 reg &= ~((SUN4I_CLK_CTL_CDR1_MASK << 8) | SUN4I_CLK_CTL_DRS);
 269                 reg |= SUN4I_CLK_CTL_CDR1(div);
 270         }
 271
 272         writel(reg, SPI_REG(priv, SPI_CCR));
 273
 274         reg = readl(SPI_REG(priv, SPI_TCR));
 275         reg &= ~(SPI_BIT(priv, SPI_TCR_CPOL) | SPI_BIT(priv, SPI_TCR_CPHA));
 276
 277         if (priv->mode & SPI_CPOL)
 278                 reg |= SPI_BIT(priv, SPI_TCR_CPOL);
 279
 280         if (priv->mode & SPI_CPHA)
 281                 reg |= SPI_BIT(priv, SPI_TCR_CPHA);
 282
 283         writel(reg, SPI_REG(priv, SPI_TCR));
 284 }
 285
 286 static int sun4i_spi_claim_bus(struct udevice *dev)
 287 {
 288         struct sun4i_spi_priv *priv = dev_get_priv(dev->parent);
 289         int ret;
 290
 291         ret = sun4i_spi_set_clock(dev->parent, true);
 292         if (ret)
 293                 return ret;
 294
 295         setbits_le32(SPI_REG(priv, SPI_GCR), SUN4I_CTL_ENABLE |
 296                      SUN4I_CTL_MASTER | SPI_BIT(priv, SPI_GCR_TP));
 297
 298         if (priv->variant->has_soft_reset)
 299                 setbits_le32(SPI_REG(priv, SPI_GCR),
 300                              SPI_BIT(priv, SPI_GCR_SRST));
 301
 302         setbits_le32(SPI_REG(priv, SPI_TCR), SPI_BIT(priv, SPI_TCR_CS_MANUAL) |
 303                      SPI_BIT(priv, SPI_TCR_CS_ACTIVE_LOW));
 304
 305         sun4i_spi_set_speed_mode(dev->parent);
 306
 307         return 0;
 308 }
 309
 310 static int sun4i_spi_release_bus(struct udevice *dev)
 311 {
 312         struct sun4i_spi_priv *priv = dev_get_priv(dev->parent);
 313
 314         clrbits_le32(SPI_REG(priv, SPI_GCR), SUN4I_CTL_ENABLE);
 315
 316         sun4i_spi_set_clock(dev->parent, false);
 317
 318         return 0;
 319 }
 320
 321 static int sun4i_spi_xfer(struct udevice *dev, unsigned int bitlen,
 322                           const void *dout, void *din, unsigned long flags)
 323 {
 324         struct udevice *bus = dev->parent;
 325         struct sun4i_spi_priv *priv = dev_get_priv(bus);
 326         struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
 327
 328         u32 len = bitlen / 8;
 329         u8 nbytes;
 330         int ret;
 331
 332         priv->tx_buf = dout;
 333         priv->rx_buf = din;
 334
 335         if (bitlen % 8) {
 336                 debug("%s: non byte-aligned SPI transfer.\n", __func__);
 337                 return -ENAVAIL;
 338         }
 339
 340         if (flags & SPI_XFER_BEGIN)
 341                 sun4i_spi_set_cs(bus, slave_plat->cs, true);
 342
 343         /* Reset FIFOs */
 344         setbits_le32(SPI_REG(priv, SPI_FCR), SPI_BIT(priv, SPI_FCR_RF_RST) |
 345                      SPI_BIT(priv, SPI_FCR_TF_RST));
 346
 347         while (len) {
 348                 /* Setup the transfer now... */
 349                 nbytes = min(len, (priv->variant->fifo_depth - 1));
 350
 351                 /* Setup the counters */
 352                 writel(SUN4I_BURST_CNT(nbytes), SPI_REG(priv, SPI_BC));
 353                 writel(SUN4I_XMIT_CNT(nbytes), SPI_REG(priv, SPI_TC));
 354
 355                 if (priv->variant->has_burst_ctl)
 356                         writel(SUN4I_BURST_CNT(nbytes),
 357                                SPI_REG(priv, SPI_BCTL));
 358
 359                 /* Fill the TX FIFO */
 360                 sun4i_spi_fill_fifo(priv, nbytes);
 361
 362                 /* Start the transfer */
 363                 setbits_le32(SPI_REG(priv, SPI_TCR),
 364                              SPI_BIT(priv, SPI_TCR_XCH));
 365
 366                 /* Wait for the transfer to be done */
 367                 ret = wait_for_bit_le32((const void *)SPI_REG(priv, SPI_TCR),
 368                                         SPI_BIT(priv, SPI_TCR_XCH),
 369                                         false, SUN4I_SPI_TIMEOUT_MS, false);
 370                 if (ret < 0) {
 371                         printf("ERROR: sun4i_spi: Timeout transferring data\n");
 372                         sun4i_spi_set_cs(bus, slave_plat->cs, false);
 373                         return ret;
 374                 }
 375
 376                 /* Drain the RX FIFO */
 377                 sun4i_spi_drain_fifo(priv, nbytes);
 378
 379                 len -= nbytes;
 380         }
 381
 382         if (flags & SPI_XFER_END)
 383                 sun4i_spi_set_cs(bus, slave_plat->cs, false);
 384
 385         return 0;
 386 }
 387
 388 static int sun4i_spi_set_speed(struct udevice *dev, uint speed)
 389 {
 390         struct sun4i_spi_plat *plat = dev_get_plat(dev);
 391         struct sun4i_spi_priv *priv = dev_get_priv(dev);
 392
 393         if (speed > plat->max_hz)
 394                 speed = plat->max_hz;
 395
 396         if (speed < SUN4I_SPI_MIN_RATE)
 397                 speed = SUN4I_SPI_MIN_RATE;
 398
 399         priv->freq = speed;
 400
 401         return 0;
 402 }
 403
 404 static int sun4i_spi_set_mode(struct udevice *dev, uint mode)
 405 {
 406         struct sun4i_spi_priv *priv = dev_get_priv(dev);
 407
 408         priv->mode = mode;
 409
 410         return 0;
 411 }
 412
 413 static const struct dm_spi_ops sun4i_spi_ops = {
 414         .claim_bus              = sun4i_spi_claim_bus,
 415         .release_bus            = sun4i_spi_release_bus,
 416         .xfer                   = sun4i_spi_xfer,
 417         .set_speed              = sun4i_spi_set_speed,
 418         .set_mode               = sun4i_spi_set_mode,
 419 };
 420
 421 static int sun4i_spi_probe(struct udevice *bus)
 422 {
 423         struct sun4i_spi_plat *plat = dev_get_plat(bus);
 424         struct sun4i_spi_priv *priv = dev_get_priv(bus);
 425         int ret;
 426
 427         ret = clk_get_by_name(bus, "ahb", &priv->clk_ahb);
 428         if (ret) {
 429                 dev_err(bus, "failed to get ahb clock\n");
 430                 return ret;
 431         }
 432
 433         ret = clk_get_by_name(bus, "mod", &priv->clk_mod);
 434         if (ret) {
 435                 dev_err(bus, "failed to get mod clock\n");
 436                 return ret;
 437         }
 438
 439         ret = reset_get_by_index(bus, 0, &priv->reset);
 440         if (ret && ret != -ENOENT) {
 441                 dev_err(bus, "failed to get reset\n");
 442                 return ret;
 443         }
 444
 445         priv->variant = plat->variant;
 446         priv->base = plat->base;
 447         priv->freq = plat->max_hz;
 448
 449         return 0;
 450 }
 451
 452 static int sun4i_spi_of_to_plat(struct udevice *bus)
 453 {
 454         struct sun4i_spi_plat *plat = dev_get_plat(bus);
 455         int node = dev_of_offset(bus);
 456
 457         plat->base = dev_read_addr(bus);
 458         plat->variant = (struct sun4i_spi_variant *)dev_get_driver_data(bus);
 459         plat->max_hz = fdtdec_get_int(gd->fdt_blob, node,
 460                                       "spi-max-frequency",
 461                                       SUN4I_SPI_DEFAULT_RATE);
 462
 463         if (plat->max_hz > SUN4I_SPI_MAX_RATE)
 464                 plat->max_hz = SUN4I_SPI_MAX_RATE;
 465
 466         return 0;
 467 }
 468
 469 static const unsigned long sun4i_spi_regs[] = {
 470         [SPI_GCR]               = SUN4I_CTL_REG,
 471         [SPI_TCR]               = SUN4I_CTL_REG,
 472         [SPI_FCR]               = SUN4I_CTL_REG,
 473         [SPI_FSR]               = SUN4I_FIFO_STA_REG,
 474         [SPI_CCR]               = SUN4I_CLK_CTL_REG,
 475         [SPI_BC]                = SUN4I_BURST_CNT_REG,
 476         [SPI_TC]                = SUN4I_XMIT_CNT_REG,
 477         [SPI_TXD]               = SUN4I_TXDATA_REG,
 478         [SPI_RXD]               = SUN4I_RXDATA_REG,
 479 };
 480
 481 static const u32 sun4i_spi_bits[] = {
 482         [SPI_GCR_TP]            = BIT(18),
 483         [SPI_TCR_CPHA]          = BIT(2),
 484         [SPI_TCR_CPOL]          = BIT(3),
 485         [SPI_TCR_CS_ACTIVE_LOW] = BIT(4),
 486         [SPI_TCR_XCH]           = BIT(10),
 487         [SPI_TCR_CS_SEL]        = 12,
 488         [SPI_TCR_CS_MASK]       = 0x3000,
 489         [SPI_TCR_CS_MANUAL]     = BIT(16),
 490         [SPI_TCR_CS_LEVEL]      = BIT(17),
 491         [SPI_FCR_TF_RST]        = BIT(8),
 492         [SPI_FCR_RF_RST]        = BIT(9),
 493         [SPI_FSR_RF_CNT_MASK]   = GENMASK(6, 0),
 494 };
 495
 496 static const unsigned long sun6i_spi_regs[] = {
 497         [SPI_GCR]               = SUN6I_GBL_CTL_REG,
 498         [SPI_TCR]               = SUN6I_TFR_CTL_REG,
 499         [SPI_FCR]               = SUN6I_FIFO_CTL_REG,
 500         [SPI_FSR]               = SUN6I_FIFO_STA_REG,
 501         [SPI_CCR]               = SUN6I_CLK_CTL_REG,
 502         [SPI_BC]                = SUN6I_BURST_CNT_REG,
 503         [SPI_TC]                = SUN6I_XMIT_CNT_REG,
 504         [SPI_BCTL]              = SUN6I_BURST_CTL_REG,
 505         [SPI_TXD]               = SUN6I_TXDATA_REG,
 506         [SPI_RXD]               = SUN6I_RXDATA_REG,
 507 };
 508
 509 static const u32 sun6i_spi_bits[] = {
 510         [SPI_GCR_TP]            = BIT(7),
 511         [SPI_GCR_SRST]          = BIT(31),
 512         [SPI_TCR_CPHA]          = BIT(0),
 513         [SPI_TCR_CPOL]          = BIT(1),
 514         [SPI_TCR_CS_ACTIVE_LOW] = BIT(2),
 515         [SPI_TCR_CS_SEL]        = 4,
 516         [SPI_TCR_CS_MASK]       = 0x30,
 517         [SPI_TCR_CS_MANUAL]     = BIT(6),
 518         [SPI_TCR_CS_LEVEL]      = BIT(7),
 519         [SPI_TCR_XCH]           = BIT(31),
 520         [SPI_FCR_RF_RST]        = BIT(15),
 521         [SPI_FCR_TF_RST]        = BIT(31),
 522         [SPI_FSR_RF_CNT_MASK]   = GENMASK(7, 0),
 523 };
 524
 525 static const struct sun4i_spi_variant sun4i_a10_spi_variant = {
 526         .regs                   = sun4i_spi_regs,
 527         .bits                   = sun4i_spi_bits,
 528         .fifo_depth             = 64,
 529 };
 530
 531 static const struct sun4i_spi_variant sun6i_a31_spi_variant = {
 532         .regs                   = sun6i_spi_regs,
 533         .bits                   = sun6i_spi_bits,
 534         .fifo_depth             = 128,
 535         .has_soft_reset         = true,
 536         .has_burst_ctl          = true,
 537 };
 538
 539 static const struct sun4i_spi_variant sun8i_h3_spi_variant = {
 540         .regs                   = sun6i_spi_regs,
 541         .bits                   = sun6i_spi_bits,
 542         .fifo_depth             = 64,
 543         .has_soft_reset         = true,
 544         .has_burst_ctl          = true,
 545 };
 546
 547 static const struct udevice_id sun4i_spi_ids[] = {
 548         {
 549           .compatible = "allwinner,sun4i-a10-spi",
 550           .data = (ulong)&sun4i_a10_spi_variant,
 551         },
 552         {
 553           .compatible = "allwinner,sun6i-a31-spi",
 554           .data = (ulong)&sun6i_a31_spi_variant,
 555         },
 556         {
 557           .compatible = "allwinner,sun8i-h3-spi",
 558           .data = (ulong)&sun8i_h3_spi_variant,
 559         },
 560         { /* sentinel */ }
 561 };
 562
 563 U_BOOT_DRIVER(sun4i_spi) = {
 564         .name   = "sun4i_spi",
 565         .id     = UCLASS_SPI,
 566         .of_match       = sun4i_spi_ids,
 567         .ops    = &sun4i_spi_ops,
 568         .of_to_plat     = sun4i_spi_of_to_plat,
 569         .plat_auto      = sizeof(struct sun4i_spi_plat),
 570         .priv_auto      = sizeof(struct sun4i_spi_priv),
 571         .probe  = sun4i_spi_probe,
 572 };