1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
3 * Copyright (c) 2018 Microsemi Corporation
6 #ifndef __ASM_MACH_COMMON_H
7 #define __ASM_MACH_COMMON_H
9 #if defined(CONFIG_SOC_OCELOT)
10 #include <mach/ocelot/ocelot.h>
11 #include <mach/ocelot/ocelot_devcpu_gcb.h>
12 #include <mach/ocelot/ocelot_icpu_cfg.h>
13 #elif defined(CONFIG_SOC_LUTON)
14 #include <mach/luton/luton.h>
15 #include <mach/luton/luton_devcpu_gcb.h>
16 #include <mach/luton/luton_icpu_cfg.h>
18 #error Unsupported platform
21 #define MSCC_DDR_TO 0x20000000 /* DDR RAM base offset */
22 #define MSCC_MEMCTL1_TO 0x40000000 /* SPI/PI base offset */
23 #define MSCC_MEMCTL2_TO 0x50000000 /* SPI/PI base offset */
24 #define MSCC_FLASH_TO MSCC_MEMCTL1_TO /* Flash base offset */
26 #define VCOREIII_TIMER_DIVIDER 25 /* Clock tick ~ 0.1 us */
28 #endif /* __ASM_MACH_COMMON_H */