dts/upstream/src/arm/rockchip/rk3036.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2
   3 #include <dt-bindings/gpio/gpio.h>
   4 #include <dt-bindings/interrupt-controller/irq.h>
   5 #include <dt-bindings/interrupt-controller/arm-gic.h>
   6 #include <dt-bindings/pinctrl/rockchip.h>
   7 #include <dt-bindings/clock/rk3036-cru.h>
   8 #include <dt-bindings/soc/rockchip,boot-mode.h>
   9 #include <dt-bindings/power/rk3036-power.h>
  10
  11 / {
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14
  15         compatible = "rockchip,rk3036";
  16
  17         interrupt-parent = <&gic>;
  18
  19         aliases {
  20                 gpio0 = &gpio0;
  21                 gpio1 = &gpio1;
  22                 gpio2 = &gpio2;
  23                 i2c0 = &i2c0;
  24                 i2c1 = &i2c1;
  25                 i2c2 = &i2c2;
  26                 mshc0 = &emmc;
  27                 mshc1 = &sdmmc;
  28                 mshc2 = &sdio;
  29                 serial0 = &uart0;
  30                 serial1 = &uart1;
  31                 serial2 = &uart2;
  32                 spi = &spi;
  33         };
  34
  35         cpus {
  36                 #address-cells = <1>;
  37                 #size-cells = <0>;
  38                 enable-method = "rockchip,rk3036-smp";
  39
  40                 cpu0: cpu@f00 {
  41                         device_type = "cpu";
  42                         compatible = "arm,cortex-a7";
  43                         reg = <0xf00>;
  44                         resets = <&cru SRST_CORE0>;
  45                         operating-points = <
  46                                 /* KHz    uV */
  47                                  816000 1000000
  48                         >;
  49                         clock-latency = <40000>;
  50                         clocks = <&cru ARMCLK>;
  51                 };
  52
  53                 cpu1: cpu@f01 {
  54                         device_type = "cpu";
  55                         compatible = "arm,cortex-a7";
  56                         reg = <0xf01>;
  57                         resets = <&cru SRST_CORE1>;
  58                 };
  59         };
  60
  61         arm-pmu {
  62                 compatible = "arm,cortex-a7-pmu";
  63                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
  64                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
  65                 interrupt-affinity = <&cpu0>, <&cpu1>;
  66         };
  67
  68         display-subsystem {
  69                 compatible = "rockchip,display-subsystem";
  70                 ports = <&vop_out>;
  71         };
  72
  73         timer {
  74                 compatible = "arm,armv7-timer";
  75                 arm,cpu-registers-not-fw-configured;
  76                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
  77                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
  78                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
  79                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
  80                 clock-frequency = <24000000>;
  81         };
  82
  83         xin24m: oscillator {
  84                 compatible = "fixed-clock";
  85                 clock-frequency = <24000000>;
  86                 clock-output-names = "xin24m";
  87                 #clock-cells = <0>;
  88         };
  89
  90         bus_intmem: sram@10080000 {
  91                 compatible = "mmio-sram";
  92                 reg = <0x10080000 0x2000>;
  93                 #address-cells = <1>;
  94                 #size-cells = <1>;
  95                 ranges = <0 0x10080000 0x2000>;
  96
  97                 smp-sram@0 {
  98                         compatible = "rockchip,rk3066-smp-sram";
  99                         reg = <0x00 0x10>;
 100                 };
 101         };
 102
 103         gpu: gpu@10090000 {
 104                 compatible = "rockchip,rk3036-mali", "arm,mali-400";
 105                 reg = <0x10090000 0x10000>;
 106                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 107                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 108                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 109                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 110                 interrupt-names = "gp",
 111                                   "gpmmu",
 112                                   "pp0",
 113                                   "ppmmu0";
 114                 assigned-clocks = <&cru SCLK_GPU>;
 115                 assigned-clock-rates = <100000000>;
 116                 clocks = <&cru SCLK_GPU>, <&cru SCLK_GPU>;
 117                 clock-names = "bus", "core";
 118                 power-domains = <&power RK3036_PD_GPU>;
 119                 resets = <&cru SRST_GPU>;
 120                 status = "disabled";
 121         };
 122
 123         vpu: video-codec@10108000 {
 124                 compatible = "rockchip,rk3036-vpu";
 125                 reg = <0x10108000 0x800>;
 126                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 127                 interrupt-names = "vdpu";
 128                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
 129                 clock-names = "aclk", "hclk";
 130                 iommus = <&vpu_mmu>;
 131                 power-domains = <&power RK3036_PD_VPU>;
 132         };
 133
 134         vpu_mmu: iommu@10108800 {
 135                 compatible = "rockchip,iommu";
 136                 reg = <0x10108800 0x100>;
 137                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 138                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
 139                 clock-names = "aclk", "iface";
 140                 power-domains = <&power RK3036_PD_VPU>;
 141                 #iommu-cells = <0>;
 142         };
 143
 144         vop: vop@10118000 {
 145                 compatible = "rockchip,rk3036-vop";
 146                 reg = <0x10118000 0x19c>;
 147                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 148                 clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>;
 149                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 150                 resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>;
 151                 reset-names = "axi", "ahb", "dclk";
 152                 iommus = <&vop_mmu>;
 153                 power-domains = <&power RK3036_PD_VIO>;
 154                 status = "disabled";
 155
 156                 vop_out: port {
 157                         #address-cells = <1>;
 158                         #size-cells = <0>;
 159                         vop_out_hdmi: endpoint@0 {
 160                                 reg = <0>;
 161                                 remote-endpoint = <&hdmi_in_vop>;
 162                         };
 163                 };
 164         };
 165
 166         vop_mmu: iommu@10118300 {
 167                 compatible = "rockchip,iommu";
 168                 reg = <0x10118300 0x100>;
 169                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 170                 clocks = <&cru ACLK_LCDC>, <&cru HCLK_LCDC>;
 171                 clock-names = "aclk", "iface";
 172                 power-domains = <&power RK3036_PD_VIO>;
 173                 #iommu-cells = <0>;
 174                 status = "disabled";
 175         };
 176
 177         qos_gpu: qos@1012d000 {
 178                 compatible = "rockchip,rk3036-qos", "syscon";
 179                 reg = <0x1012d000 0x20>;
 180         };
 181
 182         qos_vpu: qos@1012e000 {
 183                 compatible = "rockchip,rk3036-qos", "syscon";
 184                 reg = <0x1012e000 0x20>;
 185         };
 186
 187         qos_vio: qos@1012f000 {
 188                 compatible = "rockchip,rk3036-qos", "syscon";
 189                 reg = <0x1012f000 0x20>;
 190         };
 191
 192         gic: interrupt-controller@10139000 {
 193                 compatible = "arm,gic-400";
 194                 interrupt-controller;
 195                 #interrupt-cells = <3>;
 196                 #address-cells = <0>;
 197
 198                 reg = <0x10139000 0x1000>,
 199                       <0x1013a000 0x2000>,
 200                       <0x1013c000 0x2000>,
 201                       <0x1013e000 0x2000>;
 202                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 203         };
 204
 205         usb_otg: usb@10180000 {
 206                 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
 207                                 "snps,dwc2";
 208                 reg = <0x10180000 0x40000>;
 209                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 210                 clocks = <&cru HCLK_OTG0>;
 211                 clock-names = "otg";
 212                 dr_mode = "otg";
 213                 g-np-tx-fifo-size = <16>;
 214                 g-rx-fifo-size = <275>;
 215                 g-tx-fifo-size = <256 128 128 64 64 32>;
 216                 status = "disabled";
 217         };
 218
 219         usb_host: usb@101c0000 {
 220                 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
 221                                 "snps,dwc2";
 222                 reg = <0x101c0000 0x40000>;
 223                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 224                 clocks = <&cru HCLK_OTG1>;
 225                 clock-names = "otg";
 226                 dr_mode = "host";
 227                 status = "disabled";
 228         };
 229
 230         emac: ethernet@10200000 {
 231                 compatible = "rockchip,rk3036-emac";
 232                 reg = <0x10200000 0x4000>;
 233                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 234                 rockchip,grf = <&grf>;
 235                 clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>;
 236                 clock-names = "hclk", "macref", "macclk";
 237                 /*
 238                  * Fix the emac parent clock is DPLL instead of APLL.
 239                  * since that will cause some unstable things if the cpufreq
 240                  * is working. (e.g: the accurate 50MHz what mac_ref need)
 241                  */
 242                 assigned-clocks = <&cru SCLK_MACPLL>;
 243                 assigned-clock-parents = <&cru PLL_DPLL>;
 244                 max-speed = <100>;
 245                 phy-mode = "rmii";
 246                 status = "disabled";
 247         };
 248
 249         sdmmc: mmc@10214000 {
 250                 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
 251                 reg = <0x10214000 0x4000>;
 252                 clock-frequency = <37500000>;
 253                 max-frequency = <37500000>;
 254                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 255                 clock-names = "biu", "ciu";
 256                 fifo-depth = <0x100>;
 257                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 258                 resets = <&cru SRST_MMC0>;
 259                 reset-names = "reset";
 260                 status = "disabled";
 261         };
 262
 263         sdio: mmc@10218000 {
 264                 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
 265                 reg = <0x10218000 0x4000>;
 266                 max-frequency = <37500000>;
 267                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 268                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 269                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 270                 fifo-depth = <0x100>;
 271                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 272                 resets = <&cru SRST_SDIO>;
 273                 reset-names = "reset";
 274                 status = "disabled";
 275         };
 276
 277         emmc: mmc@1021c000 {
 278                 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
 279                 reg = <0x1021c000 0x4000>;
 280                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 281                 bus-width = <8>;
 282                 cap-mmc-highspeed;
 283                 clock-frequency = <37500000>;
 284                 max-frequency = <37500000>;
 285                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 286                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 287                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 288                 disable-wp;
 289                 dmas = <&pdma 12>;
 290                 dma-names = "rx-tx";
 291                 fifo-depth = <0x100>;
 292                 mmc-ddr-1_8v;
 293                 non-removable;
 294                 pinctrl-names = "default";
 295                 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
 296                 resets = <&cru SRST_EMMC>;
 297                 reset-names = "reset";
 298                 status = "disabled";
 299         };
 300
 301         i2s: i2s@10220000 {
 302                 compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s";
 303                 reg = <0x10220000 0x4000>;
 304                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 305                 clock-names = "i2s_clk", "i2s_hclk";
 306                 clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>;
 307                 dmas = <&pdma 0>, <&pdma 1>;
 308                 dma-names = "tx", "rx";
 309                 pinctrl-names = "default";
 310                 pinctrl-0 = <&i2s_bus>;
 311                 #sound-dai-cells = <0>;
 312                 status = "disabled";
 313         };
 314
 315         nfc: nand-controller@10500000 {
 316                 compatible = "rockchip,rk3036-nfc",
 317                              "rockchip,rk2928-nfc";
 318                 reg = <0x10500000 0x4000>;
 319                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 320                 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
 321                 clock-names = "ahb", "nfc";
 322                 assigned-clocks = <&cru SCLK_NANDC>;
 323                 assigned-clock-rates = <150000000>;
 324                 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0
 325                              &flash_rdn &flash_rdy &flash_wrn>;
 326                 pinctrl-names = "default";
 327                 status = "disabled";
 328         };
 329
 330         cru: clock-controller@20000000 {
 331                 compatible = "rockchip,rk3036-cru";
 332                 reg = <0x20000000 0x1000>;
 333                 clocks = <&xin24m>;
 334                 clock-names = "xin24m";
 335                 rockchip,grf = <&grf>;
 336                 #clock-cells = <1>;
 337                 #reset-cells = <1>;
 338                 assigned-clocks = <&cru PLL_GPLL>;
 339                 assigned-clock-rates = <594000000>;
 340         };
 341
 342         grf: syscon@20008000 {
 343                 compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd";
 344                 reg = <0x20008000 0x1000>;
 345
 346                 power: power-controller {
 347                         compatible = "rockchip,rk3036-power-controller";
 348                         #power-domain-cells = <1>;
 349                         #address-cells = <1>;
 350                         #size-cells = <0>;
 351
 352                         power-domain@RK3036_PD_VIO {
 353                                 reg = <RK3036_PD_VIO>;
 354                                 clocks = <&cru ACLK_LCDC>,
 355                                          <&cru HCLK_LCDC>,
 356                                          <&cru SCLK_LCDC>;
 357                                 pm_qos = <&qos_vio>;
 358                                 #power-domain-cells = <0>;
 359                         };
 360
 361                         power-domain@RK3036_PD_VPU {
 362                                 reg = <RK3036_PD_VPU>;
 363                                 clocks = <&cru ACLK_VCODEC>,
 364                                          <&cru HCLK_VCODEC>;
 365                                 pm_qos = <&qos_vpu>;
 366                                 #power-domain-cells = <0>;
 367                         };
 368
 369                         power-domain@RK3036_PD_GPU {
 370                                 reg = <RK3036_PD_GPU>;
 371                                 clocks = <&cru SCLK_GPU>;
 372                                 pm_qos = <&qos_gpu>;
 373                                 #power-domain-cells = <0>;
 374                         };
 375                 };
 376
 377                 reboot-mode {
 378                         compatible = "syscon-reboot-mode";
 379                         offset = <0x1d8>;
 380                         mode-normal = <BOOT_NORMAL>;
 381                         mode-recovery = <BOOT_RECOVERY>;
 382                         mode-bootloader = <BOOT_FASTBOOT>;
 383                         mode-loader = <BOOT_BL_DOWNLOAD>;
 384                 };
 385         };
 386
 387         acodec: audio-codec@20030000 {
 388                 compatible = "rockchip,rk3036-codec";
 389                 reg = <0x20030000 0x4000>;
 390                 clock-names = "acodec_pclk";
 391                 clocks = <&cru PCLK_ACODEC>;
 392                 rockchip,grf = <&grf>;
 393                 #sound-dai-cells = <0>;
 394                 status = "disabled";
 395         };
 396
 397         hdmi: hdmi@20034000 {
 398                 compatible = "rockchip,rk3036-inno-hdmi";
 399                 reg = <0x20034000 0x4000>;
 400                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 401                 clocks = <&cru  PCLK_HDMI>;
 402                 clock-names = "pclk";
 403                 pinctrl-names = "default";
 404                 pinctrl-0 = <&hdmi_ctl>;
 405                 #sound-dai-cells = <0>;
 406                 status = "disabled";
 407
 408                 ports {
 409                         #address-cells = <1>;
 410                         #size-cells = <0>;
 411
 412                         hdmi_in: port@0 {
 413                                 reg = <0>;
 414
 415                                 hdmi_in_vop: endpoint {
 416                                         remote-endpoint = <&vop_out_hdmi>;
 417                                 };
 418                         };
 419
 420                         hdmi_out: port@1 {
 421                                 reg = <1>;
 422                         };
 423                 };
 424         };
 425
 426         timer: timer@20044000 {
 427                 compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer";
 428                 reg = <0x20044000 0x20>;
 429                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 430                 clocks = <&cru PCLK_TIMER>, <&xin24m>;
 431                 clock-names = "pclk", "timer";
 432         };
 433
 434         pwm0: pwm@20050000 {
 435                 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
 436                 reg = <0x20050000 0x10>;
 437                 #pwm-cells = <3>;
 438                 clocks = <&cru PCLK_PWM>;
 439                 pinctrl-names = "default";
 440                 pinctrl-0 = <&pwm0_pin>;
 441                 status = "disabled";
 442         };
 443
 444         pwm1: pwm@20050010 {
 445                 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
 446                 reg = <0x20050010 0x10>;
 447                 #pwm-cells = <3>;
 448                 clocks = <&cru PCLK_PWM>;
 449                 pinctrl-names = "default";
 450                 pinctrl-0 = <&pwm1_pin>;
 451                 status = "disabled";
 452         };
 453
 454         pwm2: pwm@20050020 {
 455                 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
 456                 reg = <0x20050020 0x10>;
 457                 #pwm-cells = <3>;
 458                 clocks = <&cru PCLK_PWM>;
 459                 pinctrl-names = "default";
 460                 pinctrl-0 = <&pwm2_pin>;
 461                 status = "disabled";
 462         };
 463
 464         pwm3: pwm@20050030 {
 465                 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
 466                 reg = <0x20050030 0x10>;
 467                 #pwm-cells = <2>;
 468                 clocks = <&cru PCLK_PWM>;
 469                 pinctrl-names = "default";
 470                 pinctrl-0 = <&pwm3_pin>;
 471                 status = "disabled";
 472         };
 473
 474         i2c1: i2c@20056000 {
 475                 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
 476                 reg = <0x20056000 0x1000>;
 477                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 478                 #address-cells = <1>;
 479                 #size-cells = <0>;
 480                 clock-names = "i2c";
 481                 clocks = <&cru PCLK_I2C1>;
 482                 pinctrl-names = "default";
 483                 pinctrl-0 = <&i2c1_xfer>;
 484                 status = "disabled";
 485         };
 486
 487         i2c2: i2c@2005a000 {
 488                 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
 489                 reg = <0x2005a000 0x1000>;
 490                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 491                 #address-cells = <1>;
 492                 #size-cells = <0>;
 493                 clock-names = "i2c";
 494                 clocks = <&cru PCLK_I2C2>;
 495                 pinctrl-names = "default";
 496                 pinctrl-0 = <&i2c2_xfer>;
 497                 status = "disabled";
 498         };
 499
 500         uart0: serial@20060000 {
 501                 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
 502                 reg = <0x20060000 0x100>;
 503                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 504                 reg-shift = <2>;
 505                 reg-io-width = <4>;
 506                 clock-frequency = <24000000>;
 507                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 508                 clock-names = "baudclk", "apb_pclk";
 509                 pinctrl-names = "default";
 510                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 511                 status = "disabled";
 512         };
 513
 514         uart1: serial@20064000 {
 515                 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
 516                 reg = <0x20064000 0x100>;
 517                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 518                 reg-shift = <2>;
 519                 reg-io-width = <4>;
 520                 clock-frequency = <24000000>;
 521                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 522                 clock-names = "baudclk", "apb_pclk";
 523                 pinctrl-names = "default";
 524                 pinctrl-0 = <&uart1_xfer>;
 525                 status = "disabled";
 526         };
 527
 528         uart2: serial@20068000 {
 529                 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
 530                 reg = <0x20068000 0x100>;
 531                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 532                 reg-shift = <2>;
 533                 reg-io-width = <4>;
 534                 clock-frequency = <24000000>;
 535                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 536                 clock-names = "baudclk", "apb_pclk";
 537                 pinctrl-names = "default";
 538                 pinctrl-0 = <&uart2_xfer>;
 539                 status = "disabled";
 540         };
 541
 542         i2c0: i2c@20072000 {
 543                 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
 544                 reg = <0x20072000 0x1000>;
 545                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 546                 #address-cells = <1>;
 547                 #size-cells = <0>;
 548                 clock-names = "i2c";
 549                 clocks = <&cru PCLK_I2C0>;
 550                 pinctrl-names = "default";
 551                 pinctrl-0 = <&i2c0_xfer>;
 552                 status = "disabled";
 553         };
 554
 555         spi: spi@20074000 {
 556                 compatible = "rockchip,rk3036-spi";
 557                 reg = <0x20074000 0x1000>;
 558                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 559                 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
 560                 clock-names = "spiclk", "apb_pclk";
 561                 dmas = <&pdma 8>, <&pdma 9>;
 562                 dma-names = "tx", "rx";
 563                 pinctrl-names = "default";
 564                 pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>;
 565                 #address-cells = <1>;
 566                 #size-cells = <0>;
 567                 status = "disabled";
 568         };
 569
 570         pdma: dma-controller@20078000 {
 571                 compatible = "arm,pl330", "arm,primecell";
 572                 reg = <0x20078000 0x4000>;
 573                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 574                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 575                 #dma-cells = <1>;
 576                 arm,pl330-broken-no-flushp;
 577                 arm,pl330-periph-burst;
 578                 clocks = <&cru ACLK_DMAC2>;
 579                 clock-names = "apb_pclk";
 580         };
 581
 582         pinctrl: pinctrl {
 583                 compatible = "rockchip,rk3036-pinctrl";
 584                 rockchip,grf = <&grf>;
 585                 #address-cells = <1>;
 586                 #size-cells = <1>;
 587                 ranges;
 588
 589                 gpio0: gpio@2007c000 {
 590                         compatible = "rockchip,gpio-bank";
 591                         reg = <0x2007c000 0x100>;
 592                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 593                         clocks = <&cru PCLK_GPIO0>;
 594
 595                         gpio-controller;
 596                         #gpio-cells = <2>;
 597
 598                         interrupt-controller;
 599                         #interrupt-cells = <2>;
 600                 };
 601
 602                 gpio1: gpio@20080000 {
 603                         compatible = "rockchip,gpio-bank";
 604                         reg = <0x20080000 0x100>;
 605                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 606                         clocks = <&cru PCLK_GPIO1>;
 607
 608                         gpio-controller;
 609                         #gpio-cells = <2>;
 610
 611                         interrupt-controller;
 612                         #interrupt-cells = <2>;
 613                 };
 614
 615                 gpio2: gpio@20084000 {
 616                         compatible = "rockchip,gpio-bank";
 617                         reg = <0x20084000 0x100>;
 618                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 619                         clocks = <&cru PCLK_GPIO2>;
 620
 621                         gpio-controller;
 622                         #gpio-cells = <2>;
 623
 624                         interrupt-controller;
 625                         #interrupt-cells = <2>;
 626                 };
 627
 628                 pcfg_pull_default: pcfg-pull-default {
 629                         bias-pull-pin-default;
 630                 };
 631
 632                 pcfg_pull_none: pcfg-pull-none {
 633                         bias-disable;
 634                 };
 635
 636                 pwm0 {
 637                         pwm0_pin: pwm0-pin {
 638                                 rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;
 639                         };
 640                 };
 641
 642                 pwm1 {
 643                         pwm1_pin: pwm1-pin {
 644                                 rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
 645                         };
 646                 };
 647
 648                 pwm2 {
 649                         pwm2_pin: pwm2-pin {
 650                                 rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
 651                         };
 652                 };
 653
 654                 pwm3 {
 655                         pwm3_pin: pwm3-pin {
 656                                 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
 657                         };
 658                 };
 659
 660                 sdmmc {
 661                         sdmmc_clk: sdmmc-clk {
 662                                 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>;
 663                         };
 664
 665                         sdmmc_cmd: sdmmc-cmd {
 666                                 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>;
 667                         };
 668
 669                         sdmmc_cd: sdmmc-cd {
 670                                 rockchip,pins = <1 RK_PC1 1 &pcfg_pull_default>;
 671                         };
 672
 673                         sdmmc_bus1: sdmmc-bus1 {
 674                                 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>;
 675                         };
 676
 677                         sdmmc_bus4: sdmmc-bus4 {
 678                                 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>,
 679                                                 <1 RK_PC3 1 &pcfg_pull_default>,
 680                                                 <1 RK_PC4 1 &pcfg_pull_default>,
 681                                                 <1 RK_PC5 1 &pcfg_pull_default>;
 682                         };
 683                 };
 684
 685                 sdio {
 686                         sdio_bus1: sdio-bus1 {
 687                                 rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>;
 688                         };
 689
 690                         sdio_bus4: sdio-bus4 {
 691                                 rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>,
 692                                                 <0 RK_PB4 1 &pcfg_pull_default>,
 693                                                 <0 RK_PB5 1 &pcfg_pull_default>,
 694                                                 <0 RK_PB6 1 &pcfg_pull_default>;
 695                         };
 696
 697                         sdio_cmd: sdio-cmd {
 698                                 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_default>;
 699                         };
 700
 701                         sdio_clk: sdio-clk {
 702                                 rockchip,pins = <0 RK_PB1 1 &pcfg_pull_none>;
 703                         };
 704                 };
 705
 706                 emmc {
 707                         /*
 708                          * We run eMMC at max speed; bump up drive strength.
 709                          * We also have external pulls, so disable the internal ones.
 710                          */
 711                         emmc_clk: emmc-clk {
 712                                 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
 713                         };
 714
 715                         emmc_cmd: emmc-cmd {
 716                                 rockchip,pins = <2 RK_PA1 2 &pcfg_pull_default>;
 717                         };
 718
 719                         emmc_bus8: emmc-bus8 {
 720                                 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>,
 721                                                 <1 RK_PD1 2 &pcfg_pull_default>,
 722                                                 <1 RK_PD2 2 &pcfg_pull_default>,
 723                                                 <1 RK_PD3 2 &pcfg_pull_default>,
 724                                                 <1 RK_PD4 2 &pcfg_pull_default>,
 725                                                 <1 RK_PD5 2 &pcfg_pull_default>,
 726                                                 <1 RK_PD6 2 &pcfg_pull_default>,
 727                                                 <1 RK_PD7 2 &pcfg_pull_default>;
 728                         };
 729                 };
 730
 731                 nfc {
 732                         flash_ale: flash-ale {
 733                                 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_default>;
 734                         };
 735
 736                         flash_bus8: flash-bus8 {
 737                                 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_default>,
 738                                                 <1 RK_PD1 1 &pcfg_pull_default>,
 739                                                 <1 RK_PD2 1 &pcfg_pull_default>,
 740                                                 <1 RK_PD3 1 &pcfg_pull_default>,
 741                                                 <1 RK_PD4 1 &pcfg_pull_default>,
 742                                                 <1 RK_PD5 1 &pcfg_pull_default>,
 743                                                 <1 RK_PD6 1 &pcfg_pull_default>,
 744                                                 <1 RK_PD7 1 &pcfg_pull_default>;
 745                         };
 746
 747                         flash_cle: flash-cle {
 748                                 rockchip,pins = <2 RK_PA1 1 &pcfg_pull_default>;
 749                         };
 750
 751                         flash_csn0: flash-csn0 {
 752                                 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_default>;
 753                         };
 754
 755                         flash_rdn: flash-rdn {
 756                                 rockchip,pins = <2 RK_PA3 1 &pcfg_pull_default>;
 757                         };
 758
 759                         flash_rdy: flash-rdy {
 760                                 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_default>;
 761                         };
 762
 763                         flash_wrn: flash-wrn {
 764                                 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_default>;
 765                         };
 766                 };
 767
 768                 emac {
 769                         emac_xfer: emac-xfer {
 770                                 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_default>, /* crs_dvalid */
 771                                                 <2 RK_PB5 1 &pcfg_pull_default>, /* tx_en */
 772                                                 <2 RK_PB6 1 &pcfg_pull_default>, /* mac_clk */
 773                                                 <2 RK_PB7 1 &pcfg_pull_default>, /* rx_err */
 774                                                 <2 RK_PC0 1 &pcfg_pull_default>, /* rxd1 */
 775                                                 <2 RK_PC1 1 &pcfg_pull_default>, /* rxd0 */
 776                                                 <2 RK_PC2 1 &pcfg_pull_default>, /* txd1 */
 777                                                 <2 RK_PC3 1 &pcfg_pull_default>; /* txd0 */
 778                         };
 779
 780                         emac_mdio: emac-mdio {
 781                                 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_default>, /* mac_md */
 782                                                 <2 RK_PD1 1 &pcfg_pull_default>; /* mac_mdclk */
 783                         };
 784                 };
 785
 786                 i2c0 {
 787                         i2c0_xfer: i2c0-xfer {
 788                                 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
 789                                                 <0 RK_PA1 1 &pcfg_pull_none>;
 790                         };
 791                 };
 792
 793                 i2c1 {
 794                         i2c1_xfer: i2c1-xfer {
 795                                 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
 796                                                 <0 RK_PA3 1 &pcfg_pull_none>;
 797                         };
 798                 };
 799
 800                 i2c2 {
 801                         i2c2_xfer: i2c2-xfer {
 802                                 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>,
 803                                                 <2 RK_PC5 1 &pcfg_pull_none>;
 804                         };
 805                 };
 806
 807                 i2s {
 808                         i2s_bus: i2s-bus {
 809                                 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>,
 810                                                 <1 RK_PA1 1 &pcfg_pull_default>,
 811                                                 <1 RK_PA2 1 &pcfg_pull_default>,
 812                                                 <1 RK_PA3 1 &pcfg_pull_default>,
 813                                                 <1 RK_PA4 1 &pcfg_pull_default>,
 814                                                 <1 RK_PA5 1 &pcfg_pull_default>;
 815                         };
 816                 };
 817
 818                 hdmi {
 819                         hdmi_ctl: hdmi-ctl {
 820                                 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>,
 821                                                 <1 RK_PB1 1 &pcfg_pull_none>,
 822                                                 <1 RK_PB2 1 &pcfg_pull_none>,
 823                                                 <1 RK_PB3 1 &pcfg_pull_none>;
 824                         };
 825                 };
 826
 827                 uart0 {
 828                         uart0_xfer: uart0-xfer {
 829                                 rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>,
 830                                                 <0 RK_PC1 1 &pcfg_pull_none>;
 831                         };
 832
 833                         uart0_cts: uart0-cts {
 834                                 rockchip,pins = <0 RK_PC2 1 &pcfg_pull_default>;
 835                         };
 836
 837                         uart0_rts: uart0-rts {
 838                                 rockchip,pins = <0 RK_PC3 1 &pcfg_pull_none>;
 839                         };
 840                 };
 841
 842                 uart1 {
 843                         uart1_xfer: uart1-xfer {
 844                                 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_default>,
 845                                                 <2 RK_PC7 1 &pcfg_pull_none>;
 846                         };
 847                         /* no rts / cts for uart1 */
 848                 };
 849
 850                 uart2 {
 851                         uart2_xfer: uart2-xfer {
 852                                 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>,
 853                                                 <1 RK_PC3 2 &pcfg_pull_none>;
 854                         };
 855                         /* no rts / cts for uart2 */
 856                 };
 857
 858                 spi-pins {
 859                         spi_txd:spi-txd {
 860                                 rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>;
 861                         };
 862
 863                         spi_rxd:spi-rxd {
 864                                 rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>;
 865                         };
 866
 867                         spi_clk:spi-clk {
 868                                 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>;
 869                         };
 870
 871                         spi_cs0:spi-cs0 {
 872                                 rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>;
 873
 874                         };
 875
 876                         spi_cs1:spi-cs1 {
 877                                 rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>;
 878
 879                         };
 880                 };
 881         };
 882 };