dts/upstream/src/arm/nxp/imx/imx6sx-sdb.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Copyright (C) 2014 Freescale Semiconductor, Inc.
   4
   5 /dts-v1/;
   6
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/input/input.h>
   9 #include "imx6sx.dtsi"
  10
  11 / {
  12         model = "Freescale i.MX6 SoloX SDB Board";
  13         compatible = "fsl,imx6sx-sdb", "fsl,imx6sx";
  14
  15         chosen {
  16                 stdout-path = &uart1;
  17         };
  18
  19         memory@80000000 {
  20                 device_type = "memory";
  21                 reg = <0x80000000 0x40000000>;
  22         };
  23
  24         backlight_display: backlight-display {
  25                 compatible = "pwm-backlight";
  26                 pwms = <&pwm3 0 5000000 0>;
  27                 brightness-levels = <0 4 8 16 32 64 128 255>;
  28                 default-brightness-level = <6>;
  29         };
  30
  31         gpio-keys {
  32                 compatible = "gpio-keys";
  33                 pinctrl-names = "default";
  34                 pinctrl-0 = <&pinctrl_gpio_keys>;
  35
  36                 volume-up {
  37                         label = "Volume Up";
  38                         gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
  39                         linux,code = <KEY_VOLUMEUP>;
  40                         wakeup-source;
  41                 };
  42
  43                 volume-down {
  44                         label = "Volume Down";
  45                         gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
  46                         linux,code = <KEY_VOLUMEDOWN>;
  47                         wakeup-source;
  48                 };
  49         };
  50
  51         vcc_sd3: regulator-vcc-sd3 {
  52                 compatible = "regulator-fixed";
  53                 pinctrl-names = "default";
  54                 pinctrl-0 = <&pinctrl_vcc_sd3>;
  55                 regulator-name = "VCC_SD3";
  56                 regulator-min-microvolt = <3000000>;
  57                 regulator-max-microvolt = <3000000>;
  58                 gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
  59                 enable-active-high;
  60         };
  61
  62         reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
  63                 compatible = "regulator-fixed";
  64                 pinctrl-names = "default";
  65                 pinctrl-0 = <&pinctrl_usb_otg1>;
  66                 regulator-name = "usb_otg1_vbus";
  67                 regulator-min-microvolt = <5000000>;
  68                 regulator-max-microvolt = <5000000>;
  69                 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
  70                 enable-active-high;
  71         };
  72
  73         reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
  74                 compatible = "regulator-fixed";
  75                 pinctrl-names = "default";
  76                 pinctrl-0 = <&pinctrl_usb_otg2>;
  77                 regulator-name = "usb_otg2_vbus";
  78                 regulator-min-microvolt = <5000000>;
  79                 regulator-max-microvolt = <5000000>;
  80                 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
  81                 enable-active-high;
  82         };
  83
  84         reg_psu_5v: regulator-psu-5v {
  85                 compatible = "regulator-fixed";
  86                 regulator-name = "PSU-5V0";
  87                 regulator-min-microvolt = <5000000>;
  88                 regulator-max-microvolt = <5000000>;
  89         };
  90
  91         reg_lcd_3v3: regulator-lcd-3v3 {
  92                 compatible = "regulator-fixed";
  93                 regulator-name = "lcd-3v3";
  94                 gpio = <&gpio3 27 0>;
  95                 enable-active-high;
  96         };
  97
  98         reg_peri_3v3: regulator-peri-3v3 {
  99                 compatible = "regulator-fixed";
 100                 pinctrl-names = "default";
 101                 pinctrl-0 = <&pinctrl_peri_3v3>;
 102                 regulator-name = "peri_3v3";
 103                 regulator-min-microvolt = <3300000>;
 104                 regulator-max-microvolt = <3300000>;
 105                 gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>;
 106                 enable-active-high;
 107                 regulator-always-on;
 108         };
 109
 110         reg_enet_3v3: regulator-enet-3v3 {
 111                 compatible = "regulator-fixed";
 112                 pinctrl-names = "default";
 113                 pinctrl-0 = <&pinctrl_enet_3v3>;
 114                 regulator-name = "enet_3v3";
 115                 regulator-min-microvolt = <3300000>;
 116                 regulator-max-microvolt = <3300000>;
 117                 gpio = <&gpio2 6 GPIO_ACTIVE_LOW>;
 118                 regulator-boot-on;
 119                 regulator-always-on;
 120         };
 121
 122         reg_pcie_gpio: regulator-pcie-gpio {
 123                 compatible = "regulator-fixed";
 124                 pinctrl-names = "default";
 125                 pinctrl-0 = <&pinctrl_pcie_reg>;
 126                 regulator-name = "MPCIE_3V3";
 127                 regulator-min-microvolt = <3300000>;
 128                 regulator-max-microvolt = <3300000>;
 129                 gpio = <&gpio2 1 GPIO_ACTIVE_HIGH>;
 130                 enable-active-high;
 131         };
 132
 133         reg_lcd_5v: regulator-lcd-5v {
 134                 compatible = "regulator-fixed";
 135                 regulator-name = "lcd-5v0";
 136                 regulator-min-microvolt = <5000000>;
 137                 regulator-max-microvolt = <5000000>;
 138         };
 139
 140         reg_can_en: regulator-can-en {
 141                 compatible = "regulator-fixed";
 142                 regulator-name = "can-en";
 143                 regulator-min-microvolt = <3300000>;
 144                 regulator-max-microvolt = <3300000>;
 145         };
 146
 147         reg_can_stby: regulator-can-stby {
 148                 compatible = "regulator-fixed";
 149                 regulator-name = "can-stby";
 150                 regulator-min-microvolt = <3300000>;
 151                 regulator-max-microvolt = <3300000>;
 152         };
 153
 154         sound {
 155                 compatible = "fsl,imx6sx-sdb-wm8962", "fsl,imx-audio-wm8962";
 156                 pinctrl-names = "default";
 157                 pinctrl-0 = <&pinctrl_hp>;
 158                 model = "wm8962-audio";
 159                 ssi-controller = <&ssi2>;
 160                 audio-codec = <&codec>;
 161                 audio-routing =
 162                         "Headphone Jack", "HPOUTL",
 163                         "Headphone Jack", "HPOUTR",
 164                         "Ext Spk", "SPKOUTL",
 165                         "Ext Spk", "SPKOUTR",
 166                         "AMIC", "MICBIAS",
 167                         "IN3R", "AMIC";
 168                 mux-int-port = <2>;
 169                 mux-ext-port = <6>;
 170                 hp-det-gpio = <&gpio1 17 GPIO_ACTIVE_LOW>;
 171         };
 172
 173         panel {
 174                 compatible = "sii,43wvf1g";
 175                 backlight = <&backlight_display>;
 176                 dvdd-supply = <&reg_lcd_3v3>;
 177                 avdd-supply = <&reg_lcd_5v>;
 178
 179                 port {
 180                         panel_in: endpoint {
 181                                 remote-endpoint = <&display_out>;
 182                         };
 183                 };
 184         };
 185
 186         spdif_out: spdif-out {
 187                 compatible = "linux,spdif-dit";
 188                 #sound-dai-cells = <0>;
 189         };
 190
 191         sound-spdif {
 192                 compatible = "fsl,imx6sx-sdb-spdif",
 193                              "fsl,imx-audio-spdif";
 194                 model = "imx-spdif";
 195                 audio-cpu = <&spdif>;
 196                 audio-codec = <&spdif_out>;
 197         };
 198
 199 };
 200
 201 &audmux {
 202         pinctrl-names = "default";
 203         pinctrl-0 = <&pinctrl_audmux>;
 204         status = "okay";
 205 };
 206
 207 &fec1 {
 208         pinctrl-names = "default";
 209         pinctrl-0 = <&pinctrl_enet1>;
 210         phy-supply = <&reg_enet_3v3>;
 211         phy-mode = "rgmii-id";
 212         phy-handle = <&ethphy1>;
 213         phy-reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
 214         fsl,magic-packet;
 215         status = "okay";
 216
 217         mdio {
 218                 #address-cells = <1>;
 219                 #size-cells = <0>;
 220
 221                 ethphy1: ethernet-phy@1 {
 222                         reg = <1>;
 223                 };
 224
 225                 ethphy2: ethernet-phy@2 {
 226                         reg = <2>;
 227                 };
 228         };
 229 };
 230
 231 &fec2 {
 232         pinctrl-names = "default";
 233         pinctrl-0 = <&pinctrl_enet2>;
 234         phy-mode = "rgmii-id";
 235         phy-handle = <&ethphy2>;
 236         fsl,magic-packet;
 237         status = "okay";
 238 };
 239
 240 &flexcan1 {
 241         pinctrl-names = "default";
 242         pinctrl-0 = <&pinctrl_flexcan1>;
 243         xceiver-supply = <&reg_can_stby>;
 244         status = "okay";
 245 };
 246
 247 &flexcan2 {
 248         pinctrl-names = "default";
 249         pinctrl-0 = <&pinctrl_flexcan2>;
 250         xceiver-supply = <&reg_can_stby>;
 251         status = "okay";
 252 };
 253
 254 &i2c3 {
 255         clock-frequency = <100000>;
 256         pinctrl-names = "default";
 257         pinctrl-0 = <&pinctrl_i2c3>;
 258         status = "okay";
 259 };
 260
 261 &i2c4 {
 262         clock-frequency = <100000>;
 263         pinctrl-names = "default";
 264         pinctrl-0 = <&pinctrl_i2c4>;
 265         status = "okay";
 266
 267         codec: wm8962@1a {
 268                 compatible = "wlf,wm8962";
 269                 reg = <0x1a>;
 270                 clocks = <&clks IMX6SX_CLK_AUDIO>;
 271                 DCVDD-supply = <&vgen4_reg>;
 272                 DBVDD-supply = <&vgen4_reg>;
 273                 AVDD-supply = <&vgen4_reg>;
 274                 CPVDD-supply = <&vgen4_reg>;
 275                 MICVDD-supply = <&vgen3_reg>;
 276                 PLLVDD-supply = <&vgen4_reg>;
 277                 SPKVDD1-supply = <&reg_psu_5v>;
 278                 SPKVDD2-supply = <&reg_psu_5v>;
 279         };
 280 };
 281
 282 &pcie {
 283         pinctrl-names = "default";
 284         pinctrl-0 = <&pinctrl_pcie>;
 285         reset-gpio = <&gpio2 0 GPIO_ACTIVE_LOW>;
 286         vpcie-supply = <&reg_pcie_gpio>;
 287         status = "okay";
 288 };
 289
 290 &lcdif1 {
 291         pinctrl-names = "default";
 292         pinctrl-0 = <&pinctrl_lcd>;
 293         status = "okay";
 294
 295         port {
 296                 display_out: endpoint {
 297                         remote-endpoint = <&panel_in>;
 298                 };
 299         };
 300 };
 301
 302 &pwm3 {
 303         pinctrl-names = "default";
 304         pinctrl-0 = <&pinctrl_pwm3>;
 305 };
 306
 307 &snvs_poweroff {
 308         status = "okay";
 309 };
 310
 311 &sai1 {
 312         pinctrl-names = "default";
 313         pinctrl-0 = <&pinctrl_sai1>;
 314         status = "disabled";
 315 };
 316
 317 &spdif {
 318         pinctrl-names = "default";
 319         pinctrl-0 = <&pinctrl_spdif>;
 320         assigned-clocks = <&clks IMX6SX_CLK_SPDIF_PODF>;
 321         assigned-clock-rates = <24576000>;
 322         status = "okay";
 323 };
 324
 325 &ssi2 {
 326         status = "okay";
 327 };
 328
 329 &uart1 {
 330         pinctrl-names = "default";
 331         pinctrl-0 = <&pinctrl_uart1>;
 332         status = "okay";
 333 };
 334
 335 &uart5 { /* for bluetooth */
 336         pinctrl-names = "default";
 337         pinctrl-0 = <&pinctrl_uart5>;
 338         uart-has-rtscts;
 339         status = "okay";
 340 };
 341
 342 &usbotg1 {
 343         vbus-supply = <&reg_usb_otg1_vbus>;
 344         pinctrl-names = "default";
 345         pinctrl-0 = <&pinctrl_usb_otg1_id>;
 346         status = "okay";
 347 };
 348
 349 &usbotg2 {
 350         vbus-supply = <&reg_usb_otg2_vbus>;
 351         dr_mode = "host";
 352         status = "okay";
 353 };
 354
 355 &usbphy1 {
 356         fsl,tx-d-cal = <106>;
 357 };
 358
 359 &usbphy2 {
 360         fsl,tx-d-cal = <106>;
 361 };
 362
 363 &usdhc2 {
 364         pinctrl-names = "default";
 365         pinctrl-0 = <&pinctrl_usdhc2>;
 366         non-removable;
 367         no-1-8-v;
 368         keep-power-in-suspend;
 369         wakeup-source;
 370         status = "okay";
 371 };
 372
 373 &usdhc3 {
 374         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 375         pinctrl-0 = <&pinctrl_usdhc3>;
 376         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 377         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 378         bus-width = <8>;
 379         cd-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
 380         wp-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
 381         keep-power-in-suspend;
 382         wakeup-source;
 383         vmmc-supply = <&vcc_sd3>;
 384         status = "okay";
 385 };
 386
 387 &usdhc4 {
 388         pinctrl-names = "default";
 389         pinctrl-0 = <&pinctrl_usdhc4>;
 390         cd-gpios = <&gpio6 21 GPIO_ACTIVE_LOW>;
 391         wp-gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>;
 392         status = "okay";
 393 };
 394
 395 &wdog1 {
 396         pinctrl-names = "default";
 397         pinctrl-0 = <&pinctrl_wdog>;
 398         fsl,ext-reset-output;
 399 };
 400
 401 &iomuxc {
 402         imx6x-sdb {
 403                 pinctrl_audmux: audmuxgrp {
 404                         fsl,pins = <
 405                                 MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC   0x130b0
 406                                 MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS  0x130b0
 407                                 MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD    0x120b0
 408                                 MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD    0x130b0
 409                                 MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK       0x130b0
 410                         >;
 411                 };
 412
 413                 pinctrl_enet1: enet1grp {
 414                         fsl,pins = <
 415                                 MX6SX_PAD_ENET1_MDIO__ENET1_MDIO        0xa0b1
 416                                 MX6SX_PAD_ENET1_MDC__ENET1_MDC          0xa0b1
 417                                 MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC   0xa0b1
 418                                 MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0   0xa0b1
 419                                 MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1   0xa0b1
 420                                 MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2   0xa0b1
 421                                 MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3   0xa0b1
 422                                 MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN    0xa0b1
 423                                 MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK      0x3081
 424                                 MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0   0x3081
 425                                 MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1   0x3081
 426                                 MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2   0x3081
 427                                 MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3   0x3081
 428                                 MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN    0x3081
 429                                 MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M       0x91
 430                                 /* phy reset */
 431                                 MX6SX_PAD_ENET2_CRS__GPIO2_IO_7         0x10b0
 432                         >;
 433                 };
 434
 435                 pinctrl_enet_3v3: enet3v3grp {
 436                         fsl,pins = <
 437                                 MX6SX_PAD_ENET2_COL__GPIO2_IO_6         0x80000000
 438                         >;
 439                 };
 440
 441                 pinctrl_enet2: enet2grp {
 442                         fsl,pins = <
 443                                 MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC   0xa0b9
 444                                 MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0   0xa0b1
 445                                 MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1   0xa0b1
 446                                 MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2   0xa0b1
 447                                 MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3   0xa0b1
 448                                 MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN    0xa0b1
 449                                 MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK      0x3081
 450                                 MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0   0x3081
 451                                 MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1   0x3081
 452                                 MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2   0x3081
 453                                 MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3   0x3081
 454                                 MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN    0x3081
 455                         >;
 456                 };
 457
 458                 pinctrl_flexcan1: flexcan1grp {
 459                         fsl,pins = <
 460                                 MX6SX_PAD_QSPI1B_DQS__CAN1_TX           0x1b020
 461                                 MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX         0x1b020
 462                         >;
 463                 };
 464
 465                 pinctrl_flexcan2: flexcan2grp {
 466                         fsl,pins = <
 467                                 MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX         0x1b020
 468                                 MX6SX_PAD_QSPI1A_DQS__CAN2_TX           0x1b020
 469                         >;
 470                 };
 471
 472                 pinctrl_gpio_keys: gpio_keysgrp {
 473                         fsl,pins = <
 474                                 MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059
 475                                 MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x17059
 476                         >;
 477                 };
 478
 479                 pinctrl_hp: hpgrp {
 480                         fsl,pins = <
 481                                 MX6SX_PAD_CSI_DATA03__GPIO1_IO_17 0x17059
 482                         >;
 483                 };
 484
 485                 pinctrl_i2c1: i2c1grp {
 486                         fsl,pins = <
 487                                 MX6SX_PAD_GPIO1_IO01__I2C1_SDA          0x4001b8b1
 488                                 MX6SX_PAD_GPIO1_IO00__I2C1_SCL          0x4001b8b1
 489                         >;
 490                 };
 491
 492                 pinctrl_i2c3: i2c3grp {
 493                         fsl,pins = <
 494                                 MX6SX_PAD_KEY_ROW4__I2C3_SDA            0x4001b8b1
 495                                 MX6SX_PAD_KEY_COL4__I2C3_SCL            0x4001b8b1
 496                         >;
 497                 };
 498
 499                 pinctrl_i2c4: i2c4grp {
 500                         fsl,pins = <
 501                                 MX6SX_PAD_CSI_DATA07__I2C4_SDA          0x4001b8b1
 502                                 MX6SX_PAD_CSI_DATA06__I2C4_SCL          0x4001b8b1
 503                         >;
 504                 };
 505
 506                 pinctrl_lcd: lcdgrp {
 507                         fsl,pins = <
 508                                 MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0
 509                                 MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0
 510                                 MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0
 511                                 MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0
 512                                 MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0
 513                                 MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0
 514                                 MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0
 515                                 MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0
 516                                 MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0
 517                                 MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0
 518                                 MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0
 519                                 MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0
 520                                 MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0
 521                                 MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0
 522                                 MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0
 523                                 MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0
 524                                 MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0
 525                                 MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0
 526                                 MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0
 527                                 MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0
 528                                 MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0
 529                                 MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0
 530                                 MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0
 531                                 MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0
 532                                 MX6SX_PAD_LCD1_CLK__LCDIF1_CLK  0x4001b0b0
 533                                 MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0
 534                                 MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0
 535                                 MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0
 536                                 MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0
 537                         >;
 538                 };
 539
 540                 pinctrl_mqs: mqsgrp {
 541                         fsl,pins = <
 542                                 MX6SX_PAD_SD2_CLK__MQS_RIGHT 0x120b0
 543                                 MX6SX_PAD_SD2_CMD__MQS_LEFT  0x120b0
 544                         >;
 545                 };
 546
 547                 pinctrl_pcie: pciegrp {
 548                         fsl,pins = <
 549                                 MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x10b0
 550                         >;
 551                 };
 552
 553                 pinctrl_pcie_reg: pciereggrp {
 554                         fsl,pins = <
 555                                 MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0x10b0
 556                         >;
 557                 };
 558
 559                 pinctrl_peri_3v3: peri3v3grp {
 560                         fsl,pins = <
 561                                 MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16     0x80000000
 562                         >;
 563                 };
 564
 565                 pinctrl_pwm3: pwm3grp-1 {
 566                         fsl,pins = <
 567                                 MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0
 568                         >;
 569                 };
 570
 571                 pinctrl_qspi2: qspi2grp {
 572                         fsl,pins = <
 573                                 MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0     0x70f1
 574                                 MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1  0x70f1
 575                                 MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2    0x70f1
 576                                 MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3    0x70f1
 577                                 MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK        0x70f1
 578                                 MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B       0x70f1
 579                                 MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0   0x70f1
 580                                 MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1   0x70f1
 581                                 MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2     0x70f1
 582                                 MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3     0x70f1
 583                                 MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK     0x70f1
 584                                 MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B    0x70f1
 585                         >;
 586                 };
 587
 588                 pinctrl_vcc_sd3: vccsd3grp {
 589                         fsl,pins = <
 590                                 MX6SX_PAD_KEY_COL1__GPIO2_IO_11         0x17059
 591                         >;
 592                 };
 593
 594                 pinctrl_sai1: sai1grp {
 595                         fsl,pins = <
 596                                 MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK      0x130b0
 597                                 MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC      0x130b0
 598                                 MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0     0x120b0
 599                                 MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0     0x130b0
 600                                 MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK       0x130b0
 601                         >;
 602                 };
 603
 604                 pinctrl_spdif: spdifgrp {
 605                         fsl,pins = <
 606                                 MX6SX_PAD_SD4_DATA4__SPDIF_OUT          0x1b0b0
 607                         >;
 608                 };
 609
 610                 pinctrl_uart1: uart1grp {
 611                         fsl,pins = <
 612                                 MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX      0x1b0b1
 613                                 MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX      0x1b0b1
 614                         >;
 615                 };
 616
 617                 pinctrl_uart5: uart5grp {
 618                         fsl,pins = <
 619                                 MX6SX_PAD_KEY_ROW3__UART5_DCE_RX        0x1b0b1
 620                                 MX6SX_PAD_KEY_COL3__UART5_DCE_TX        0x1b0b1
 621                                 MX6SX_PAD_KEY_ROW2__UART5_DCE_CTS       0x1b0b1
 622                                 MX6SX_PAD_KEY_COL2__UART5_DCE_RTS       0x1b0b1
 623                         >;
 624                 };
 625
 626                 pinctrl_usb_otg1: usbotg1grp {
 627                         fsl,pins = <
 628                                 MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9        0x10b0
 629                         >;
 630                 };
 631
 632                 pinctrl_usb_otg1_id: usbotg1idgrp {
 633                         fsl,pins = <
 634                                 MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID    0x17059
 635                         >;
 636                 };
 637
 638                 pinctrl_usb_otg2: usbot2ggrp {
 639                         fsl,pins = <
 640                                 MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12       0x10b0
 641                         >;
 642                 };
 643
 644                 pinctrl_usdhc2: usdhc2grp {
 645                         fsl,pins = <
 646                                 MX6SX_PAD_SD2_CMD__USDHC2_CMD           0x17059
 647                                 MX6SX_PAD_SD2_CLK__USDHC2_CLK           0x10059
 648                                 MX6SX_PAD_SD2_DATA0__USDHC2_DATA0       0x17059
 649                                 MX6SX_PAD_SD2_DATA1__USDHC2_DATA1       0x17059
 650                                 MX6SX_PAD_SD2_DATA2__USDHC2_DATA2       0x17059
 651                                 MX6SX_PAD_SD2_DATA3__USDHC2_DATA3       0x17059
 652                         >;
 653                 };
 654
 655                 pinctrl_usdhc3: usdhc3grp {
 656                         fsl,pins = <
 657                                 MX6SX_PAD_SD3_CMD__USDHC3_CMD           0x17059
 658                                 MX6SX_PAD_SD3_CLK__USDHC3_CLK           0x10059
 659                                 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0       0x17059
 660                                 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1       0x17059
 661                                 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2       0x17059
 662                                 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3       0x17059
 663                                 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4       0x17059
 664                                 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5       0x17059
 665                                 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6       0x17059
 666                                 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7       0x17059
 667                                 MX6SX_PAD_KEY_COL0__GPIO2_IO_10         0x17059 /* CD */
 668                                 MX6SX_PAD_KEY_ROW0__GPIO2_IO_15         0x17059 /* WP */
 669                         >;
 670                 };
 671
 672                 pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
 673                         fsl,pins = <
 674                                 MX6SX_PAD_SD3_CMD__USDHC3_CMD           0x170b9
 675                                 MX6SX_PAD_SD3_CLK__USDHC3_CLK           0x100b9
 676                                 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0       0x170b9
 677                                 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1       0x170b9
 678                                 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2       0x170b9
 679                                 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3       0x170b9
 680                                 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4       0x170b9
 681                                 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5       0x170b9
 682                                 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6       0x170b9
 683                                 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7       0x170b9
 684                         >;
 685                 };
 686
 687                 pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
 688                         fsl,pins = <
 689                                 MX6SX_PAD_SD3_CMD__USDHC3_CMD           0x170f9
 690                                 MX6SX_PAD_SD3_CLK__USDHC3_CLK           0x100f9
 691                                 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0       0x170f9
 692                                 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1       0x170f9
 693                                 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2       0x170f9
 694                                 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3       0x170f9
 695                                 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4       0x170f9
 696                                 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5       0x170f9
 697                                 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6       0x170f9
 698                                 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7       0x170f9
 699                         >;
 700                 };
 701
 702                 pinctrl_usdhc4: usdhc4grp {
 703                         fsl,pins = <
 704                                 MX6SX_PAD_SD4_CMD__USDHC4_CMD           0x17059
 705                                 MX6SX_PAD_SD4_CLK__USDHC4_CLK           0x10059
 706                                 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0       0x17059
 707                                 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1       0x17059
 708                                 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2       0x17059
 709                                 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3       0x17059
 710                                 MX6SX_PAD_SD4_DATA7__GPIO6_IO_21        0x17059 /* CD */
 711                                 MX6SX_PAD_SD4_DATA6__GPIO6_IO_20        0x17059 /* WP */
 712                         >;
 713                 };
 714
 715                 pinctrl_wdog: wdoggrp {
 716                         fsl,pins = <
 717                                 MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x30b0
 718                         >;
 719                 };
 720         };
 721 };