dts/upstream/Bindings/watchdog/qcom-wdt.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/watchdog/qcom-wdt.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Krait Processor Sub-system (KPSS) Watchdog timer
   8
   9 maintainers:
  10   - Rajendra Nayak <[email protected]>
  11
  12 properties:
  13   $nodename:
  14     pattern: "^(watchdog|timer)@[0-9a-f]+$"
  15
  16   compatible:
  17     oneOf:
  18       - items:
  19           - enum:
  20               - qcom,kpss-wdt-ipq4019
  21               - qcom,apss-wdt-ipq5018
  22               - qcom,apss-wdt-ipq5332
  23               - qcom,apss-wdt-ipq9574
  24               - qcom,apss-wdt-msm8226
  25               - qcom,apss-wdt-msm8974
  26               - qcom,apss-wdt-msm8994
  27               - qcom,apss-wdt-qcm2290
  28               - qcom,apss-wdt-qcs404
  29               - qcom,apss-wdt-sa8255p
  30               - qcom,apss-wdt-sa8775p
  31               - qcom,apss-wdt-sc7180
  32               - qcom,apss-wdt-sc7280
  33               - qcom,apss-wdt-sc8180x
  34               - qcom,apss-wdt-sc8280xp
  35               - qcom,apss-wdt-sdm845
  36               - qcom,apss-wdt-sdx55
  37               - qcom,apss-wdt-sdx65
  38               - qcom,apss-wdt-sm6115
  39               - qcom,apss-wdt-sm6350
  40               - qcom,apss-wdt-sm8150
  41               - qcom,apss-wdt-sm8250
  42           - const: qcom,kpss-wdt
  43       - const: qcom,kpss-wdt
  44         deprecated: true
  45       - items:
  46           - const: qcom,scss-timer
  47           - const: qcom,msm-timer
  48       - items:
  49           - enum:
  50               - qcom,kpss-wdt-apq8064
  51               - qcom,kpss-wdt-ipq8064
  52               - qcom,kpss-wdt-mdm9615
  53               - qcom,kpss-wdt-msm8960
  54           - const: qcom,kpss-timer
  55           - const: qcom,msm-timer
  56
  57   reg:
  58     maxItems: 1
  59
  60   clocks:
  61     maxItems: 1
  62
  63   clock-names:
  64     items:
  65       - const: sleep
  66
  67   clock-frequency:
  68     description:
  69       The frequency of the general purpose timer in Hz.
  70
  71   cpu-offset:
  72     $ref: /schemas/types.yaml#/definitions/uint32
  73     description:
  74       Per-CPU offset used when the timer is accessed without the CPU remapping
  75       facilities. The offset is cpu-offset + (0x10000 * cpu-nr).
  76
  77   interrupts:
  78     minItems: 1
  79     maxItems: 5
  80
  81 required:
  82   - compatible
  83   - reg
  84   - clocks
  85
  86 allOf:
  87   - $ref: watchdog.yaml#
  88
  89   - if:
  90       properties:
  91         compatible:
  92           contains:
  93             const: qcom,kpss-wdt
  94     then:
  95       properties:
  96         clock-frequency: false
  97         cpu-offset: false
  98         interrupts:
  99           minItems: 1
 100           items:
 101             - description: Bark
 102             - description: Bite
 103
 104     else:
 105       properties:
 106         interrupts:
 107           minItems: 3
 108           items:
 109             - description: Debug
 110             - description: First general purpose timer
 111             - description: Second general purpose timer
 112             - description: First watchdog
 113             - description: Second watchdog
 114       required:
 115         - clock-frequency
 116
 117 unevaluatedProperties: false
 118
 119 examples:
 120   - |
 121     #include <dt-bindings/interrupt-controller/arm-gic.h>
 122
 123     watchdog@17c10000 {
 124         compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt";
 125         reg = <0x17c10000 0x1000>;
 126         clocks = <&sleep_clk>;
 127         interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
 128         timeout-sec = <10>;
 129     };
 130
 131   - |
 132     #include <dt-bindings/interrupt-controller/arm-gic.h>
 133
 134     watchdog@200a000 {
 135         compatible = "qcom,kpss-wdt-ipq8064", "qcom,kpss-timer", "qcom,msm-timer";
 136         interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
 137                      <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
 138                      <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
 139                      <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
 140                      <GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
 141         reg = <0x0200a000 0x100>;
 142         clock-frequency = <25000000>;
 143         clocks = <&sleep_clk>;
 144         clock-names = "sleep";
 145         cpu-offset = <0x80000>;
 146     };