board/dhelectronics/dh_imx6/dh_imx6_spl.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * DHCOM DH-iMX6 PDK SPL support
   4  *
   5  * Copyright (C) 2017 Marek Vasut <[email protected]>
   6  */
   7
   8 #include <common.h>
   9 #include <init.h>
  10 #include <asm/arch/clock.h>
  11 #include <asm/arch/crm_regs.h>
  12 #include <asm/arch/imx-regs.h>
  13 #include <asm/arch/iomux.h>
  14 #include <asm/arch/mx6-ddr.h>
  15 #include <asm/arch/mx6-pins.h>
  16 #include <asm/arch/sys_proto.h>
  17 #include <asm/gpio.h>
  18 #include <asm/mach-imx/boot_mode.h>
  19 #include <asm/mach-imx/iomux-v3.h>
  20 #include <asm/mach-imx/mxc_i2c.h>
  21 #include <asm/io.h>
  22 #include <errno.h>
  23 #include <fuse.h>
  24 #include <fsl_esdhc_imx.h>
  25 #include <i2c.h>
  26 #include <mmc.h>
  27 #include <spl.h>
  28
  29 #define ENET_PAD_CTRL                                                   \
  30         (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |  \
  31          PAD_CTL_HYS)
  32
  33 #define GPIO_PAD_CTRL                                                   \
  34         (PAD_CTL_HYS | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
  35
  36 #define SPI_PAD_CTRL                                                    \
  37         (PAD_CTL_HYS | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |          \
  38         PAD_CTL_SRE_FAST)
  39
  40 #define UART_PAD_CTRL                                                   \
  41         (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |  \
  42          PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  43
  44 #define USDHC_PAD_CTRL                                                  \
  45         (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |   \
  46          PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  47
  48 static const struct mx6dq_iomux_ddr_regs dhcom6dq_ddr_ioregs = {
  49         .dram_sdclk_0   = 0x00020030,
  50         .dram_sdclk_1   = 0x00020030,
  51         .dram_cas       = 0x00020030,
  52         .dram_ras       = 0x00020030,
  53         .dram_reset     = 0x00020030,
  54         .dram_sdcke0    = 0x00003000,
  55         .dram_sdcke1    = 0x00003000,
  56         .dram_sdba2     = 0x00000000,
  57         .dram_sdodt0    = 0x00003030,
  58         .dram_sdodt1    = 0x00003030,
  59         .dram_sdqs0     = 0x00000030,
  60         .dram_sdqs1     = 0x00000030,
  61         .dram_sdqs2     = 0x00000030,
  62         .dram_sdqs3     = 0x00000030,
  63         .dram_sdqs4     = 0x00000030,
  64         .dram_sdqs5     = 0x00000030,
  65         .dram_sdqs6     = 0x00000030,
  66         .dram_sdqs7     = 0x00000030,
  67         .dram_dqm0      = 0x00020030,
  68         .dram_dqm1      = 0x00020030,
  69         .dram_dqm2      = 0x00020030,
  70         .dram_dqm3      = 0x00020030,
  71         .dram_dqm4      = 0x00020030,
  72         .dram_dqm5      = 0x00020030,
  73         .dram_dqm6      = 0x00020030,
  74         .dram_dqm7      = 0x00020030,
  75 };
  76
  77 static const struct mx6dq_iomux_grp_regs dhcom6dq_grp_ioregs = {
  78         .grp_ddr_type   = 0x000C0000,
  79         .grp_ddrmode_ctl = 0x00020000,
  80         .grp_ddrpke     = 0x00000000,
  81         .grp_addds      = 0x00000030,
  82         .grp_ctlds      = 0x00000030,
  83         .grp_ddrmode    = 0x00020000,
  84         .grp_b0ds       = 0x00000030,
  85         .grp_b1ds       = 0x00000030,
  86         .grp_b2ds       = 0x00000030,
  87         .grp_b3ds       = 0x00000030,
  88         .grp_b4ds       = 0x00000030,
  89         .grp_b5ds       = 0x00000030,
  90         .grp_b6ds       = 0x00000030,
  91         .grp_b7ds       = 0x00000030,
  92 };
  93
  94 static const struct mx6sdl_iomux_ddr_regs dhcom6sdl_ddr_ioregs = {
  95         .dram_sdclk_0   = 0x00020030,
  96         .dram_sdclk_1   = 0x00020030,
  97         .dram_cas       = 0x00020030,
  98         .dram_ras       = 0x00020030,
  99         .dram_reset     = 0x00020030,
 100         .dram_sdcke0    = 0x00003000,
 101         .dram_sdcke1    = 0x00003000,
 102         .dram_sdba2     = 0x00000000,
 103         .dram_sdodt0    = 0x00003030,
 104         .dram_sdodt1    = 0x00003030,
 105         .dram_sdqs0     = 0x00000030,
 106         .dram_sdqs1     = 0x00000030,
 107         .dram_sdqs2     = 0x00000030,
 108         .dram_sdqs3     = 0x00000030,
 109         .dram_sdqs4     = 0x00000030,
 110         .dram_sdqs5     = 0x00000030,
 111         .dram_sdqs6     = 0x00000030,
 112         .dram_sdqs7     = 0x00000030,
 113         .dram_dqm0      = 0x00020030,
 114         .dram_dqm1      = 0x00020030,
 115         .dram_dqm2      = 0x00020030,
 116         .dram_dqm3      = 0x00020030,
 117         .dram_dqm4      = 0x00020030,
 118         .dram_dqm5      = 0x00020030,
 119         .dram_dqm6      = 0x00020030,
 120         .dram_dqm7      = 0x00020030,
 121 };
 122
 123 static const struct mx6sdl_iomux_grp_regs dhcom6sdl_grp_ioregs = {
 124         .grp_ddr_type   = 0x000C0000,
 125         .grp_ddrmode_ctl = 0x00020000,
 126         .grp_ddrpke     = 0x00000000,
 127         .grp_addds      = 0x00000030,
 128         .grp_ctlds      = 0x00000030,
 129         .grp_ddrmode    = 0x00020000,
 130         .grp_b0ds       = 0x00000030,
 131         .grp_b1ds       = 0x00000030,
 132         .grp_b2ds       = 0x00000030,
 133         .grp_b3ds       = 0x00000030,
 134         .grp_b4ds       = 0x00000030,
 135         .grp_b5ds       = 0x00000030,
 136         .grp_b6ds       = 0x00000030,
 137         .grp_b7ds       = 0x00000030,
 138 };
 139
 140 static const struct mx6_mmdc_calibration dhcom_mmdc_calib_4x4g_1066 = {
 141         .p0_mpwldectrl0 = 0x00150019,
 142         .p0_mpwldectrl1 = 0x001C000B,
 143         .p1_mpwldectrl0 = 0x00020018,
 144         .p1_mpwldectrl1 = 0x0002000C,
 145         .p0_mpdgctrl0   = 0x43140320,
 146         .p0_mpdgctrl1   = 0x03080304,
 147         .p1_mpdgctrl0   = 0x43180320,
 148         .p1_mpdgctrl1   = 0x03100254,
 149         .p0_mprddlctl   = 0x4830383C,
 150         .p1_mprddlctl   = 0x3836323E,
 151         .p0_mpwrdlctl   = 0x3E444642,
 152         .p1_mpwrdlctl   = 0x42344442,
 153 };
 154
 155 static const struct mx6_mmdc_calibration dhcom_mmdc_calib_2x4g_800 = {
 156         .p0_mpwldectrl0 = 0x0040003C,
 157         .p0_mpwldectrl1 = 0x0032003E,
 158         .p0_mpdgctrl0   = 0x42350231,
 159         .p0_mpdgctrl1   = 0x021A0218,
 160         .p0_mprddlctl   = 0x4B4B4E49,
 161         .p0_mpwrdlctl   = 0x3F3F3035,
 162 };
 163
 164 static const struct mx6_mmdc_calibration dhcom_mmdc_calib_4x2g_1066 = {
 165         .p0_mpwldectrl0 = 0x001a001a,
 166         .p0_mpwldectrl1 = 0x00260015,
 167         .p0_mpdgctrl0   = 0x030c0320,
 168         .p0_mpdgctrl1   = 0x03100304,
 169         .p0_mprddlctl   = 0x432e3538,
 170         .p0_mpwrdlctl   = 0x363f423d,
 171         .p1_mpwldectrl0 = 0x0006001e,
 172         .p1_mpwldectrl1 = 0x00050015,
 173         .p1_mpdgctrl0   = 0x031c0324,
 174         .p1_mpdgctrl1   = 0x030c0258,
 175         .p1_mprddlctl   = 0x3834313f,
 176         .p1_mpwrdlctl   = 0x47374a42,
 177 };
 178
 179 static const struct mx6_mmdc_calibration dhcom_mmdc_calib_4x2g_800 = {
 180         .p0_mpwldectrl0 = 0x003A003A,
 181         .p0_mpwldectrl1 = 0x0030002F,
 182         .p1_mpwldectrl0 = 0x002F0038,
 183         .p1_mpwldectrl1 = 0x00270039,
 184         .p0_mpdgctrl0   = 0x420F020F,
 185         .p0_mpdgctrl1   = 0x01760175,
 186         .p1_mpdgctrl0   = 0x41640171,
 187         .p1_mpdgctrl1   = 0x015E0160,
 188         .p0_mprddlctl   = 0x45464B4A,
 189         .p1_mprddlctl   = 0x49484A46,
 190         .p0_mpwrdlctl   = 0x40402E32,
 191         .p1_mpwrdlctl   = 0x3A3A3231,
 192 };
 193
 194 static const struct mx6_mmdc_calibration dhcom_mmdc_calib_2x2g_800 = {
 195         .p0_mpwldectrl0 = 0x0040003C,
 196         .p0_mpwldectrl1 = 0x0032003E,
 197         .p0_mpdgctrl0   = 0x42350231,
 198         .p0_mpdgctrl1   = 0x021A0218,
 199         .p0_mprddlctl   = 0x4B4B4E49,
 200         .p0_mpwrdlctl   = 0x3F3F3035,
 201 };
 202
 203 /*
 204  * 2 Gbit DDR3 memory
 205  *   - NANYA #NT5CC128M16IP-DII
 206  *   - NANYA #NT5CB128M16FP-DII
 207  */
 208 static const struct mx6_ddr3_cfg dhcom_mem_ddr_2g = {
 209         .mem_speed      = 1600,
 210         .density        = 2,
 211         .width          = 16,
 212         .banks          = 8,
 213         .rowaddr        = 14,
 214         .coladdr        = 10,
 215         .pagesz         = 2,
 216         .trcd           = 1375,
 217         .trcmin         = 5863,
 218         .trasmin        = 3750,
 219 };
 220
 221 /*
 222  * 4 Gbit DDR3 memory
 223  *   - Intelligent Memory #IM4G16D3EABG-125I
 224  */
 225 static const struct mx6_ddr3_cfg dhcom_mem_ddr_4g = {
 226         .mem_speed      = 1600,
 227         .density        = 4,
 228         .width          = 16,
 229         .banks          = 8,
 230         .rowaddr        = 15,
 231         .coladdr        = 10,
 232         .pagesz         = 2,
 233         .trcd           = 1375,
 234         .trcmin         = 4875,
 235         .trasmin        = 3500,
 236 };
 237
 238 /* DDR3 64bit */
 239 static const struct mx6_ddr_sysinfo dhcom_ddr_64bit = {
 240         /* width of data bus:0=16,1=32,2=64 */
 241         .dsize          = 2,
 242         .cs_density     = 32,
 243         .ncs            = 1,    /* single chip select */
 244         .cs1_mirror     = 1,
 245         .rtt_wr         = 1,    /* DDR3_RTT_60_OHM, RTT_Wr = RZQ/4 */
 246         .rtt_nom        = 1,    /* DDR3_RTT_60_OHM, RTT_Nom = RZQ/4 */
 247         .walat          = 1,    /* Write additional latency */
 248         .ralat          = 5,    /* Read additional latency */
 249         .mif3_mode      = 3,    /* Command prediction working mode */
 250         .bi_on          = 1,    /* Bank interleaving enabled */
 251         .sde_to_rst     = 0x10, /* 14 cycles, 200us (JEDEC default) */
 252         .rst_to_cke     = 0x23, /* 33 cycles, 500us (JEDEC default) */
 253         .refsel         = 1,    /* Refresh cycles at 32KHz */
 254         .refr           = 3,    /* 4 refresh commands per refresh cycle */
 255 };
 256
 257 /* DDR3 32bit */
 258 static const struct mx6_ddr_sysinfo dhcom_ddr_32bit = {
 259         /* width of data bus:0=16,1=32,2=64 */
 260         .dsize          = 1,
 261         .cs_density     = 32,
 262         .ncs            = 1,    /* single chip select */
 263         .cs1_mirror     = 1,
 264         .rtt_wr         = 1,    /* DDR3_RTT_60_OHM, RTT_Wr = RZQ/4 */
 265         .rtt_nom        = 1,    /* DDR3_RTT_60_OHM, RTT_Nom = RZQ/4 */
 266         .walat          = 1,    /* Write additional latency */
 267         .ralat          = 5,    /* Read additional latency */
 268         .mif3_mode      = 3,    /* Command prediction working mode */
 269         .bi_on          = 1,    /* Bank interleaving enabled */
 270         .sde_to_rst     = 0x10, /* 14 cycles, 200us (JEDEC default) */
 271         .rst_to_cke     = 0x23, /* 33 cycles, 500us (JEDEC default) */
 272         .refsel         = 1,    /* Refresh cycles at 32KHz */
 273         .refr           = 3,    /* 4 refresh commands per refresh cycle */
 274 };
 275
 276 static void ccgr_init(void)
 277 {
 278         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 279
 280         writel(0x00C03F3F, &ccm->CCGR0);
 281         writel(0x0030FC03, &ccm->CCGR1);
 282         writel(0x0FFFC000, &ccm->CCGR2);
 283         writel(0x3FF00000, &ccm->CCGR3);
 284         writel(0x00FFF300, &ccm->CCGR4);
 285         writel(0x0F0000C3, &ccm->CCGR5);
 286         writel(0x000003FF, &ccm->CCGR6);
 287 }
 288
 289 /* Board ID */
 290 static iomux_v3_cfg_t const hwcode_pads[] = {
 291         IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19      | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 292         IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06      | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 293         IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16      | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 294 };
 295
 296 static void setup_iomux_boardid(void)
 297 {
 298         /* HW code pins: Setup alternate function and configure pads */
 299         SETUP_IOMUX_PADS(hwcode_pads);
 300 }
 301
 302 /* DDR Code */
 303 static iomux_v3_cfg_t const ddrcode_pads[] = {
 304         IOMUX_PADS(PAD_EIM_A16__GPIO2_IO22      | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 305         IOMUX_PADS(PAD_EIM_A17__GPIO2_IO21      | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 306 };
 307
 308 static void setup_iomux_ddrcode(void)
 309 {
 310         /* ddr code pins */
 311         SETUP_IOMUX_PADS(ddrcode_pads);
 312 }
 313
 314 enum dhcom_ddr3_code {
 315         DH_DDR3_SIZE_256MIB = 0x00,
 316         DH_DDR3_SIZE_512MIB = 0x01,
 317         DH_DDR3_SIZE_1GIB   = 0x02,
 318         DH_DDR3_SIZE_2GIB   = 0x03
 319 };
 320
 321 #define DDR3_CODE_BIT_0   IMX_GPIO_NR(2, 22)
 322 #define DDR3_CODE_BIT_1   IMX_GPIO_NR(2, 21)
 323
 324 enum dhcom_ddr3_code dhcom_get_ddr3_code(void)
 325 {
 326         enum dhcom_ddr3_code ddr3_code;
 327
 328         gpio_request(DDR3_CODE_BIT_0, "DDR3_CODE_BIT_0");
 329         gpio_request(DDR3_CODE_BIT_1, "DDR3_CODE_BIT_1");
 330
 331         gpio_direction_input(DDR3_CODE_BIT_0);
 332         gpio_direction_input(DDR3_CODE_BIT_1);
 333
 334         /* 256MB = 0b00; 512MB = 0b01; 1GB = 0b10; 2GB = 0b11 */
 335         ddr3_code = (!!gpio_get_value(DDR3_CODE_BIT_1) << 1)
 336              | (!!gpio_get_value(DDR3_CODE_BIT_0));
 337
 338         return ddr3_code;
 339 }
 340
 341 /* GPIO */
 342 static iomux_v3_cfg_t const gpio_pads[] = {
 343         IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02       | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 344         IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04       | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 345         IOMUX_PADS(PAD_GPIO_5__GPIO1_IO05       | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 346         IOMUX_PADS(PAD_CSI0_DAT17__GPIO6_IO03   | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 347         IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05      | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 348         IOMUX_PADS(PAD_DI0_PIN4__GPIO4_IO20     | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 349         IOMUX_PADS(PAD_EIM_D27__GPIO3_IO27      | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 350         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07     | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 351         IOMUX_PADS(PAD_KEY_COL1__GPIO4_IO08     | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 352         IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14    | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 353         IOMUX_PADS(PAD_NANDF_CS2__GPIO6_IO15    | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 354         IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09     | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 355         IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00     | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 356         IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01     | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 357         IOMUX_PADS(PAD_CSI0_VSYNC__GPIO5_IO21   | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 358         IOMUX_PADS(PAD_GPIO_18__GPIO7_IO13      | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 359         IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18      | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 360         IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16     | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 361         IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17     | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 362         IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19     | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 363         IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20      | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 364         IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18  | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 365         IOMUX_PADS(PAD_CSI0_MCLK__GPIO5_IO19    | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 366 };
 367
 368 static void setup_iomux_gpio(void)
 369 {
 370         SETUP_IOMUX_PADS(gpio_pads);
 371 }
 372
 373 /* Ethernet */
 374 static iomux_v3_cfg_t const enet_pads[] = {
 375         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 376         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC       | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 377         IOMUX_PADS(PAD_ENET_TX_EN__ENET_TX_EN   | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 378         IOMUX_PADS(PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 379         IOMUX_PADS(PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 380         IOMUX_PADS(PAD_GPIO_16__ENET_REF_CLK    | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 381         IOMUX_PADS(PAD_ENET_RX_ER__ENET_RX_ER   | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 382         IOMUX_PADS(PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 383         IOMUX_PADS(PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 384         IOMUX_PADS(PAD_ENET_CRS_DV__ENET_RX_EN  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 385         /* SMSC PHY Reset */
 386         IOMUX_PADS(PAD_EIM_WAIT__GPIO5_IO00     | MUX_PAD_CTRL(NO_PAD_CTRL)),
 387         /* ENET_VIO_GPIO */
 388         IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07       | MUX_PAD_CTRL(NO_PAD_CTRL)),
 389         /* ENET_Interrupt - (not used) */
 390         IOMUX_PADS(PAD_RGMII_RD0__GPIO6_IO25    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 391 };
 392
 393 static void setup_iomux_enet(void)
 394 {
 395         SETUP_IOMUX_PADS(enet_pads);
 396 }
 397
 398 /* SD interface */
 399 static iomux_v3_cfg_t const usdhc2_pads[] = {
 400         IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 401         IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 402         IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 403         IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 404         IOMUX_PADS(PAD_SD2_CLK__SD2_CLK         | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 405         IOMUX_PADS(PAD_SD2_CMD__SD2_CMD         | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 406         IOMUX_PADS(PAD_NANDF_CS3__GPIO6_IO16    | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
 407 };
 408
 409 /* onboard microSD */
 410 static iomux_v3_cfg_t const usdhc3_pads[] = {
 411         IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 412         IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 413         IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 414         IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 415         IOMUX_PADS(PAD_SD3_CLK__SD3_CLK         | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 416         IOMUX_PADS(PAD_SD3_CMD__SD3_CMD         | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 417         IOMUX_PADS(PAD_SD3_RST__GPIO7_IO08      | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
 418 };
 419
 420 /* eMMC */
 421 static iomux_v3_cfg_t const usdhc4_pads[] = {
 422         IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 423         IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 424         IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 425         IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 426         IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 427         IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 428         IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 429         IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 430         IOMUX_PADS(PAD_SD4_CLK__SD4_CLK         | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 431         IOMUX_PADS(PAD_SD4_CMD__SD4_CMD         | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 432 };
 433
 434 /* SD */
 435 static void setup_iomux_sd(void)
 436 {
 437         SETUP_IOMUX_PADS(usdhc2_pads);
 438         SETUP_IOMUX_PADS(usdhc3_pads);
 439         SETUP_IOMUX_PADS(usdhc4_pads);
 440 }
 441
 442 /* SPI */
 443 static iomux_v3_cfg_t const ecspi1_pads[] = {
 444         /* SS0 - SS of boot flash */
 445         IOMUX_PADS(PAD_EIM_EB2__GPIO2_IO30      |
 446                 MUX_PAD_CTRL(SPI_PAD_CTRL | PAD_CTL_PUS_100K_UP)),
 447         /* SS2 - SS of DHCOM SPI1 */
 448         IOMUX_PADS(PAD_KEY_ROW2__GPIO4_IO11     |
 449                 MUX_PAD_CTRL(SPI_PAD_CTRL | PAD_CTL_PUS_100K_UP)),
 450
 451         IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO     | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 452         IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI     | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 453         IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK     | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 454 };
 455
 456 static void setup_iomux_spi(void)
 457 {
 458         SETUP_IOMUX_PADS(ecspi1_pads);
 459 }
 460
 461 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 462 {
 463         if (bus == 0 && cs == 0)
 464                 return IMX_GPIO_NR(2, 30);
 465         else
 466                 return -1;
 467 }
 468
 469 /* UART */
 470 static iomux_v3_cfg_t const uart1_pads[] = {
 471         IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA  | MUX_PAD_CTRL(UART_PAD_CTRL)),
 472         IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA  | MUX_PAD_CTRL(UART_PAD_CTRL)),
 473 };
 474
 475 static void setup_iomux_uart(void)
 476 {
 477         SETUP_IOMUX_PADS(uart1_pads);
 478 }
 479
 480 #ifdef CONFIG_FSL_USDHC
 481 struct fsl_esdhc_cfg usdhc_cfg[1] = {
 482         {USDHC4_BASE_ADDR},
 483 };
 484
 485 int board_mmc_get_env_dev(int devno)
 486 {
 487         return devno - 1;
 488 }
 489
 490 int board_mmc_getcd(struct mmc *mmc)
 491 {
 492         return 1; /* eMMC/uSDHC4 is always present */
 493 }
 494
 495 int board_mmc_init(bd_t *bis)
 496 {
 497         SETUP_IOMUX_PADS(usdhc4_pads);
 498         usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
 499         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 500         usdhc_cfg[0].max_bus_width = 8;
 501
 502         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 503 }
 504 #endif
 505
 506 /* USB */
 507 static iomux_v3_cfg_t const usb_pads[] = {
 508         IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID       | MUX_PAD_CTRL(NO_PAD_CTRL)),
 509         IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31      | MUX_PAD_CTRL(NO_PAD_CTRL)),
 510 };
 511
 512 static void setup_iomux_usb(void)
 513 {
 514         SETUP_IOMUX_PADS(usb_pads);
 515 }
 516
 517 /* Perform DDR DRAM calibration */
 518 static int spl_dram_perform_cal(struct mx6_ddr_sysinfo const *sysinfo)
 519 {
 520         int ret = 0;
 521
 522 #ifdef CONFIG_MX6_DDRCAL
 523         udelay(100);
 524         ret = mmdc_do_write_level_calibration(sysinfo);
 525         if (ret) {
 526                 printf("DDR3: Write level calibration error [%d]\n", ret);
 527                 return ret;
 528         }
 529
 530         ret = mmdc_do_dqs_calibration(sysinfo);
 531         if (ret) {
 532                 printf("DDR3: DQS calibration error [%d]\n", ret);
 533                 return ret;
 534         }
 535 #endif /* CONFIG_MX6_DDRCAL */
 536
 537         return ret;
 538 }
 539
 540
 541 /* DRAM */
 542 static void dhcom_spl_dram_init(void)
 543 {
 544         enum dhcom_ddr3_code ddr3_code = dhcom_get_ddr3_code();
 545
 546         if (is_mx6dq()) {
 547                 mx6dq_dram_iocfg(64, &dhcom6dq_ddr_ioregs,
 548                                         &dhcom6dq_grp_ioregs);
 549                 switch (ddr3_code) {
 550                 default:
 551                         printf("imx6qd: unsupported ddr3 code %d\n", ddr3_code);
 552                         printf("        choosing 1024 MB\n");
 553                         /* fall through */
 554                 case DH_DDR3_SIZE_1GIB:
 555                         mx6_dram_cfg(&dhcom_ddr_64bit,
 556                                      &dhcom_mmdc_calib_4x2g_1066,
 557                                      &dhcom_mem_ddr_2g);
 558                         break;
 559                 case DH_DDR3_SIZE_2GIB:
 560                         mx6_dram_cfg(&dhcom_ddr_64bit,
 561                                      &dhcom_mmdc_calib_4x4g_1066,
 562                                      &dhcom_mem_ddr_4g);
 563                         break;
 564                 }
 565
 566                 /* Perform DDR DRAM calibration */
 567                 spl_dram_perform_cal(&dhcom_ddr_64bit);
 568
 569         } else if (is_cpu_type(MXC_CPU_MX6DL)) {
 570                 mx6sdl_dram_iocfg(64, &dhcom6sdl_ddr_ioregs,
 571                                           &dhcom6sdl_grp_ioregs);
 572                 switch (ddr3_code) {
 573                 default:
 574                         printf("imx6dl: unsupported ddr3 code %d\n", ddr3_code);
 575                         printf("        choosing 1024 MB\n");
 576                         /* fall through */
 577                 case DH_DDR3_SIZE_1GIB:
 578                         mx6_dram_cfg(&dhcom_ddr_64bit,
 579                                      &dhcom_mmdc_calib_4x2g_800,
 580                                      &dhcom_mem_ddr_2g);
 581                         break;
 582                 }
 583
 584                 /* Perform DDR DRAM calibration */
 585                 spl_dram_perform_cal(&dhcom_ddr_64bit);
 586
 587         } else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
 588                 mx6sdl_dram_iocfg(32, &dhcom6sdl_ddr_ioregs,
 589                                           &dhcom6sdl_grp_ioregs);
 590                 switch (ddr3_code) {
 591                 default:
 592                         printf("imx6s: unsupported ddr3 code %d\n", ddr3_code);
 593                         printf("       choosing 512 MB\n");
 594                         /* fall through */
 595                 case DH_DDR3_SIZE_512MIB:
 596                         mx6_dram_cfg(&dhcom_ddr_32bit,
 597                                      &dhcom_mmdc_calib_2x2g_800,
 598                                      &dhcom_mem_ddr_2g);
 599                         break;
 600                 case DH_DDR3_SIZE_1GIB:
 601                         mx6_dram_cfg(&dhcom_ddr_32bit,
 602                                      &dhcom_mmdc_calib_2x4g_800,
 603                                      &dhcom_mem_ddr_4g);
 604                         break;
 605                 }
 606
 607                 /* Perform DDR DRAM calibration */
 608                 spl_dram_perform_cal(&dhcom_ddr_32bit);
 609         }
 610 }
 611
 612 void board_init_f(ulong dummy)
 613 {
 614         /* setup AIPS and disable watchdog */
 615         arch_cpu_init();
 616
 617         ccgr_init();
 618         gpr_init();
 619
 620         /* setup GP timer */
 621         timer_init();
 622
 623         setup_iomux_boardid();
 624         setup_iomux_ddrcode();
 625         setup_iomux_gpio();
 626         setup_iomux_enet();
 627         setup_iomux_sd();
 628         setup_iomux_spi();
 629         setup_iomux_uart();
 630         setup_iomux_usb();
 631
 632         /* UART clocks enabled and gd valid - init serial console */
 633         preloader_console_init();
 634
 635         /* DDR3 initialization */
 636         dhcom_spl_dram_init();
 637
 638         /* Clear the BSS. */
 639         memset(__bss_start, 0, __bss_end - __bss_start);
 640
 641         /* load/boot image from boot device */
 642         board_init_r(NULL, 0);
 643 }