drivers/mtd/nand/raw/tegra_nand.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (c) 2011 The Chromium OS Authors.
   4  * (C) Copyright 2011 NVIDIA Corporation <www.nvidia.com>
   5  * (C) Copyright 2006 Detlev Zundel, [email protected]
   6  * (C) Copyright 2006 DENX Software Engineering
   7  */
   8
   9 #include <common.h>
  10 #include <log.h>
  11 #include <asm/io.h>
  12 #include <memalign.h>
  13 #include <nand.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/arch/funcmux.h>
  16 #include <asm/arch-tegra/clk_rst.h>
  17 #include <dm/device_compat.h>
  18 #include <linux/bug.h>
  19 #include <linux/delay.h>
  20 #include <linux/errno.h>
  21 #include <asm/gpio.h>
  22 #include <fdtdec.h>
  23 #include <bouncebuf.h>
  24 #include <dm.h>
  25 #include "tegra_nand.h"
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 #define NAND_CMD_TIMEOUT_MS             10
  30
  31 #define SKIPPED_SPARE_BYTES             4
  32
  33 /* ECC bytes to be generated for tag data */
  34 #define TAG_ECC_BYTES                   4
  35
  36 static const struct udevice_id tegra_nand_dt_ids[] = {
  37         {
  38                 .compatible = "nvidia,tegra20-nand",
  39         },
  40         { /* sentinel */ }
  41 };
  42
  43 /* 64 byte oob block info for large page (== 2KB) device
  44  *
  45  * OOB flash layout for Tegra with Reed-Solomon 4 symbol correct ECC:
  46  *      Skipped bytes(4)
  47  *      Main area Ecc(36)
  48  *      Tag data(20)
  49  *      Tag data Ecc(4)
  50  *
  51  * Yaffs2 will use 16 tag bytes.
  52  */
  53 static struct nand_ecclayout eccoob = {
  54         .eccbytes = 36,
  55         .eccpos = {
  56                 4,  5,  6,  7,  8,  9,  10, 11, 12,
  57                 13, 14, 15, 16, 17, 18, 19, 20, 21,
  58                 22, 23, 24, 25, 26, 27, 28, 29, 30,
  59                 31, 32, 33, 34, 35, 36, 37, 38, 39,
  60         },
  61         .oobavail = 20,
  62         .oobfree = {
  63                         {
  64                         .offset = 40,
  65                         .length = 20,
  66                         },
  67         }
  68 };
  69
  70 enum {
  71         ECC_OK,
  72         ECC_TAG_ERROR = 1 << 0,
  73         ECC_DATA_ERROR = 1 << 1
  74 };
  75
  76 /* Timing parameters */
  77 enum {
  78         FDT_NAND_MAX_TRP_TREA,
  79         FDT_NAND_TWB,
  80         FDT_NAND_MAX_TCR_TAR_TRR,
  81         FDT_NAND_TWHR,
  82         FDT_NAND_MAX_TCS_TCH_TALS_TALH,
  83         FDT_NAND_TWH,
  84         FDT_NAND_TWP,
  85         FDT_NAND_TRH,
  86         FDT_NAND_TADL,
  87
  88         FDT_NAND_TIMING_COUNT
  89 };
  90
  91 /* Information about an attached NAND chip */
  92 struct fdt_nand {
  93         struct nand_ctlr *reg;
  94         int enabled;            /* 1 to enable, 0 to disable */
  95         struct gpio_desc wp_gpio;       /* write-protect GPIO */
  96         s32 width;              /* bit width, normally 8 */
  97         u32 timing[FDT_NAND_TIMING_COUNT];
  98 };
  99
 100 struct nand_drv {
 101         struct nand_ctlr *reg;
 102         struct fdt_nand config;
 103 };
 104
 105 struct tegra_nand_info {
 106         struct udevice *dev;
 107         struct nand_drv nand_ctrl;
 108         struct nand_chip nand_chip;
 109 };
 110
 111 /**
 112  * Wait for command completion
 113  *
 114  * @param reg   nand_ctlr structure
 115  * @return
 116  *      1 - Command completed
 117  *      0 - Timeout
 118  */
 119 static int nand_waitfor_cmd_completion(struct nand_ctlr *reg)
 120 {
 121         u32 reg_val;
 122         int running;
 123         int i;
 124
 125         for (i = 0; i < NAND_CMD_TIMEOUT_MS * 1000; i++) {
 126                 if ((readl(&reg->command) & CMD_GO) ||
 127                                 !(readl(&reg->status) & STATUS_RBSY0) ||
 128                                 !(readl(&reg->isr) & ISR_IS_CMD_DONE)) {
 129                         udelay(1);
 130                         continue;
 131                 }
 132                 reg_val = readl(&reg->dma_mst_ctrl);
 133                 /*
 134                  * If DMA_MST_CTRL_EN_A_ENABLE or DMA_MST_CTRL_EN_B_ENABLE
 135                  * is set, that means DMA engine is running.
 136                  *
 137                  * Then we have to wait until DMA_MST_CTRL_IS_DMA_DONE
 138                  * is cleared, indicating DMA transfer completion.
 139                  */
 140                 running = reg_val & (DMA_MST_CTRL_EN_A_ENABLE |
 141                                 DMA_MST_CTRL_EN_B_ENABLE);
 142                 if (!running || (reg_val & DMA_MST_CTRL_IS_DMA_DONE))
 143                         return 1;
 144                 udelay(1);
 145         }
 146         return 0;
 147 }
 148
 149 /**
 150  * Read one byte from the chip
 151  *
 152  * @param mtd   MTD device structure
 153  * @return      data byte
 154  *
 155  * Read function for 8bit bus-width
 156  */
 157 static uint8_t read_byte(struct mtd_info *mtd)
 158 {
 159         struct nand_chip *chip = mtd_to_nand(mtd);
 160         struct nand_drv *info;
 161
 162         info = (struct nand_drv *)nand_get_controller_data(chip);
 163
 164         writel(CMD_GO | CMD_PIO | CMD_RX | CMD_CE0 | CMD_A_VALID,
 165                &info->reg->command);
 166         if (!nand_waitfor_cmd_completion(info->reg))
 167                 printf("Command timeout\n");
 168
 169         return (uint8_t)readl(&info->reg->resp);
 170 }
 171
 172 /**
 173  * Read len bytes from the chip into a buffer
 174  *
 175  * @param mtd   MTD device structure
 176  * @param buf   buffer to store data to
 177  * @param len   number of bytes to read
 178  *
 179  * Read function for 8bit bus-width
 180  */
 181 static void read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 182 {
 183         int i, s;
 184         unsigned int reg;
 185         struct nand_chip *chip = mtd_to_nand(mtd);
 186         struct nand_drv *info = (struct nand_drv *)nand_get_controller_data(chip);
 187
 188         for (i = 0; i < len; i += 4) {
 189                 s = (len - i) > 4 ? 4 : len - i;
 190                 writel(CMD_PIO | CMD_RX | CMD_A_VALID | CMD_CE0 |
 191                         ((s - 1) << CMD_TRANS_SIZE_SHIFT) | CMD_GO,
 192                         &info->reg->command);
 193                 if (!nand_waitfor_cmd_completion(info->reg))
 194                         puts("Command timeout during read_buf\n");
 195                 reg = readl(&info->reg->resp);
 196                 memcpy(buf + i, &reg, s);
 197         }
 198 }
 199
 200 /**
 201  * Check NAND status to see if it is ready or not
 202  *
 203  * @param mtd   MTD device structure
 204  * @return
 205  *      1 - ready
 206  *      0 - not ready
 207  */
 208 static int nand_dev_ready(struct mtd_info *mtd)
 209 {
 210         struct nand_chip *chip = mtd_to_nand(mtd);
 211         int reg_val;
 212         struct nand_drv *info;
 213
 214         info = (struct nand_drv *)nand_get_controller_data(chip);
 215
 216         reg_val = readl(&info->reg->status);
 217         if (reg_val & STATUS_RBSY0)
 218                 return 1;
 219         else
 220                 return 0;
 221 }
 222
 223 /* Dummy implementation: we don't support multiple chips */
 224 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
 225 {
 226         switch (chipnr) {
 227         case -1:
 228         case 0:
 229                 break;
 230
 231         default:
 232                 BUG();
 233         }
 234 }
 235
 236 /**
 237  * Clear all interrupt status bits
 238  *
 239  * @param reg   nand_ctlr structure
 240  */
 241 static void nand_clear_interrupt_status(struct nand_ctlr *reg)
 242 {
 243         u32 reg_val;
 244
 245         /* Clear interrupt status */
 246         reg_val = readl(&reg->isr);
 247         writel(reg_val, &reg->isr);
 248 }
 249
 250 /**
 251  * Send command to NAND device
 252  *
 253  * @param mtd           MTD device structure
 254  * @param command       the command to be sent
 255  * @param column        the column address for this command, -1 if none
 256  * @param page_addr     the page address for this command, -1 if none
 257  */
 258 static void nand_command(struct mtd_info *mtd, unsigned int command,
 259         int column, int page_addr)
 260 {
 261         struct nand_chip *chip = mtd_to_nand(mtd);
 262         struct nand_drv *info;
 263
 264         info = (struct nand_drv *)nand_get_controller_data(chip);
 265
 266         /*
 267          * Write out the command to the device.
 268          *
 269          * Only command NAND_CMD_RESET or NAND_CMD_READID will come
 270          * here before mtd->writesize is initialized.
 271          */
 272
 273         /* Emulate NAND_CMD_READOOB */
 274         if (command == NAND_CMD_READOOB) {
 275                 assert(mtd->writesize != 0);
 276                 column += mtd->writesize;
 277                 command = NAND_CMD_READ0;
 278         }
 279
 280         /* Adjust columns for 16 bit bus-width */
 281         if (column != -1 && (chip->options & NAND_BUSWIDTH_16))
 282                 column >>= 1;
 283
 284         nand_clear_interrupt_status(info->reg);
 285
 286         /* Stop DMA engine, clear DMA completion status */
 287         writel(DMA_MST_CTRL_EN_A_DISABLE
 288                 | DMA_MST_CTRL_EN_B_DISABLE
 289                 | DMA_MST_CTRL_IS_DMA_DONE,
 290                 &info->reg->dma_mst_ctrl);
 291
 292         /*
 293          * Program and erase have their own busy handlers
 294          * status and sequential in needs no delay
 295          */
 296         switch (command) {
 297         case NAND_CMD_READID:
 298                 writel(NAND_CMD_READID, &info->reg->cmd_reg1);
 299                 writel(column & 0xFF, &info->reg->addr_reg1);
 300                 writel(CMD_GO | CMD_CLE | CMD_ALE | CMD_CE0,
 301                        &info->reg->command);
 302                 break;
 303         case NAND_CMD_PARAM:
 304                 writel(NAND_CMD_PARAM, &info->reg->cmd_reg1);
 305                 writel(column & 0xFF, &info->reg->addr_reg1);
 306                 writel(CMD_GO | CMD_CLE | CMD_ALE | CMD_CE0,
 307                         &info->reg->command);
 308                 break;
 309         case NAND_CMD_READ0:
 310                 writel(NAND_CMD_READ0, &info->reg->cmd_reg1);
 311                 writel(NAND_CMD_READSTART, &info->reg->cmd_reg2);
 312                 writel((page_addr << 16) | (column & 0xFFFF),
 313                         &info->reg->addr_reg1);
 314                 writel(page_addr >> 16, &info->reg->addr_reg2);
 315                 return;
 316         case NAND_CMD_SEQIN:
 317                 writel(NAND_CMD_SEQIN, &info->reg->cmd_reg1);
 318                 writel(NAND_CMD_PAGEPROG, &info->reg->cmd_reg2);
 319                 writel((page_addr << 16) | (column & 0xFFFF),
 320                         &info->reg->addr_reg1);
 321                 writel(page_addr >> 16,
 322                         &info->reg->addr_reg2);
 323                 return;
 324         case NAND_CMD_PAGEPROG:
 325                 return;
 326         case NAND_CMD_ERASE1:
 327                 writel(NAND_CMD_ERASE1, &info->reg->cmd_reg1);
 328                 writel(NAND_CMD_ERASE2, &info->reg->cmd_reg2);
 329                 writel(page_addr, &info->reg->addr_reg1);
 330                 writel(CMD_GO | CMD_CLE | CMD_ALE |
 331                         CMD_SEC_CMD | CMD_CE0 | CMD_ALE_BYTES3,
 332                         &info->reg->command);
 333                 break;
 334         case NAND_CMD_ERASE2:
 335                 return;
 336         case NAND_CMD_STATUS:
 337                 writel(NAND_CMD_STATUS, &info->reg->cmd_reg1);
 338                 writel(CMD_GO | CMD_CLE | CMD_PIO | CMD_RX
 339                         | ((1 - 0) << CMD_TRANS_SIZE_SHIFT)
 340                         | CMD_CE0,
 341                         &info->reg->command);
 342                 break;
 343         case NAND_CMD_RESET:
 344                 writel(NAND_CMD_RESET, &info->reg->cmd_reg1);
 345                 writel(CMD_GO | CMD_CLE | CMD_CE0,
 346                         &info->reg->command);
 347                 break;
 348         case NAND_CMD_RNDOUT:
 349         default:
 350                 printf("%s: Unsupported command %d\n", __func__, command);
 351                 return;
 352         }
 353         if (!nand_waitfor_cmd_completion(info->reg))
 354                 printf("Command 0x%02X timeout\n", command);
 355 }
 356
 357 /**
 358  * Check whether the pointed buffer are all 0xff (blank).
 359  *
 360  * @param buf   data buffer for blank check
 361  * @param len   length of the buffer in byte
 362  * @return
 363  *      1 - blank
 364  *      0 - non-blank
 365  */
 366 static int blank_check(u8 *buf, int len)
 367 {
 368         int i;
 369
 370         for (i = 0; i < len; i++)
 371                 if (buf[i] != 0xFF)
 372                         return 0;
 373         return 1;
 374 }
 375
 376 /**
 377  * After a DMA transfer for read, we call this function to see whether there
 378  * is any uncorrectable error on the pointed data buffer or oob buffer.
 379  *
 380  * @param reg           nand_ctlr structure
 381  * @param databuf       data buffer
 382  * @param a_len         data buffer length
 383  * @param oobbuf        oob buffer
 384  * @param b_len         oob buffer length
 385  * @return
 386  *      ECC_OK - no ECC error or correctable ECC error
 387  *      ECC_TAG_ERROR - uncorrectable tag ECC error
 388  *      ECC_DATA_ERROR - uncorrectable data ECC error
 389  *      ECC_DATA_ERROR + ECC_TAG_ERROR - uncorrectable data+tag ECC error
 390  */
 391 static int check_ecc_error(struct nand_ctlr *reg, u8 *databuf,
 392         int a_len, u8 *oobbuf, int b_len)
 393 {
 394         int return_val = ECC_OK;
 395         u32 reg_val;
 396
 397         if (!(readl(&reg->isr) & ISR_IS_ECC_ERR))
 398                 return ECC_OK;
 399
 400         /*
 401          * Area A is used for the data block (databuf). Area B is used for
 402          * the spare block (oobbuf)
 403          */
 404         reg_val = readl(&reg->dec_status);
 405         if ((reg_val & DEC_STATUS_A_ECC_FAIL) && databuf) {
 406                 reg_val = readl(&reg->bch_dec_status_buf);
 407                 /*
 408                  * If uncorrectable error occurs on data area, then see whether
 409                  * they are all FF. If all are FF, it's a blank page.
 410                  * Not error.
 411                  */
 412                 if ((reg_val & BCH_DEC_STATUS_FAIL_SEC_FLAG_MASK) &&
 413                                 !blank_check(databuf, a_len))
 414                         return_val |= ECC_DATA_ERROR;
 415         }
 416
 417         if ((reg_val & DEC_STATUS_B_ECC_FAIL) && oobbuf) {
 418                 reg_val = readl(&reg->bch_dec_status_buf);
 419                 /*
 420                  * If uncorrectable error occurs on tag area, then see whether
 421                  * they are all FF. If all are FF, it's a blank page.
 422                  * Not error.
 423                  */
 424                 if ((reg_val & BCH_DEC_STATUS_FAIL_TAG_MASK) &&
 425                                 !blank_check(oobbuf, b_len))
 426                         return_val |= ECC_TAG_ERROR;
 427         }
 428
 429         return return_val;
 430 }
 431
 432 /**
 433  * Set GO bit to send command to device
 434  *
 435  * @param reg   nand_ctlr structure
 436  */
 437 static void start_command(struct nand_ctlr *reg)
 438 {
 439         u32 reg_val;
 440
 441         reg_val = readl(&reg->command);
 442         reg_val |= CMD_GO;
 443         writel(reg_val, &reg->command);
 444 }
 445
 446 /**
 447  * Clear command GO bit, DMA GO bit, and DMA completion status
 448  *
 449  * @param reg   nand_ctlr structure
 450  */
 451 static void stop_command(struct nand_ctlr *reg)
 452 {
 453         /* Stop command */
 454         writel(0, &reg->command);
 455
 456         /* Stop DMA engine and clear DMA completion status */
 457         writel(DMA_MST_CTRL_GO_DISABLE
 458                 | DMA_MST_CTRL_IS_DMA_DONE,
 459                 &reg->dma_mst_ctrl);
 460 }
 461
 462 /**
 463  * Set up NAND bus width and page size
 464  *
 465  * @param info          nand_info structure
 466  * @param *reg_val      address of reg_val
 467  * @return 0 if ok, -1 on error
 468  */
 469 static int set_bus_width_page_size(struct mtd_info *our_mtd,
 470                                    struct fdt_nand *config, u32 *reg_val)
 471 {
 472         if (config->width == 8)
 473                 *reg_val = CFG_BUS_WIDTH_8BIT;
 474         else if (config->width == 16)
 475                 *reg_val = CFG_BUS_WIDTH_16BIT;
 476         else {
 477                 debug("%s: Unsupported bus width %d\n", __func__,
 478                       config->width);
 479                 return -1;
 480         }
 481
 482         if (our_mtd->writesize == 512)
 483                 *reg_val |= CFG_PAGE_SIZE_512;
 484         else if (our_mtd->writesize == 2048)
 485                 *reg_val |= CFG_PAGE_SIZE_2048;
 486         else if (our_mtd->writesize == 4096)
 487                 *reg_val |= CFG_PAGE_SIZE_4096;
 488         else {
 489                 debug("%s: Unsupported page size %d\n", __func__,
 490                       our_mtd->writesize);
 491                 return -1;
 492         }
 493
 494         return 0;
 495 }
 496
 497 /**
 498  * Page read/write function
 499  *
 500  * @param mtd           mtd info structure
 501  * @param chip          nand chip info structure
 502  * @param buf           data buffer
 503  * @param page          page number
 504  * @param with_ecc      1 to enable ECC, 0 to disable ECC
 505  * @param is_writing    0 for read, 1 for write
 506  * @return      0 when successfully completed
 507  *              -EIO when command timeout
 508  */
 509 static int nand_rw_page(struct mtd_info *mtd, struct nand_chip *chip,
 510         uint8_t *buf, int page, int with_ecc, int is_writing)
 511 {
 512         u32 reg_val;
 513         int tag_size;
 514         struct nand_oobfree *free = chip->ecc.layout->oobfree;
 515         /* 4*128=512 (byte) is the value that our HW can support. */
 516         ALLOC_CACHE_ALIGN_BUFFER(u32, tag_buf, 128);
 517         char *tag_ptr;
 518         struct nand_drv *info;
 519         struct fdt_nand *config;
 520         unsigned int bbflags;
 521         struct bounce_buffer bbstate, bbstate_oob;
 522
 523         if ((uintptr_t)buf & 0x03) {
 524                 printf("buf %p has to be 4-byte aligned\n", buf);
 525                 return -EINVAL;
 526         }
 527
 528         info = (struct nand_drv *)nand_get_controller_data(chip);
 529         config = &info->config;
 530         if (set_bus_width_page_size(mtd, config, &reg_val))
 531                 return -EINVAL;
 532
 533         /* Need to be 4-byte aligned */
 534         tag_ptr = (char *)tag_buf;
 535
 536         stop_command(info->reg);
 537
 538         if (is_writing)
 539                 bbflags = GEN_BB_READ;
 540         else
 541                 bbflags = GEN_BB_WRITE;
 542
 543         bounce_buffer_start(&bbstate, (void *)buf, 1 << chip->page_shift,
 544                             bbflags);
 545         writel((1 << chip->page_shift) - 1, &info->reg->dma_cfg_a);
 546         writel(virt_to_phys(bbstate.bounce_buffer), &info->reg->data_block_ptr);
 547
 548         /* Set ECC selection, configure ECC settings */
 549         if (with_ecc) {
 550                 if (is_writing)
 551                         memcpy(tag_ptr, chip->oob_poi + free->offset,
 552                                chip->ecc.layout->oobavail + TAG_ECC_BYTES);
 553                 tag_size = chip->ecc.layout->oobavail + TAG_ECC_BYTES;
 554                 reg_val |= (CFG_SKIP_SPARE_SEL_4
 555                         | CFG_SKIP_SPARE_ENABLE
 556                         | CFG_HW_ECC_CORRECTION_ENABLE
 557                         | CFG_ECC_EN_TAG_DISABLE
 558                         | CFG_HW_ECC_SEL_RS
 559                         | CFG_HW_ECC_ENABLE
 560                         | CFG_TVAL4
 561                         | (tag_size - 1));
 562
 563                 if (!is_writing)
 564                         tag_size += SKIPPED_SPARE_BYTES;
 565                 bounce_buffer_start(&bbstate_oob, (void *)tag_ptr, tag_size,
 566                                     bbflags);
 567         } else {
 568                 tag_size = mtd->oobsize;
 569                 reg_val |= (CFG_SKIP_SPARE_DISABLE
 570                         | CFG_HW_ECC_CORRECTION_DISABLE
 571                         | CFG_ECC_EN_TAG_DISABLE
 572                         | CFG_HW_ECC_DISABLE
 573                         | (tag_size - 1));
 574                 bounce_buffer_start(&bbstate_oob, (void *)chip->oob_poi,
 575                                     tag_size, bbflags);
 576         }
 577         writel(reg_val, &info->reg->config);
 578         writel(virt_to_phys(bbstate_oob.bounce_buffer), &info->reg->tag_ptr);
 579         writel(BCH_CONFIG_BCH_ECC_DISABLE, &info->reg->bch_config);
 580         writel(tag_size - 1, &info->reg->dma_cfg_b);
 581
 582         nand_clear_interrupt_status(info->reg);
 583
 584         reg_val = CMD_CLE | CMD_ALE
 585                 | CMD_SEC_CMD
 586                 | (CMD_ALE_BYTES5 << CMD_ALE_BYTE_SIZE_SHIFT)
 587                 | CMD_A_VALID
 588                 | CMD_B_VALID
 589                 | (CMD_TRANS_SIZE_PAGE << CMD_TRANS_SIZE_SHIFT)
 590                 | CMD_CE0;
 591         if (!is_writing)
 592                 reg_val |= (CMD_AFT_DAT_DISABLE | CMD_RX);
 593         else
 594                 reg_val |= (CMD_AFT_DAT_ENABLE | CMD_TX);
 595         writel(reg_val, &info->reg->command);
 596
 597         /* Setup DMA engine */
 598         reg_val = DMA_MST_CTRL_GO_ENABLE
 599                 | DMA_MST_CTRL_BURST_8WORDS
 600                 | DMA_MST_CTRL_EN_A_ENABLE
 601                 | DMA_MST_CTRL_EN_B_ENABLE;
 602
 603         if (!is_writing)
 604                 reg_val |= DMA_MST_CTRL_DIR_READ;
 605         else
 606                 reg_val |= DMA_MST_CTRL_DIR_WRITE;
 607
 608         writel(reg_val, &info->reg->dma_mst_ctrl);
 609
 610         start_command(info->reg);
 611
 612         if (!nand_waitfor_cmd_completion(info->reg)) {
 613                 if (!is_writing)
 614                         printf("Read Page 0x%X timeout ", page);
 615                 else
 616                         printf("Write Page 0x%X timeout ", page);
 617                 if (with_ecc)
 618                         printf("with ECC");
 619                 else
 620                         printf("without ECC");
 621                 printf("\n");
 622                 return -EIO;
 623         }
 624
 625         bounce_buffer_stop(&bbstate_oob);
 626         bounce_buffer_stop(&bbstate);
 627
 628         if (with_ecc && !is_writing) {
 629                 memcpy(chip->oob_poi, tag_ptr,
 630                         SKIPPED_SPARE_BYTES);
 631                 memcpy(chip->oob_poi + free->offset,
 632                         tag_ptr + SKIPPED_SPARE_BYTES,
 633                         chip->ecc.layout->oobavail);
 634                 reg_val = (u32)check_ecc_error(info->reg, (u8 *)buf,
 635                         1 << chip->page_shift,
 636                         (u8 *)(tag_ptr + SKIPPED_SPARE_BYTES),
 637                         chip->ecc.layout->oobavail);
 638                 if (reg_val & ECC_TAG_ERROR)
 639                         printf("Read Page 0x%X tag ECC error\n", page);
 640                 if (reg_val & ECC_DATA_ERROR)
 641                         printf("Read Page 0x%X data ECC error\n",
 642                                 page);
 643                 if (reg_val & (ECC_DATA_ERROR | ECC_TAG_ERROR))
 644                         return -EIO;
 645         }
 646         return 0;
 647 }
 648
 649 /**
 650  * Hardware ecc based page read function
 651  *
 652  * @param mtd   mtd info structure
 653  * @param chip  nand chip info structure
 654  * @param buf   buffer to store read data
 655  * @param page  page number to read
 656  * @return      0 when successfully completed
 657  *              -EIO when command timeout
 658  */
 659 static int nand_read_page_hwecc(struct mtd_info *mtd,
 660         struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
 661 {
 662         return nand_rw_page(mtd, chip, buf, page, 1, 0);
 663 }
 664
 665 /**
 666  * Hardware ecc based page write function
 667  *
 668  * @param mtd   mtd info structure
 669  * @param chip  nand chip info structure
 670  * @param buf   data buffer
 671  */
 672 static int nand_write_page_hwecc(struct mtd_info *mtd,
 673         struct nand_chip *chip, const uint8_t *buf, int oob_required,
 674         int page)
 675 {
 676         nand_rw_page(mtd, chip, (uint8_t *)buf, page, 1, 1);
 677         return 0;
 678 }
 679
 680
 681 /**
 682  * Read raw page data without ecc
 683  *
 684  * @param mtd   mtd info structure
 685  * @param chip  nand chip info structure
 686  * @param buf   buffer to store read data
 687  * @param page  page number to read
 688  * @return      0 when successfully completed
 689  *              -EINVAL when chip->oob_poi is not double-word aligned
 690  *              -EIO when command timeout
 691  */
 692 static int nand_read_page_raw(struct mtd_info *mtd,
 693         struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
 694 {
 695         return nand_rw_page(mtd, chip, buf, page, 0, 0);
 696 }
 697
 698 /**
 699  * Raw page write function
 700  *
 701  * @param mtd   mtd info structure
 702  * @param chip  nand chip info structure
 703  * @param buf   data buffer
 704  */
 705 static int nand_write_page_raw(struct mtd_info *mtd,
 706                 struct nand_chip *chip, const uint8_t *buf,
 707                 int oob_required, int page)
 708 {
 709         nand_rw_page(mtd, chip, (uint8_t *)buf, page, 0, 1);
 710         return 0;
 711 }
 712
 713 /**
 714  * OOB data read/write function
 715  *
 716  * @param mtd           mtd info structure
 717  * @param chip          nand chip info structure
 718  * @param page          page number to read
 719  * @param with_ecc      1 to enable ECC, 0 to disable ECC
 720  * @param is_writing    0 for read, 1 for write
 721  * @return      0 when successfully completed
 722  *              -EINVAL when chip->oob_poi is not double-word aligned
 723  *              -EIO when command timeout
 724  */
 725 static int nand_rw_oob(struct mtd_info *mtd, struct nand_chip *chip,
 726         int page, int with_ecc, int is_writing)
 727 {
 728         u32 reg_val;
 729         int tag_size;
 730         struct nand_oobfree *free = chip->ecc.layout->oobfree;
 731         struct nand_drv *info;
 732         unsigned int bbflags;
 733         struct bounce_buffer bbstate_oob;
 734
 735         if (((int)chip->oob_poi) & 0x03)
 736                 return -EINVAL;
 737         info = (struct nand_drv *)nand_get_controller_data(chip);
 738         if (set_bus_width_page_size(mtd, &info->config, &reg_val))
 739                 return -EINVAL;
 740
 741         stop_command(info->reg);
 742
 743         /* Set ECC selection */
 744         tag_size = mtd->oobsize;
 745         if (with_ecc)
 746                 reg_val |= CFG_ECC_EN_TAG_ENABLE;
 747         else
 748                 reg_val |= (CFG_ECC_EN_TAG_DISABLE);
 749
 750         reg_val |= ((tag_size - 1) |
 751                 CFG_SKIP_SPARE_DISABLE |
 752                 CFG_HW_ECC_CORRECTION_DISABLE |
 753                 CFG_HW_ECC_DISABLE);
 754         writel(reg_val, &info->reg->config);
 755
 756         if (is_writing && with_ecc)
 757                 tag_size -= TAG_ECC_BYTES;
 758
 759         if (is_writing)
 760                 bbflags = GEN_BB_READ;
 761         else
 762                 bbflags = GEN_BB_WRITE;
 763
 764         bounce_buffer_start(&bbstate_oob, (void *)chip->oob_poi, tag_size,
 765                             bbflags);
 766         writel(virt_to_phys(bbstate_oob.bounce_buffer), &info->reg->tag_ptr);
 767
 768         writel(BCH_CONFIG_BCH_ECC_DISABLE, &info->reg->bch_config);
 769
 770         writel(tag_size - 1, &info->reg->dma_cfg_b);
 771
 772         nand_clear_interrupt_status(info->reg);
 773
 774         reg_val = CMD_CLE | CMD_ALE
 775                 | CMD_SEC_CMD
 776                 | (CMD_ALE_BYTES5 << CMD_ALE_BYTE_SIZE_SHIFT)
 777                 | CMD_B_VALID
 778                 | CMD_CE0;
 779         if (!is_writing)
 780                 reg_val |= (CMD_AFT_DAT_DISABLE | CMD_RX);
 781         else
 782                 reg_val |= (CMD_AFT_DAT_ENABLE | CMD_TX);
 783         writel(reg_val, &info->reg->command);
 784
 785         /* Setup DMA engine */
 786         reg_val = DMA_MST_CTRL_GO_ENABLE
 787                 | DMA_MST_CTRL_BURST_8WORDS
 788                 | DMA_MST_CTRL_EN_B_ENABLE;
 789         if (!is_writing)
 790                 reg_val |= DMA_MST_CTRL_DIR_READ;
 791         else
 792                 reg_val |= DMA_MST_CTRL_DIR_WRITE;
 793
 794         writel(reg_val, &info->reg->dma_mst_ctrl);
 795
 796         start_command(info->reg);
 797
 798         if (!nand_waitfor_cmd_completion(info->reg)) {
 799                 if (!is_writing)
 800                         printf("Read OOB of Page 0x%X timeout\n", page);
 801                 else
 802                         printf("Write OOB of Page 0x%X timeout\n", page);
 803                 return -EIO;
 804         }
 805
 806         bounce_buffer_stop(&bbstate_oob);
 807
 808         if (with_ecc && !is_writing) {
 809                 reg_val = (u32)check_ecc_error(info->reg, 0, 0,
 810                         (u8 *)(chip->oob_poi + free->offset),
 811                         chip->ecc.layout->oobavail);
 812                 if (reg_val & ECC_TAG_ERROR)
 813                         printf("Read OOB of Page 0x%X tag ECC error\n", page);
 814         }
 815         return 0;
 816 }
 817
 818 /**
 819  * OOB data read function
 820  *
 821  * @param mtd           mtd info structure
 822  * @param chip          nand chip info structure
 823  * @param page          page number to read
 824  */
 825 static int nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
 826         int page)
 827 {
 828         chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
 829         nand_rw_oob(mtd, chip, page, 0, 0);
 830         return 0;
 831 }
 832
 833 /**
 834  * OOB data write function
 835  *
 836  * @param mtd   mtd info structure
 837  * @param chip  nand chip info structure
 838  * @param page  page number to write
 839  * @return      0 when successfully completed
 840  *              -EINVAL when chip->oob_poi is not double-word aligned
 841  *              -EIO when command timeout
 842  */
 843 static int nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
 844         int page)
 845 {
 846         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
 847
 848         return nand_rw_oob(mtd, chip, page, 0, 1);
 849 }
 850
 851 /**
 852  * Set up NAND memory timings according to the provided parameters
 853  *
 854  * @param timing        Timing parameters
 855  * @param reg           NAND controller register address
 856  */
 857 static void setup_timing(unsigned timing[FDT_NAND_TIMING_COUNT],
 858                          struct nand_ctlr *reg)
 859 {
 860         u32 reg_val, clk_rate, clk_period, time_val;
 861
 862         clk_rate = (u32)clock_get_periph_rate(PERIPH_ID_NDFLASH,
 863                 CLOCK_ID_PERIPH) / 1000000;
 864         clk_period = 1000 / clk_rate;
 865         reg_val = ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) <<
 866                 TIMING_TRP_RESP_CNT_SHIFT) & TIMING_TRP_RESP_CNT_MASK;
 867         reg_val |= ((timing[FDT_NAND_TWB] / clk_period) <<
 868                 TIMING_TWB_CNT_SHIFT) & TIMING_TWB_CNT_MASK;
 869         time_val = timing[FDT_NAND_MAX_TCR_TAR_TRR] / clk_period;
 870         if (time_val > 2)
 871                 reg_val |= ((time_val - 2) << TIMING_TCR_TAR_TRR_CNT_SHIFT) &
 872                         TIMING_TCR_TAR_TRR_CNT_MASK;
 873         reg_val |= ((timing[FDT_NAND_TWHR] / clk_period) <<
 874                 TIMING_TWHR_CNT_SHIFT) & TIMING_TWHR_CNT_MASK;
 875         time_val = timing[FDT_NAND_MAX_TCS_TCH_TALS_TALH] / clk_period;
 876         if (time_val > 1)
 877                 reg_val |= ((time_val - 1) << TIMING_TCS_CNT_SHIFT) &
 878                         TIMING_TCS_CNT_MASK;
 879         reg_val |= ((timing[FDT_NAND_TWH] / clk_period) <<
 880                 TIMING_TWH_CNT_SHIFT) & TIMING_TWH_CNT_MASK;
 881         reg_val |= ((timing[FDT_NAND_TWP] / clk_period) <<
 882                 TIMING_TWP_CNT_SHIFT) & TIMING_TWP_CNT_MASK;
 883         reg_val |= ((timing[FDT_NAND_TRH] / clk_period) <<
 884                 TIMING_TRH_CNT_SHIFT) & TIMING_TRH_CNT_MASK;
 885         reg_val |= ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) <<
 886                 TIMING_TRP_CNT_SHIFT) & TIMING_TRP_CNT_MASK;
 887         writel(reg_val, &reg->timing);
 888
 889         reg_val = 0;
 890         time_val = timing[FDT_NAND_TADL] / clk_period;
 891         if (time_val > 2)
 892                 reg_val = (time_val - 2) & TIMING2_TADL_CNT_MASK;
 893         writel(reg_val, &reg->timing2);
 894 }
 895
 896 /**
 897  * Decode NAND parameters from the device tree
 898  *
 899  * @param dev           Driver model device
 900  * @param config        Device tree NAND configuration
 901  * @return 0 if ok, -ve on error (FDT_ERR_...)
 902  */
 903 static int fdt_decode_nand(struct udevice *dev, struct fdt_nand *config)
 904 {
 905         int err;
 906
 907         config->reg = (struct nand_ctlr *)dev_read_addr(dev);
 908         config->enabled = dev_read_enabled(dev);
 909         config->width = dev_read_u32_default(dev, "nvidia,nand-width", 8);
 910         err = gpio_request_by_name(dev, "nvidia,wp-gpios", 0, &config->wp_gpio,
 911                                    GPIOD_IS_OUT);
 912         if (err)
 913                 return err;
 914         err = dev_read_u32_array(dev, "nvidia,timing", config->timing,
 915                                  FDT_NAND_TIMING_COUNT);
 916         if (err < 0)
 917                 return err;
 918
 919         return 0;
 920 }
 921
 922 static int tegra_probe(struct udevice *dev)
 923 {
 924         struct tegra_nand_info *tegra = dev_get_priv(dev);
 925         struct nand_chip *nand = &tegra->nand_chip;
 926         struct nand_drv *info = &tegra->nand_ctrl;
 927         struct fdt_nand *config = &info->config;
 928         struct mtd_info *our_mtd;
 929         int ret;
 930
 931         if (fdt_decode_nand(dev, config)) {
 932                 printf("Could not decode nand-flash in device tree\n");
 933                 return -1;
 934         }
 935         if (!config->enabled)
 936                 return -1;
 937         info->reg = config->reg;
 938         nand->ecc.mode = NAND_ECC_HW;
 939         nand->ecc.layout = &eccoob;
 940
 941         nand->options = LP_OPTIONS;
 942         nand->cmdfunc = nand_command;
 943         nand->read_byte = read_byte;
 944         nand->read_buf = read_buf;
 945         nand->ecc.read_page = nand_read_page_hwecc;
 946         nand->ecc.write_page = nand_write_page_hwecc;
 947         nand->ecc.read_page_raw = nand_read_page_raw;
 948         nand->ecc.write_page_raw = nand_write_page_raw;
 949         nand->ecc.read_oob = nand_read_oob;
 950         nand->ecc.write_oob = nand_write_oob;
 951         nand->ecc.strength = 1;
 952         nand->select_chip = nand_select_chip;
 953         nand->dev_ready  = nand_dev_ready;
 954         nand_set_controller_data(nand, &tegra->nand_ctrl);
 955
 956         /* Disable subpage writes as we do not provide ecc->hwctl */
 957         nand->options |= NAND_NO_SUBPAGE_WRITE;
 958
 959         /* Adjust controller clock rate */
 960         clock_start_periph_pll(PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH, 52000000);
 961
 962         /* Adjust timing for NAND device */
 963         setup_timing(config->timing, info->reg);
 964
 965         dm_gpio_set_value(&config->wp_gpio, 1);
 966
 967         our_mtd = nand_to_mtd(nand);
 968         ret = nand_scan_ident(our_mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
 969         if (ret)
 970                 return ret;
 971
 972         nand->ecc.size = our_mtd->writesize;
 973         nand->ecc.bytes = our_mtd->oobsize;
 974
 975         ret = nand_scan_tail(our_mtd);
 976         if (ret)
 977                 return ret;
 978
 979         ret = nand_register(0, our_mtd);
 980         if (ret) {
 981                 dev_err(dev, "Failed to register MTD: %d\n", ret);
 982                 return ret;
 983         }
 984
 985         return 0;
 986 }
 987
 988 U_BOOT_DRIVER(tegra_nand) = {
 989         .name = "tegra-nand",
 990         .id = UCLASS_MTD,
 991         .of_match = tegra_nand_dt_ids,
 992         .probe = tegra_probe,
 993         .priv_auto      = sizeof(struct tegra_nand_info),
 994 };
 995
 996 void board_nand_init(void)
 997 {
 998         struct udevice *dev;
 999         int ret;
1000
1001         ret = uclass_get_device_by_driver(UCLASS_MTD,
1002                                           DM_DRIVER_GET(tegra_nand), &dev);
1003         if (ret && ret != -ENODEV)
1004                 pr_err("Failed to initialize %s. (error %d)\n", dev->name,
1005                        ret);
1006 }