1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017 Weidmüller Interface GmbH & Co. KG
7 * Copyright (C) 2011-2017 Xilinx, Inc. All rights reserved.
15 * (C) Copyright 2002-2004
19 * Texas Instruments <www.ti.com>
22 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
26 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
38 #include <asm/arch/hardware.h>
39 #include <asm/arch/clk.h>
41 DECLARE_GLOBAL_DATA_PTR;
44 u32 load; /* Timer Load Register */
45 u32 counter; /* Timer Counter Register */
46 u32 control; /* Timer Control Register */
49 static struct scu_timer *timer_base =
50 (struct scu_timer *)ZYNQ_SCUTIMER_BASEADDR;
52 #define SCUTIMER_CONTROL_PRESCALER_MASK 0x0000FF00 /* Prescaler */
53 #define SCUTIMER_CONTROL_PRESCALER_SHIFT 8
54 #define SCUTIMER_CONTROL_AUTO_RELOAD_MASK 0x00000002 /* Auto-reload */
55 #define SCUTIMER_CONTROL_ENABLE_MASK 0x00000001 /* Timer enable */
57 #define TIMER_LOAD_VAL 0xFFFFFFFF
58 #define TIMER_PRESCALE 255
62 const u32 emask = SCUTIMER_CONTROL_AUTO_RELOAD_MASK |
63 (TIMER_PRESCALE << SCUTIMER_CONTROL_PRESCALER_SHIFT) |
64 SCUTIMER_CONTROL_ENABLE_MASK;
70 ret = uclass_get_device_by_driver(UCLASS_CLK,
71 DM_DRIVER_GET(zynq_clk), &dev);
75 clk.id = cpu_6or4x_clk;
76 ret = clk_request(dev, &clk);
80 gd->cpu_clk = clk_get_rate(&clk);
84 gd->arch.timer_rate_hz = (gd->cpu_clk / 2) / (TIMER_PRESCALE + 1);
86 /* Load the timer counter register */
87 writel(0xFFFFFFFF, &timer_base->load);
90 * Start the A9Timer device
91 * Enable Auto reload mode, Clear prescaler control bits
92 * Set prescaler value, Enable the decrementer
94 clrsetbits_le32(&timer_base->control, SCUTIMER_CONTROL_PRESCALER_MASK,
98 gd->arch.lastinc = readl(&timer_base->counter) /
99 (gd->arch.timer_rate_hz / CONFIG_SYS_HZ);
106 * This function is derived from PowerPC code (timebase clock frequency).
107 * On ARM it returns the number of timer ticks per second.
109 ulong get_tbclk(void)
111 return gd->arch.timer_rate_hz;