arch/arm/mach-socfpga/clock_manager_agilex.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2019 Intel Corporation <www.intel.com>
   4  *
   5  */
   6
   7 #include <clk.h>
   8 #include <common.h>
   9 #include <dm.h>
  10 #include <log.h>
  11 #include <malloc.h>
  12 #include <asm/arch/clock_manager.h>
  13 #include <asm/arch/system_manager.h>
  14 #include <asm/io.h>
  15 #include <dt-bindings/clock/agilex-clock.h>
  16
  17 DECLARE_GLOBAL_DATA_PTR;
  18
  19 static ulong cm_get_rate_dm(u32 id)
  20 {
  21         struct udevice *dev;
  22         struct clk clk;
  23         ulong rate;
  24         int ret;
  25
  26         ret = uclass_get_device_by_driver(UCLASS_CLK,
  27                                           DM_DRIVER_GET(socfpga_agilex_clk),
  28                                           &dev);
  29         if (ret)
  30                 return 0;
  31
  32         clk.id = id;
  33         ret = clk_request(dev, &clk);
  34         if (ret < 0)
  35                 return 0;
  36
  37         rate = clk_get_rate(&clk);
  38
  39         clk_free(&clk);
  40
  41         if ((rate == (unsigned long)-ENOSYS) ||
  42             (rate == (unsigned long)-ENXIO) ||
  43             (rate == (unsigned long)-EIO)) {
  44                 debug("%s id %u: clk_get_rate err: %ld\n",
  45                       __func__, id, rate);
  46                 return 0;
  47         }
  48
  49         return rate;
  50 }
  51
  52 static u32 cm_get_rate_dm_khz(u32 id)
  53 {
  54         return cm_get_rate_dm(id) / 1000;
  55 }
  56
  57 unsigned long cm_get_mpu_clk_hz(void)
  58 {
  59         return cm_get_rate_dm(AGILEX_MPU_CLK);
  60 }
  61
  62 unsigned int cm_get_l4_sys_free_clk_hz(void)
  63 {
  64         return cm_get_rate_dm(AGILEX_L4_SYS_FREE_CLK);
  65 }
  66
  67 u32 cm_get_qspi_controller_clk_hz(void)
  68 {
  69         return readl(socfpga_get_sysmgr_addr() +
  70                      SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
  71 }
  72
  73 void cm_print_clock_quick_summary(void)
  74 {
  75         printf("MPU       %10d kHz\n",
  76                cm_get_rate_dm_khz(AGILEX_MPU_CLK));
  77         printf("L4 Main     %8d kHz\n",
  78                cm_get_rate_dm_khz(AGILEX_L4_MAIN_CLK));
  79         printf("L4 sys free %8d kHz\n",
  80                cm_get_rate_dm_khz(AGILEX_L4_SYS_FREE_CLK));
  81         printf("L4 MP       %8d kHz\n",
  82                cm_get_rate_dm_khz(AGILEX_L4_MP_CLK));
  83         printf("L4 SP       %8d kHz\n",
  84                cm_get_rate_dm_khz(AGILEX_L4_SP_CLK));
  85         printf("SDMMC       %8d kHz\n",
  86                cm_get_rate_dm_khz(AGILEX_SDMMC_CLK));
  87 }