arch/arm/mach-k3/j721s2/j721s2_init.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * J721E: SoC specific initialization
   4  *
   5  * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
   6  *      David Huang <[email protected]>
   7  */
   8
   9 #include <init.h>
  10 #include <spl.h>
  11 #include <asm/io.h>
  12 #include <asm/armv7_mpu.h>
  13 #include <asm/arch/hardware.h>
  14 #include <linux/soc/ti/ti_sci_protocol.h>
  15 #include <dm.h>
  16 #include <dm/uclass-internal.h>
  17 #include <dm/pinctrl.h>
  18 #include <dm/root.h>
  19 #include <mmc.h>
  20 #include <remoteproc.h>
  21
  22 #include "../sysfw-loader.h"
  23 #include "../common.h"
  24
  25 /* NAVSS North Bridge (NB) */
  26 #define NAVSS0_NBSS_NB0_CFG_MMRS                0x03702000
  27 #define NAVSS0_NBSS_NB1_CFG_MMRS                0x03703000
  28 #define NAVSS0_NBSS_NB0_CFG_NB_THREADMAP        (NAVSS0_NBSS_NB0_CFG_MMRS + 0x10)
  29 #define NAVSS0_NBSS_NB1_CFG_NB_THREADMAP        (NAVSS0_NBSS_NB1_CFG_MMRS + 0x10)
  30 /*
  31  * Thread Map for North Bridge Configuration
  32  * Each bit is for each VBUSM source.
  33  * Bit[0] maps orderID 0-3 to VBUSM.C thread number
  34  * Bit[1] maps orderID 4-9 to VBUSM.C thread number
  35  * Bit[2] maps orderID 10-15 to VBUSM.C thread number
  36  * When bit has value 0: VBUSM.C thread 0 (non-real time traffic)
  37  * When bit has value 1: VBUSM.C thread 2 (real time traffic)
  38  */
  39 #define NB_THREADMAP_BIT0                               BIT(0)
  40 #define NB_THREADMAP_BIT1                               BIT(1)
  41 #define NB_THREADMAP_BIT2                               BIT(2)
  42
  43 struct fwl_data cbass_hc_cfg0_fwls[] = {
  44         { "PCIE0_CFG", 2577, 7 },
  45         { "EMMC8SS0_CFG", 2579, 4 },
  46         { "USB3SS0_CORE", 2580, 4 },
  47         { "USB3SS1_CORE", 2581, 1 },
  48 }, cbass_hc2_fwls[] = {
  49         { "PCIE0", 2547, 24 },
  50         { "HC2_WIZ16B8M4CT2", 2552, 1 },
  51 }, cbass_rc_cfg0_fwls[] = {
  52         { "EMMCSD4SS0_CFG", 2400, 4 },
  53 }, infra_cbass0_fwls[] = {
  54         { "PSC0", 5, 1 },
  55         { "PLL_CTRL0", 6, 1 },
  56         { "PLL_MMR0", 8, 26 },
  57         { "CTRL_MMR0", 9, 16 },
  58         { "GPIO0", 16, 1 },
  59 }, mcu_cbass0_fwls[] = {
  60         { "MCU_R5FSS0_CORE0", 1024, 4 },
  61         { "MCU_R5FSS0_CORE0_CFG", 1025, 3 },
  62         { "MCU_R5FSS0_CORE1", 1028, 4 },
  63         { "MCU_R5FSS0_CORE1_CFG", 1029, 1 },
  64         { "MCU_FSS0_CFG", 1032, 12 },
  65         { "MCU_FSS0_S1", 1033, 8 },
  66         { "MCU_FSS0_S0", 1036, 8 },
  67         { "MCU_PSROM49152X32", 1048, 1 },
  68         { "MCU_MSRAM128KX64", 1050, 8 },
  69         { "MCU_MSRAM128KX64_CFG", 1051, 1 },
  70         { "MCU_TIMER0", 1056, 1 },
  71         { "MCU_TIMER9", 1065, 1 },
  72         { "MCU_USART0", 1120, 1 },
  73         { "MCU_I2C0", 1152, 1 },
  74         { "MCU_CTRL_MMR0", 1200, 8 },
  75         { "MCU_PLL_MMR0", 1201, 3 },
  76         { "MCU_CPSW0", 1220, 2 },
  77 }, wkup_cbass0_fwls[] = {
  78         { "WKUP_PSC0", 129, 1 },
  79         { "WKUP_PLL_CTRL0", 130, 1 },
  80         { "WKUP_CTRL_MMR0", 131, 16 },
  81         { "WKUP_GPIO0", 132, 1 },
  82         { "WKUP_I2C0", 144, 1 },
  83         { "WKUP_USART0", 160, 1 },
  84 }, navss_cbass0_fwls[] = {
  85         { "NACSS_VIRT0", 6253, 1 },
  86 };
  87
  88 static void ctrl_mmr_unlock(void)
  89 {
  90         /* Unlock all WKUP_CTRL_MMR0 module registers */
  91         mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
  92         mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
  93         mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
  94         mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
  95         mmr_unlock(WKUP_CTRL_MMR0_BASE, 4);
  96         mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
  97         mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
  98
  99         /* Unlock all MCU_CTRL_MMR0 module registers */
 100         mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
 101         mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
 102         mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
 103         mmr_unlock(MCU_CTRL_MMR0_BASE, 3);
 104         mmr_unlock(MCU_CTRL_MMR0_BASE, 4);
 105
 106         /* Unlock all CTRL_MMR0 module registers */
 107         mmr_unlock(CTRL_MMR0_BASE, 0);
 108         mmr_unlock(CTRL_MMR0_BASE, 1);
 109         mmr_unlock(CTRL_MMR0_BASE, 2);
 110         mmr_unlock(CTRL_MMR0_BASE, 3);
 111         mmr_unlock(CTRL_MMR0_BASE, 5);
 112         mmr_unlock(CTRL_MMR0_BASE, 7);
 113 }
 114
 115 void k3_mmc_stop_clock(void)
 116 {
 117         if (IS_ENABLED(CONFIG_K3_LOAD_SYSFW)) {
 118                 if (spl_boot_device() == BOOT_DEVICE_MMC1) {
 119                         struct mmc *mmc = find_mmc_device(0);
 120
 121                         if (!mmc)
 122                                 return;
 123
 124                         mmc->saved_clock = mmc->clock;
 125                         mmc_set_clock(mmc, 0, true);
 126                 }
 127         }
 128 }
 129
 130 void k3_mmc_restart_clock(void)
 131 {
 132         if (IS_ENABLED(CONFIG_K3_LOAD_SYSFW)) {
 133                 if (spl_boot_device() == BOOT_DEVICE_MMC1) {
 134                         struct mmc *mmc = find_mmc_device(0);
 135
 136                         if (!mmc)
 137                                 return;
 138
 139                         mmc_set_clock(mmc, mmc->saved_clock, false);
 140                 }
 141         }
 142 }
 143
 144 /* Setup North Bridge registers to map ORDERID 10-15 to RT traffic */
 145 static void setup_navss_nb(void)
 146 {
 147         writel(NB_THREADMAP_BIT1, (uintptr_t)NAVSS0_NBSS_NB0_CFG_NB_THREADMAP);
 148         writel(NB_THREADMAP_BIT2, (uintptr_t)NAVSS0_NBSS_NB1_CFG_NB_THREADMAP);
 149 }
 150
 151 /*
 152  * This uninitialized global variable would normal end up in the .bss section,
 153  * but the .bss is cleared between writing and reading this variable, so move
 154  * it to the .data section.
 155  */
 156 u32 bootindex __attribute__((section(".data")));
 157 static struct rom_extended_boot_data bootdata __section(".data");
 158
 159 static void store_boot_info_from_rom(void)
 160 {
 161         bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
 162         memcpy(&bootdata, (uintptr_t *)ROM_EXTENDED_BOOT_DATA_INFO,
 163                sizeof(struct rom_extended_boot_data));
 164 }
 165
 166 void k3_spl_init(void)
 167 {
 168         struct udevice *dev;
 169         int ret;
 170         /*
 171          * Cannot delay this further as there is a chance that
 172          * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
 173          */
 174         store_boot_info_from_rom();
 175
 176         /* Make all control module registers accessible */
 177         ctrl_mmr_unlock();
 178
 179         if (IS_ENABLED(CONFIG_CPU_V7R)) {
 180                 disable_linefill_optimization();
 181                 setup_k3_mpu_regions();
 182         }
 183
 184         /* Init DM early */
 185         spl_early_init();
 186
 187         /* Prepare console output */
 188         preloader_console_init();
 189
 190         if (IS_ENABLED(CONFIG_K3_LOAD_SYSFW)) {
 191                 /*
 192                  * Process pinctrl for the serial0 a.k.a. WKUP_UART0 module and continue
 193                  * regardless of the result of pinctrl. Do this without probing the
 194                  * device, but instead by searching the device that would request the
 195                  * given sequence number if probed. The UART will be used by the system
 196                  * firmware (SYSFW) image for various purposes and SYSFW depends on us
 197                  * to initialize its pin settings.
 198                  */
 199                 ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, &dev);
 200                 if (!ret)
 201                         pinctrl_select_state(dev, "default");
 202
 203                 /*
 204                  * Load, start up, and configure system controller firmware. Provide
 205                  * the U-Boot console init function to the SYSFW post-PM configuration
 206                  * callback hook, effectively switching on (or over) the console
 207                  * output.
 208                  */
 209                 k3_sysfw_loader(is_rom_loaded_sysfw(&bootdata),
 210                                 k3_mmc_stop_clock, k3_mmc_restart_clock);
 211
 212                 if (IS_ENABLED(CONFIG_SPL_CLK_K3)) {
 213                         /*
 214                          * Force probe of clk_k3 driver here to ensure basic default clock
 215                          * configuration is always done for enabling PM services.
 216                          */
 217                         ret = uclass_get_device_by_driver(UCLASS_CLK,
 218                                                           DM_DRIVER_GET(ti_clk),
 219                                                           &dev);
 220                         if (ret)
 221                                 panic("Failed to initialize clk-k3!\n");
 222                 }
 223
 224                 remove_fwl_configs(cbass_hc_cfg0_fwls, ARRAY_SIZE(cbass_hc_cfg0_fwls));
 225                 remove_fwl_configs(cbass_hc2_fwls, ARRAY_SIZE(cbass_hc2_fwls));
 226                 remove_fwl_configs(cbass_rc_cfg0_fwls, ARRAY_SIZE(cbass_rc_cfg0_fwls));
 227                 remove_fwl_configs(infra_cbass0_fwls, ARRAY_SIZE(infra_cbass0_fwls));
 228                 remove_fwl_configs(mcu_cbass0_fwls, ARRAY_SIZE(mcu_cbass0_fwls));
 229                 remove_fwl_configs(wkup_cbass0_fwls, ARRAY_SIZE(wkup_cbass0_fwls));
 230                 remove_fwl_configs(navss_cbass0_fwls, ARRAY_SIZE(navss_cbass0_fwls));
 231         }
 232
 233         /* Output System Firmware version info */
 234         k3_sysfw_print_ver();
 235 }
 236
 237 bool check_rom_loaded_sysfw(void)
 238 {
 239         return is_rom_loaded_sysfw(&bootdata);
 240 }
 241
 242 void k3_mem_init(void)
 243 {
 244         struct udevice *dev;
 245         int ret;
 246
 247         if (IS_ENABLED(CONFIG_K3_J721E_DDRSS)) {
 248                 ret = uclass_get_device_by_name(UCLASS_MISC, "msmc", &dev);
 249                 if (ret)
 250                         panic("Probe of msmc failed: %d\n", ret);
 251
 252                 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
 253                 if (ret)
 254                         panic("DRAM 0 init failed: %d\n", ret);
 255
 256                 ret = uclass_next_device_err(&dev);
 257                 if (ret && ret != -ENODEV)
 258                         panic("DRAM 1 init failed: %d\n", ret);
 259         }
 260         spl_enable_cache();
 261 }
 262
 263 /* Support for the various EVM / SK families */
 264 #if defined(CONFIG_SPL_OF_LIST) && defined(CONFIG_TI_I2C_BOARD_DETECT)
 265 void do_dt_magic(void)
 266 {
 267         int ret, rescan, mmc_dev = -1;
 268         static struct mmc *mmc;
 269
 270         do_board_detect();
 271
 272         /*
 273          * Board detection has been done.
 274          * Let us see if another dtb wouldn't be a better match
 275          * for our board
 276          */
 277         if (IS_ENABLED(CONFIG_CPU_V7R)) {
 278                 ret = fdtdec_resetup(&rescan);
 279                 if (!ret && rescan) {
 280                         dm_uninit();
 281                         dm_init_and_scan(true);
 282                 }
 283         }
 284
 285         /*
 286          * Because of multi DTB configuration, the MMC device has
 287          * to be re-initialized after reconfiguring FDT inorder to
 288          * boot from MMC. Do this when boot mode is MMC and ROM has
 289          * not loaded SYSFW.
 290          */
 291         switch (spl_boot_device()) {
 292         case BOOT_DEVICE_MMC1:
 293                 mmc_dev = 0;
 294                 break;
 295         case BOOT_DEVICE_MMC2:
 296         case BOOT_DEVICE_MMC2_2:
 297                 mmc_dev = 1;
 298                 break;
 299         }
 300
 301         if (mmc_dev > 0 && !check_rom_loaded_sysfw()) {
 302                 ret = mmc_init_device(mmc_dev);
 303                 if (!ret) {
 304                         mmc = find_mmc_device(mmc_dev);
 305                         if (mmc) {
 306                                 ret = mmc_init(mmc);
 307                                 if (ret)
 308                                         printf("mmc init failed with error: %d\n", ret);
 309                         }
 310                 }
 311         }
 312 }
 313 #endif
 314
 315 #ifdef CONFIG_XPL_BUILD
 316 void board_init_f(ulong dummy)
 317 {
 318         struct udevice *dev;
 319         int ret;
 320
 321         k3_spl_init();
 322 #if defined(CONFIG_SPL_OF_LIST) && defined(CONFIG_TI_I2C_BOARD_DETECT)
 323         do_dt_magic();
 324 #endif
 325         k3_mem_init();
 326
 327         if (IS_ENABLED(CONFIG_CPU_V7R))
 328                 setup_navss_nb();
 329
 330         setup_qos();
 331
 332         if (IS_ENABLED(CONFIG_CPU_V7R) && IS_ENABLED(CONFIG_K3_AVS0)) {
 333                 ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(k3_avs),
 334                                                   &dev);
 335                 if (ret)
 336                         printf("AVS init failed: %d\n", ret);
 337         }
 338 }
 339 #endif
 340
 341 u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
 342 {
 343         switch (boot_device) {
 344         case BOOT_DEVICE_MMC1:
 345                 return MMCSD_MODE_EMMCBOOT;
 346         case BOOT_DEVICE_MMC2:
 347                 return MMCSD_MODE_FS;
 348         default:
 349                 return MMCSD_MODE_RAW;
 350         }
 351 }
 352
 353 static u32 __get_backup_bootmedia(u32 main_devstat)
 354 {
 355         u32 bkup_boot = (main_devstat & MAIN_DEVSTAT_BKUP_BOOTMODE_MASK) >>
 356                         MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT;
 357
 358         switch (bkup_boot) {
 359         case BACKUP_BOOT_DEVICE_USB:
 360                 return BOOT_DEVICE_DFU;
 361         case BACKUP_BOOT_DEVICE_UART:
 362                 return BOOT_DEVICE_UART;
 363         case BACKUP_BOOT_DEVICE_ETHERNET:
 364                 return BOOT_DEVICE_ETHERNET;
 365         case BACKUP_BOOT_DEVICE_MMC2:
 366         {
 367                 u32 port = (main_devstat & MAIN_DEVSTAT_BKUP_MMC_PORT_MASK) >>
 368                             MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT;
 369                 if (port == 0x0)
 370                         return BOOT_DEVICE_MMC1;
 371                 return BOOT_DEVICE_MMC2;
 372         }
 373         case BACKUP_BOOT_DEVICE_SPI:
 374                 return BOOT_DEVICE_SPI;
 375         case BACKUP_BOOT_DEVICE_I2C:
 376                 return BOOT_DEVICE_I2C;
 377         }
 378
 379         return BOOT_DEVICE_RAM;
 380 }
 381
 382 static u32 __get_primary_bootmedia(u32 main_devstat, u32 wkup_devstat)
 383 {
 384         u32 bootmode = (wkup_devstat & WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
 385                         WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
 386
 387         bootmode |= (main_devstat & MAIN_DEVSTAT_BOOT_MODE_B_MASK) <<
 388                         BOOT_MODE_B_SHIFT;
 389
 390         if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI ||
 391             bootmode == BOOT_DEVICE_XSPI)
 392                 bootmode = BOOT_DEVICE_SPI;
 393
 394         if (bootmode == BOOT_DEVICE_MMC2) {
 395                 u32 port = (main_devstat &
 396                             MAIN_DEVSTAT_PRIM_BOOTMODE_MMC_PORT_MASK) >>
 397                            MAIN_DEVSTAT_PRIM_BOOTMODE_PORT_SHIFT;
 398                 if (port == 0x0)
 399                         bootmode = BOOT_DEVICE_MMC1;
 400         }
 401
 402         return bootmode;
 403 }
 404
 405 u32 spl_boot_device(void)
 406 {
 407         u32 wkup_devstat = readl(CTRLMMR_WKUP_DEVSTAT);
 408         u32 main_devstat;
 409
 410         if (wkup_devstat & WKUP_DEVSTAT_MCU_OMLY_MASK) {
 411                 printf("ERROR: MCU only boot is not yet supported\n");
 412                 return BOOT_DEVICE_RAM;
 413         }
 414
 415         /* MAIN CTRL MMR can only be read if MCU ONLY is 0 */
 416         main_devstat = readl(CTRLMMR_MAIN_DEVSTAT);
 417
 418         if (bootindex == K3_PRIMARY_BOOTMODE)
 419                 return __get_primary_bootmedia(main_devstat, wkup_devstat);
 420         else
 421                 return __get_backup_bootmedia(main_devstat);
 422 }